[thirdparty/qemu.git] / include / hw / sh4 / sh_intc.h

#ifndef __SH_INTC_H__
#define __SH_INTC_H__

#include "qemu-common.h"
#include "hw/irq.h"
#include "exec/address-spaces.h"

typedef unsigned char intc_enum;

struct intc_vect {
    intc_enum enum_id;
    unsigned short vect;
};

#define INTC_VECT(enum_id, vect) { enum_id, vect }

struct intc_group {
    intc_enum enum_id;
    intc_enum enum_ids[32];
};

#define INTC_GROUP(enum_id, ...) { enum_id, {  __VA_ARGS__ } }

struct intc_mask_reg {
    unsigned long set_reg, clr_reg, reg_width;
    intc_enum enum_ids[32];
    unsigned long value;
};

struct intc_prio_reg {
    unsigned long set_reg, clr_reg, reg_width, field_width;
    intc_enum enum_ids[16];
    unsigned long value;
};

#define _INTC_ARRAY(a) a, ARRAY_SIZE(a)

struct intc_source {
    unsigned short vect;
    intc_enum next_enum_id;

    int asserted; /* emulates the interrupt signal line from device to intc */
    int enable_count;
    int enable_max;
    int pending; /* emulates the result of signal and masking */
    struct intc_desc *parent;
};

struct intc_desc {
    MemoryRegion iomem;
    MemoryRegion *iomem_aliases;
    qemu_irq *irqs;
    struct intc_source *sources;
    int nr_sources;
    struct intc_mask_reg *mask_regs;
    int nr_mask_regs;
    struct intc_prio_reg *prio_regs;
    int nr_prio_regs;
    int pending; /* number of interrupt sources that has pending set */
};

int sh_intc_get_pending_vector(struct intc_desc *desc, int imask);
struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id);
void sh_intc_toggle_source(struct intc_source *source,
			   int enable_adj, int assert_adj);

void sh_intc_register_sources(struct intc_desc *desc,
			      struct intc_vect *vectors,
			      int nr_vectors,
			      struct intc_group *groups,
			      int nr_groups);

int sh_intc_init(MemoryRegion *sysmem,
                 struct intc_desc *desc,
		 int nr_sources,
		 struct intc_mask_reg *mask_regs,
		 int nr_mask_regs,
		 struct intc_prio_reg *prio_regs,
		 int nr_prio_regs);

void sh_intc_set_irl(void *opaque, int n, int level);

#endif /* __SH_INTC_H__ */
Commit	Line	Data
80f515e6 AZ	1	#ifndef __SH_INTC_H__
	2	#define __SH_INTC_H__
	3
96e2fc41	4	#include "qemu-common.h"
83c9f4ca	5	#include "hw/irq.h"
022c62cb	6	#include "exec/address-spaces.h"
96e2fc41	7
80f515e6 AZ	8	typedef unsigned char intc_enum;
	9
	10	struct intc_vect {
	11	intc_enum enum_id;
	12	unsigned short vect;
	13	};
	14
	15	#define INTC_VECT(enum_id, vect) { enum_id, vect }
	16
	17	struct intc_group {
	18	intc_enum enum_id;
	19	intc_enum enum_ids[32];
	20	};
	21
001faf32	22	#define INTC_GROUP(enum_id, ...) { enum_id, { __VA_ARGS__ } }
80f515e6 AZ	23
	24	struct intc_mask_reg {
	25	unsigned long set_reg, clr_reg, reg_width;
	26	intc_enum enum_ids[32];
	27	unsigned long value;
	28	};
	29
	30	struct intc_prio_reg {
	31	unsigned long set_reg, clr_reg, reg_width, field_width;
	32	intc_enum enum_ids[16];
	33	unsigned long value;
	34	};
	35
b1503cda	36	#define _INTC_ARRAY(a) a, ARRAY_SIZE(a)
80f515e6 AZ	37
	38	struct intc_source {
	39	unsigned short vect;
	40	intc_enum next_enum_id;
	41
e96e2044	42	int asserted; /* emulates the interrupt signal line from device to intc */
80f515e6 AZ	43	int enable_count;
80f515e6 AZ	44	int enable_max;
e96e2044 TS	45	int pending; /* emulates the result of signal and masking */
e96e2044 TS	46	struct intc_desc *parent;
80f515e6 AZ	47	};
	48
	49	struct intc_desc {
b279e5ef BC	50	MemoryRegion iomem;
b279e5ef BC	51	MemoryRegion *iomem_aliases;
96e2fc41	52	qemu_irq *irqs;
80f515e6 AZ	53	struct intc_source *sources;
	54	int nr_sources;
	55	struct intc_mask_reg *mask_regs;
	56	int nr_mask_regs;
	57	struct intc_prio_reg *prio_regs;
	58	int nr_prio_regs;
e96e2044	59	int pending; /* number of interrupt sources that has pending set */
80f515e6 AZ	60	};
80f515e6 AZ	61
e96e2044	62	int sh_intc_get_pending_vector(struct intc_desc *desc, int imask);
80f515e6	63	struct intc_source sh_intc_source(struct intc_desc desc, intc_enum id);
e96e2044 TS	64	void sh_intc_toggle_source(struct intc_source *source,
e96e2044 TS	65	int enable_adj, int assert_adj);
80f515e6 AZ	66
	67	void sh_intc_register_sources(struct intc_desc *desc,
	68	struct intc_vect *vectors,
	69	int nr_vectors,
	70	struct intc_group *groups,
	71	int nr_groups);
	72
b279e5ef BC	73	int sh_intc_init(MemoryRegion *sysmem,
b279e5ef BC	74	struct intc_desc *desc,
80f515e6 AZ	75	int nr_sources,
	76	struct intc_mask_reg *mask_regs,
	77	int nr_mask_regs,
	78	struct intc_prio_reg *prio_regs,
	79	int nr_prio_regs);
	80
c6d86a33 AZ	81	void sh_intc_set_irl(void *opaque, int n, int level);
c6d86a33 AZ	82
80f515e6	83	#endif /* __SH_INTC_H__ */