[thirdparty/qemu.git] / include / hw / timer / a9gtimer.h

/*
 * Global peripheral timer block for ARM A9MP
 *
 * (C) 2013 Xilinx Inc.
 *
 * Written by François LEGAL
 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef A9GTIMER_H
#define A9GTIMER_H

#include "hw/sysbus.h"
#include "qom/object.h"

#define A9_GTIMER_MAX_CPUS 4

#define TYPE_A9_GTIMER "arm.cortex-a9-global-timer"
typedef struct A9GTimerState A9GTimerState;
#define A9_GTIMER(obj) OBJECT_CHECK(A9GTimerState, (obj), TYPE_A9_GTIMER)

#define R_COUNTER_LO                0x00
#define R_COUNTER_HI                0x04

#define R_CONTROL                   0x08
#define R_CONTROL_TIMER_ENABLE      (1 << 0)
#define R_CONTROL_COMP_ENABLE       (1 << 1)
#define R_CONTROL_IRQ_ENABLE        (1 << 2)
#define R_CONTROL_AUTO_INCREMENT    (1 << 3)
#define R_CONTROL_PRESCALER_SHIFT   8
#define R_CONTROL_PRESCALER_LEN     8
#define R_CONTROL_PRESCALER_MASK    (((1 << R_CONTROL_PRESCALER_LEN) - 1) << \
                                     R_CONTROL_PRESCALER_SHIFT)

#define R_CONTROL_BANKED            (R_CONTROL_COMP_ENABLE | \
                                     R_CONTROL_IRQ_ENABLE | \
                                     R_CONTROL_AUTO_INCREMENT)
#define R_CONTROL_NEEDS_SYNC        (R_CONTROL_TIMER_ENABLE | \
                                     R_CONTROL_PRESCALER_MASK)

#define R_INTERRUPT_STATUS          0x0C
#define R_COMPARATOR_LO             0x10
#define R_COMPARATOR_HI             0x14
#define R_AUTO_INCREMENT            0x18

typedef struct A9GTimerPerCPU A9GTimerPerCPU;

struct A9GTimerPerCPU {
    A9GTimerState *parent;

    uint32_t control; /* only per cpu banked bits valid */
    uint64_t compare;
    uint32_t status;
    uint32_t inc;

    MemoryRegion iomem;
    qemu_irq irq; /* PPI interrupts */
};

struct A9GTimerState {
    /*< private >*/
    SysBusDevice parent_obj;
    /*< public >*/

    MemoryRegion iomem;
    /* static props */
    uint32_t num_cpu;

    QEMUTimer *timer;

    uint64_t counter; /* current timer value */

    uint64_t ref_counter;
    uint64_t cpu_ref_time; /* the cpu time as of last update of ref_counter */
    uint32_t control; /* only non per cpu banked bits valid */

    A9GTimerPerCPU per_cpu[A9_GTIMER_MAX_CPUS];
};

typedef struct A9GTimerUpdate {
    uint64_t now;
    uint64_t new;
} A9GTimerUpdate;

#endif /* A9GTIMER_H */
Commit	Line	Data
c21c3b53 PC	1	/*
	2	* Global peripheral timer block for ARM A9MP
	3	*
	4	* (C) 2013 Xilinx Inc.
	5	*
	6	* Written by François LEGAL
	7	* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along
	20	* with this program; if not, see <http://www.gnu.org/licenses/>.
	21	*/
	22
121d0712 MA	23	#ifndef A9GTIMER_H
121d0712 MA	24	#define A9GTIMER_H
c21c3b53 PC	25
c21c3b53 PC	26	#include "hw/sysbus.h"
db1015e9	27	#include "qom/object.h"
c21c3b53 PC	28
	29	#define A9_GTIMER_MAX_CPUS 4
	30
	31	#define TYPE_A9_GTIMER "arm.cortex-a9-global-timer"
db1015e9	32	typedef struct A9GTimerState A9GTimerState;
c21c3b53 PC	33	#define A9_GTIMER(obj) OBJECT_CHECK(A9GTimerState, (obj), TYPE_A9_GTIMER)
	34
	35	#define R_COUNTER_LO 0x00
	36	#define R_COUNTER_HI 0x04
	37
	38	#define R_CONTROL 0x08
	39	#define R_CONTROL_TIMER_ENABLE (1 << 0)
	40	#define R_CONTROL_COMP_ENABLE (1 << 1)
	41	#define R_CONTROL_IRQ_ENABLE (1 << 2)
786f9ce2	42	#define R_CONTROL_AUTO_INCREMENT (1 << 3)
c21c3b53 PC	43	#define R_CONTROL_PRESCALER_SHIFT 8
	44	#define R_CONTROL_PRESCALER_LEN 8
	45	#define R_CONTROL_PRESCALER_MASK (((1 << R_CONTROL_PRESCALER_LEN) - 1) << \
	46	R_CONTROL_PRESCALER_SHIFT)
	47
	48	#define R_CONTROL_BANKED (R_CONTROL_COMP_ENABLE \| \
	49	R_CONTROL_IRQ_ENABLE \| \
	50	R_CONTROL_AUTO_INCREMENT)
	51	#define R_CONTROL_NEEDS_SYNC (R_CONTROL_TIMER_ENABLE \| \
	52	R_CONTROL_PRESCALER_MASK)
	53
	54	#define R_INTERRUPT_STATUS 0x0C
	55	#define R_COMPARATOR_LO 0x10
	56	#define R_COMPARATOR_HI 0x14
	57	#define R_AUTO_INCREMENT 0x18
	58
	59	typedef struct A9GTimerPerCPU A9GTimerPerCPU;
c21c3b53 PC	60
	61	struct A9GTimerPerCPU {
	62	A9GTimerState *parent;
	63
	64	uint32_t control; /* only per cpu banked bits valid */
	65	uint64_t compare;
	66	uint32_t status;
	67	uint32_t inc;
	68
	69	MemoryRegion iomem;
	70	qemu_irq irq; /* PPI interrupts */
	71	};
	72
	73	struct A9GTimerState {
	74	/< private >/
	75	SysBusDevice parent_obj;
	76	/< public >/
	77
	78	MemoryRegion iomem;
	79	/* static props */
	80	uint32_t num_cpu;
	81
	82	QEMUTimer *timer;
	83
	84	uint64_t counter; /* current timer value */
	85
	86	uint64_t ref_counter;
	87	uint64_t cpu_ref_time; /* the cpu time as of last update of ref_counter */
	88	uint32_t control; /* only non per cpu banked bits valid */
	89
	90	A9GTimerPerCPU per_cpu[A9_GTIMER_MAX_CPUS];
	91	};
	92
	93	typedef struct A9GTimerUpdate {
	94	uint64_t now;
	95	uint64_t new;
	96	} A9GTimerUpdate;
	97
121d0712	98	#endif /* A9GTIMER_H */