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214ec6bb WD |
1 | /*----------------------------------------------------------------------------+ |
2 | | | |
65bd0e28 WD |
3 | | This source code has been made available to you by IBM on an AS-IS |
4 | | basis. Anyone receiving this source is licensed under IBM | |
5 | | copyrights to use it in any way he or she deems fit, including | |
6 | | copying it, modifying it, compiling it, and redistributing it either | |
7 | | with or without modifications. No license under IBM patents or | |
8 | | patent applications is to be implied by the copyright license. | |
214ec6bb | 9 | | |
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10 | | Any user of this software should understand that IBM cannot provide |
11 | | technical support for this software and will not be responsible for | |
12 | | any consequences resulting from the use of this software. | |
214ec6bb | 13 | | |
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14 | | Any person who transfers this source code or any derivative work |
15 | | must include the IBM copyright notice, this paragraph, and the | |
16 | | preceding two paragraphs in the transferred software. | |
214ec6bb | 17 | | |
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18 | | COPYRIGHT I B M CORPORATION 1999 |
19 | | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
214ec6bb WD |
20 | +----------------------------------------------------------------------------*/ |
21 | /*----------------------------------------------------------------------------+ | |
22 | | | |
65bd0e28 | 23 | | File Name: miiphy.h |
214ec6bb | 24 | | |
65bd0e28 | 25 | | Function: Include file defining PHY registers. |
214ec6bb | 26 | | |
65bd0e28 | 27 | | Author: Mark Wisner |
214ec6bb | 28 | | |
214ec6bb WD |
29 | +----------------------------------------------------------------------------*/ |
30 | #ifndef _miiphy_h_ | |
31 | #define _miiphy_h_ | |
32 | ||
63ff004c | 33 | #include <net.h> |
214ec6bb | 34 | |
298035df LJ |
35 | int miiphy_read (char *devname, unsigned char addr, unsigned char reg, |
36 | unsigned short *value); | |
37 | int miiphy_write (char *devname, unsigned char addr, unsigned char reg, | |
38 | unsigned short value); | |
39 | int miiphy_info (char *devname, unsigned char addr, unsigned int *oui, | |
40 | unsigned char *model, unsigned char *rev); | |
41 | int miiphy_reset (char *devname, unsigned char addr); | |
42 | int miiphy_speed (char *devname, unsigned char addr); | |
43 | int miiphy_duplex (char *devname, unsigned char addr); | |
fc3e2165 | 44 | #ifdef CFG_FAULT_ECHO_LINK_DOWN |
298035df | 45 | int miiphy_link (char *devname, unsigned char addr); |
fc3e2165 | 46 | #endif |
214ec6bb | 47 | |
298035df | 48 | void miiphy_init (void); |
d9785c14 | 49 | |
298035df LJ |
50 | void miiphy_register (char *devname, |
51 | int (*read) (char *devname, unsigned char addr, | |
52 | unsigned char reg, unsigned short *value), | |
53 | int (*write) (char *devname, unsigned char addr, | |
54 | unsigned char reg, unsigned short value)); | |
63ff004c | 55 | |
298035df LJ |
56 | int miiphy_set_current_dev (char *devname); |
57 | char *miiphy_get_current_dev (void); | |
63ff004c | 58 | |
298035df | 59 | void miiphy_listdev (void); |
63ff004c MB |
60 | |
61 | #define BB_MII_DEVNAME "bbmii" | |
62 | ||
63 | int bb_miiphy_read (char *devname, unsigned char addr, | |
298035df | 64 | unsigned char reg, unsigned short *value); |
63ff004c | 65 | int bb_miiphy_write (char *devname, unsigned char addr, |
298035df | 66 | unsigned char reg, unsigned short value); |
214ec6bb WD |
67 | |
68 | /* phy seed setup */ | |
65bd0e28 | 69 | #define AUTO 99 |
298035df | 70 | #define _1000BASET 1000 |
65bd0e28 WD |
71 | #define _100BASET 100 |
72 | #define _10BASET 10 | |
73 | #define HALF 22 | |
74 | #define FULL 44 | |
214ec6bb WD |
75 | |
76 | /* phy register offsets */ | |
65bd0e28 | 77 | #define PHY_BMCR 0x00 |
214ec6bb | 78 | #define PHY_BMSR 0x01 |
65bd0e28 WD |
79 | #define PHY_PHYIDR1 0x02 |
80 | #define PHY_PHYIDR2 0x03 | |
214ec6bb | 81 | #define PHY_ANAR 0x04 |
65bd0e28 | 82 | #define PHY_ANLPAR 0x05 |
214ec6bb | 83 | #define PHY_ANER 0x06 |
65bd0e28 | 84 | #define PHY_ANNPTR 0x07 |
298035df LJ |
85 | #define PHY_ANLPNP 0x08 |
86 | #define PHY_1000BTCR 0x09 | |
87 | #define PHY_1000BTSR 0x0A | |
65bd0e28 WD |
88 | #define PHY_PHYSTS 0x10 |
89 | #define PHY_MIPSCR 0x11 | |
90 | #define PHY_MIPGSR 0x12 | |
91 | #define PHY_DCR 0x13 | |
214ec6bb WD |
92 | #define PHY_FCSCR 0x14 |
93 | #define PHY_RECR 0x15 | |
94 | #define PHY_PCSR 0x16 | |
65bd0e28 WD |
95 | #define PHY_LBR 0x17 |
96 | #define PHY_10BTSCR 0x18 | |
97 | #define PHY_PHYCTRL 0x19 | |
214ec6bb WD |
98 | |
99 | /* PHY BMCR */ | |
65bd0e28 WD |
100 | #define PHY_BMCR_RESET 0x8000 |
101 | #define PHY_BMCR_LOOP 0x4000 | |
214ec6bb WD |
102 | #define PHY_BMCR_100MB 0x2000 |
103 | #define PHY_BMCR_AUTON 0x1000 | |
104 | #define PHY_BMCR_POWD 0x0800 | |
105 | #define PHY_BMCR_ISO 0x0400 | |
106 | #define PHY_BMCR_RST_NEG 0x0200 | |
107 | #define PHY_BMCR_DPLX 0x0100 | |
108 | #define PHY_BMCR_COL_TST 0x0080 | |
109 | ||
298035df LJ |
110 | #define PHY_BMCR_SPEED_MASK 0x2040 |
111 | #define PHY_BMCR_1000_MBPS 0x0040 | |
112 | #define PHY_BMCR_100_MBPS 0x2000 | |
113 | #define PHY_BMCR_10_MBPS 0x0000 | |
b9711de1 | 114 | |
214ec6bb WD |
115 | /* phy BMSR */ |
116 | #define PHY_BMSR_100T4 0x8000 | |
117 | #define PHY_BMSR_100TXF 0x4000 | |
118 | #define PHY_BMSR_100TXH 0x2000 | |
119 | #define PHY_BMSR_10TF 0x1000 | |
120 | #define PHY_BMSR_10TH 0x0800 | |
121 | #define PHY_BMSR_PRE_SUP 0x0040 | |
122 | #define PHY_BMSR_AUTN_COMP 0x0020 | |
123 | #define PHY_BMSR_RF 0x0010 | |
124 | #define PHY_BMSR_AUTN_ABLE 0x0008 | |
125 | #define PHY_BMSR_LS 0x0004 | |
126 | #define PHY_BMSR_JD 0x0002 | |
127 | #define PHY_BMSR_EXT 0x0001 | |
128 | ||
129 | /*phy ANLPAR */ | |
130 | #define PHY_ANLPAR_NP 0x8000 | |
131 | #define PHY_ANLPAR_ACK 0x4000 | |
65bd0e28 WD |
132 | #define PHY_ANLPAR_RF 0x2000 |
133 | #define PHY_ANLPAR_T4 0x0200 | |
134 | #define PHY_ANLPAR_TXFD 0x0100 | |
135 | #define PHY_ANLPAR_TX 0x0080 | |
214ec6bb | 136 | #define PHY_ANLPAR_10FD 0x0040 |
65bd0e28 | 137 | #define PHY_ANLPAR_10 0x0020 |
298035df LJ |
138 | #define PHY_ANLPAR_100 0x0380 /* we can run at 100 */ |
139 | ||
140 | #define PHY_ANLPAR_PSB_MASK 0x001f | |
141 | #define PHY_ANLPAR_PSB_802_3 0x0001 | |
142 | #define PHY_ANLPAR_PSB_802_9 0x0002 | |
143 | ||
144 | /* phy 1000BTSR */ | |
145 | #define PHY_1000BTSR_MSCF 0x8000 | |
146 | #define PHY_1000BTSR_MSCR 0x4000 | |
147 | #define PHY_1000BTSR_LRS 0x2000 | |
148 | #define PHY_1000BTSR_RRS 0x1000 | |
149 | #define PHY_1000BTSR_1000FD 0x0800 | |
150 | #define PHY_1000BTSR_1000HD 0x0400 | |
855a496f | 151 | |
214ec6bb | 152 | #endif |