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1 | /* |
2 | * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
3 | * Andreas Heppel <aheppel@sysgo.de> | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef _MPC106_PCI_H | |
25 | #define _MPC106_PCI_H | |
26 | ||
27 | /* | |
28 | * Defines for the MPC106 PCI Config address and data registers followed by | |
29 | * defines for the standard PCI device configuration header. | |
30 | */ | |
53677ef1 | 31 | #define PCIDEVID_MPC106 0x0 |
1df49e27 WD |
32 | |
33 | /* | |
34 | * MPC106 Registers | |
35 | */ | |
36 | #define MPC106_REG 0x80000000 | |
37 | ||
6d0f6bcf | 38 | #ifdef CONFIG_SYS_ADDRESS_MAP_A |
53677ef1 | 39 | #define MPC106_REG_ADDR 0x80000cf8 |
1df49e27 WD |
40 | #define MPC106_REG_DATA 0x80000cfc |
41 | #define MPC106_ISA_IO_PHYS 0x80000000 | |
42 | #define MPC106_ISA_IO_BUS 0x00000000 | |
43 | #define MPC106_ISA_IO_SIZE 0x00800000 | |
44 | #define MPC106_PCI_IO_PHYS 0x81000000 | |
45 | #define MPC106_PCI_IO_BUS 0x01000000 | |
46 | #define MPC106_PCI_IO_SIZE 0x3e800000 | |
47 | #define MPC106_PCI_MEM_PHYS 0xc0000000 | |
48 | #define MPC106_PCI_MEM_BUS 0x00000000 | |
49 | #define MPC106_PCI_MEM_SIZE 0x3f000000 | |
50 | #define MPC106_PCI_MEMORY_PHYS 0x00000000 | |
51 | #define MPC106_PCI_MEMORY_BUS 0x80000000 | |
52 | #define MPC106_PCI_MEMORY_SIZE 0x80000000 | |
53 | #else | |
53677ef1 | 54 | #define MPC106_REG_ADDR 0xfec00cf8 |
1df49e27 WD |
55 | #define MPC106_REG_DATA 0xfee00cfc |
56 | #define MPC106_ISA_MEM_PHYS 0xfd000000 | |
57 | #define MPC106_ISA_MEM_BUS 0x00000000 | |
58 | #define MPC106_ISA_MEM_SIZE 0x01000000 | |
59 | #define MPC106_ISA_IO_PHYS 0xfe000000 | |
60 | #define MPC106_ISA_IO_BUS 0x00000000 | |
61 | #define MPC106_ISA_IO_SIZE 0x00800000 | |
62 | #define MPC106_PCI_IO_PHYS 0xfe800000 | |
63 | #define MPC106_PCI_IO_BUS 0x00800000 | |
64 | #define MPC106_PCI_IO_SIZE 0x00400000 | |
65 | #define MPC106_PCI_MEM_PHYS 0x80000000 | |
66 | #define MPC106_PCI_MEM_BUS 0x80000000 | |
67 | #define MPC106_PCI_MEM_SIZE 0x7d000000 | |
68 | #define MPC106_PCI_MEMORY_PHYS 0x00000000 | |
69 | #define MPC106_PCI_MEMORY_BUS 0x00000000 | |
70 | #define MPC106_PCI_MEMORY_SIZE 0x40000000 | |
71 | #endif | |
72 | ||
73 | #define CMD_SERR 0x0100 | |
74 | #define PCI_CMD_MASTER 0x0004 | |
75 | #define PCI_CMD_MEMEN 0x0002 | |
76 | #define PCI_CMD_IOEN 0x0001 | |
77 | ||
78 | #define PCI_STAT_NO_RSV_BITS 0xffff | |
79 | ||
53677ef1 WD |
80 | #define PCI_BUSNUM 0x40 |
81 | #define PCI_SUBBUSNUM 0x41 | |
82 | #define PCI_DISCOUNT 0x42 | |
1df49e27 WD |
83 | |
84 | #define PCI_PICR1 0xA8 | |
85 | #define PICR1_CF_CBA(value) ((value & 0xff) << 24) | |
86 | #define PICR1_CF_BREAD_WS(value) ((value & 0x3) << 22) | |
87 | #define PICR1_PROC_TYPE_603 0x40000 | |
88 | #define PICR1_PROC_TYPE_604 0x60000 | |
89 | #define PICR1_MCP_EN 0x800 | |
90 | #define PICR1_CF_DPARK 0x200 | |
91 | #define PICR1_CF_LOOP_SNOOP 0x10 | |
92 | #define PICR1_CF_L2_COPY_BACK 0x2 | |
93 | #define PICR1_CF_L2_CACHE_MASK 0x3 | |
94 | #define PICR1_CF_APARK 0x8 | |
95 | #define PICR1_ADDRESS_MAP 0x10000 | |
96 | #define PICR1_XIO_MODE 0x80000 | |
97 | #define PICR1_CF_CACHE_1G 0x200000 | |
98 | ||
99 | #define PCI_PICR2 0xAC | |
100 | #define PICR2_CF_SNOOP_WS(value) ((value & 0x3) << 18) | |
101 | #define PICR2_CF_FLUSH_L2 0x10000000 | |
102 | #define PICR2_CF_L2_HIT_DELAY(value) ((value & 0x3) << 9) | |
103 | #define PICR2_CF_APHASE_WS(value) ((value & 0x3) << 2) | |
104 | #define PICR2_CF_INV_MODE 0x00001000 | |
105 | #define PICR2_CF_MOD_HIGH 0x00020000 | |
106 | #define PICR2_CF_HIT_HIGH 0x00010000 | |
107 | #define PICR2_L2_SIZE_256K 0x00000000 | |
108 | #define PICR2_L2_SIZE_512K 0x00000010 | |
109 | #define PICR2_L2_SIZE_1MB 0x00000020 | |
110 | #define PICR2_L2_EN 0x40000000 | |
111 | #define PICR2_L2_UPDATE_EN 0x80000000 | |
112 | #define PICR2_CF_ADDR_ONLY_DISABLE 0x00004000 | |
113 | #define PICR2_CF_FAST_CASTOUT 0x00000080 | |
114 | #define PICR2_CF_WDATA 0x00000001 | |
115 | #define PICR2_CF_DATA_RAM_PBURST 0x00400000 | |
116 | ||
117 | /* | |
118 | * Memory controller | |
119 | */ | |
120 | #define MPC106_MCCR1 0xF0 | |
121 | #define MCCR1_TYPE_EDO 0x00020000 | |
122 | #define MCCR1_BK0_9BITS 0x0 | |
123 | #define MCCR1_BK0_10BITS 0x1 | |
124 | #define MCCR1_BK0_11BITS 0x2 | |
125 | #define MCCR1_BK0_12BITS 0x3 | |
126 | #define MCCR1_BK1_9BITS 0x0 | |
127 | #define MCCR1_BK1_10BITS 0x4 | |
128 | #define MCCR1_BK1_11BITS 0x8 | |
129 | #define MCCR1_BK1_12BITS 0xC | |
130 | #define MCCR1_BK2_9BITS 0x00 | |
131 | #define MCCR1_BK2_10BITS 0x10 | |
132 | #define MCCR1_BK2_11BITS 0x20 | |
133 | #define MCCR1_BK2_12BITS 0x30 | |
134 | #define MCCR1_BK3_9BITS 0x00 | |
135 | #define MCCR1_BK3_10BITS 0x40 | |
136 | #define MCCR1_BK3_11BITS 0x80 | |
137 | #define MCCR1_BK3_12BITS 0xC0 | |
138 | #define MCCR1_MEMGO 0x00080000 | |
139 | ||
140 | #define MPC106_MCCR2 0xF4 | |
141 | #define MPC106_MCCR3 0xF8 | |
142 | #define MPC106_MCCR4 0xFC | |
143 | ||
144 | #define MPC106_MSAR1 0x80 | |
145 | #define MPC106_EMSAR1 0x88 | |
146 | #define MPC106_EMSAR2 0x8C | |
147 | #define MPC106_MEAR1 0x90 | |
148 | #define MPC106_EMEAR1 0x98 | |
149 | #define MPC106_EMEAR2 0x9C | |
150 | ||
151 | #define MPC106_MBER 0xA0 | |
152 | #define MBER_BANK0 0x1 | |
153 | #define MBER_BANK1 0x2 | |
154 | #define MBER_BANK2 0x4 | |
155 | #define MBER_BANK3 0x8 | |
156 | ||
157 | #endif |