[people/ms/u-boot.git] / include / ns16550.h

/*
 * NS16550 Serial Port
 * originally from linux source (arch/ppc/boot/ns16550.h)
 *
 * Cleanup and unification
 * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
 *
 * modified slightly to
 * have addresses as offsets from CONFIG_SYS_ISA_BASE
 * added a few more definitions
 * added prototypes for ns16550.c
 * reduced no of com ports to 2
 * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
 *
 * added support for port on 64-bit bus
 * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
 */

#if (CONFIG_SYS_NS16550_REG_SIZE == 1)
struct NS16550 {
	unsigned char rbr;		/* 0 */
	unsigned char ier;		/* 1 */
	unsigned char fcr;		/* 2 */
	unsigned char lcr;		/* 3 */
	unsigned char mcr;		/* 4 */
	unsigned char lsr;		/* 5 */
	unsigned char msr;		/* 6 */
	unsigned char scr;		/* 7 */
#if defined(CONFIG_OMAP730)
	unsigned char mdr1;		/* 8 */
	unsigned char reg9;		/* 9 */
	unsigned char regA;		/* A */
	unsigned char regB;		/* B */
	unsigned char regC;		/* C */
	unsigned char regD;		/* D */
	unsigned char regE;		/* E */
	unsigned char regF;		/* F */
	unsigned char reg10;		/* 10 */
	unsigned char ssr;		/* 11*/
#endif
} __attribute__ ((packed));
#elif (CONFIG_SYS_NS16550_REG_SIZE == 2)
struct NS16550 {
	unsigned short rbr;		/* 0 */
	unsigned short ier;		/* 1 */
	unsigned short fcr;		/* 2 */
	unsigned short lcr;		/* 3 */
	unsigned short mcr;		/* 4 */
	unsigned short lsr;		/* 5 */
	unsigned short msr;		/* 6 */
	unsigned short scr;		/* 7 */
} __attribute__ ((packed));
#elif (CONFIG_SYS_NS16550_REG_SIZE == 4)
struct NS16550 {
	unsigned long rbr;		/* 0 r  */
	unsigned long ier;		/* 1 rw */
	unsigned long fcr;		/* 2 w  */
	unsigned long lcr;		/* 3 rw */
	unsigned long mcr;		/* 4 rw */
	unsigned long lsr;		/* 5 r  */
	unsigned long msr;		/* 6 r  */
	unsigned long scr;		/* 7 rw */
}; /* No need to pack an already aligned struct */
#elif (CONFIG_SYS_NS16550_REG_SIZE == -4)
struct NS16550 {
	unsigned char rbr;		/* 0 */
	int pad1:24;
	unsigned char ier;		/* 1 */
	int pad2:24;
	unsigned char fcr;		/* 2 */
	int pad3:24;
	unsigned char lcr;		/* 3 */
	int pad4:24;
	unsigned char mcr;		/* 4 */
	int pad5:24;
	unsigned char lsr;		/* 5 */
	int pad6:24;
	unsigned char msr;		/* 6 */
	int pad7:24;
	unsigned char scr;		/* 7 */
	int pad8:24;
#if defined(CONFIG_OMAP)
	unsigned char mdr1;		/* mode select reset TL16C750*/
#endif
#ifdef CONFIG_OMAP1510
	int pad9:24;
	unsigned long pad[10];
	unsigned char osc_12m_sel;
	int pad10:24;
#endif
} __attribute__ ((packed));
#elif (CONFIG_SYS_NS16550_REG_SIZE == -8)
struct NS16550 {
	unsigned char rbr;		/* 0 */
	unsigned char pad0[7];
	unsigned char ier;		/* 1 */
	unsigned char pad1[7];
	unsigned char fcr;		/* 2 */
	unsigned char pad2[7];
	unsigned char lcr;		/* 3 */
	unsigned char pad3[7];
	unsigned char mcr;		/* 4 */
	unsigned char pad4[7];
	unsigned char lsr;		/* 5 */
	unsigned char pad5[7];
	unsigned char msr;		/* 6 */
	unsigned char pad6[7];
	unsigned char scr;		/* 7 */
	unsigned char pad7[7];
} __attribute__ ((packed));
#else
#error "Please define NS16550 registers size."
#endif

#define thr rbr
#define iir fcr
#define dll rbr
#define dlm ier

typedef volatile struct NS16550 *NS16550_t;

/*
 * These are the definitions for the FIFO Control Register
 */
#define UART_FCR_FIFO_EN 	0x01 /* Fifo enable */
#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */

#define UART_FCR_RXSR		0x02 /* Receiver soft reset */
#define UART_FCR_TXSR		0x04 /* Transmitter soft reset */

/*
 * These are the definitions for the Modem Control Register
 */
#define UART_MCR_DTR	0x01		/* DTR   */
#define UART_MCR_RTS	0x02		/* RTS   */
#define UART_MCR_OUT1	0x04		/* Out 1 */
#define UART_MCR_OUT2	0x08		/* Out 2 */
#define UART_MCR_LOOP	0x10		/* Enable loopback test mode */

#define UART_MCR_DMA_EN	0x04
#define UART_MCR_TX_DFR	0x08

/*
 * These are the definitions for the Line Control Register
 *
 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
 */
#define UART_LCR_WLS_MSK 0x03		/* character length select mask */
#define UART_LCR_WLS_5	0x00		/* 5 bit character length */
#define UART_LCR_WLS_6	0x01		/* 6 bit character length */
#define UART_LCR_WLS_7	0x02		/* 7 bit character length */
#define UART_LCR_WLS_8	0x03		/* 8 bit character length */
#define UART_LCR_STB	0x04		/* Number of stop Bits, off = 1, on = 1.5 or 2) */
#define UART_LCR_PEN	0x08		/* Parity eneble */
#define UART_LCR_EPS	0x10		/* Even Parity Select */
#define UART_LCR_STKP	0x20		/* Stick Parity */
#define UART_LCR_SBRK	0x40		/* Set Break */
#define UART_LCR_BKSE	0x80		/* Bank select enable */
#define UART_LCR_DLAB	0x80		/* Divisor latch access bit */

/*
 * These are the definitions for the Line Status Register
 */
#define UART_LSR_DR	0x01		/* Data ready */
#define UART_LSR_OE	0x02		/* Overrun */
#define UART_LSR_PE	0x04		/* Parity error */
#define UART_LSR_FE	0x08		/* Framing error */
#define UART_LSR_BI	0x10		/* Break */
#define UART_LSR_THRE	0x20		/* Xmit holding register empty */
#define UART_LSR_TEMT	0x40		/* Xmitter empty */
#define UART_LSR_ERR	0x80		/* Error */

#define UART_MSR_DCD	0x80		/* Data Carrier Detect */
#define UART_MSR_RI	0x40		/* Ring Indicator */
#define UART_MSR_DSR	0x20		/* Data Set Ready */
#define UART_MSR_CTS	0x10		/* Clear to Send */
#define UART_MSR_DDCD	0x08		/* Delta DCD */
#define UART_MSR_TERI	0x04		/* Trailing edge ring indicator */
#define UART_MSR_DDSR	0x02		/* Delta DSR */
#define UART_MSR_DCTS	0x01		/* Delta CTS */

/*
 * These are the definitions for the Interrupt Identification Register
 */
#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */

#define UART_IIR_MSI	0x00	/* Modem status interrupt */
#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */

/*
 * These are the definitions for the Interrupt Enable Register
 */
#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */


#ifdef CONFIG_OMAP1510
#define OSC_12M_SEL	0x01	/* selects 6.5 * current clk div */
#endif

/* useful defaults for LCR */
#define UART_LCR_8N1	0x03

void	NS16550_init   (NS16550_t com_port, int baud_divisor);
void	NS16550_putc   (NS16550_t com_port, char c);
char	NS16550_getc   (NS16550_t com_port);
int	NS16550_tstc   (NS16550_t com_port);
void	NS16550_reinit (NS16550_t com_port, int baud_divisor);
Commit	Line	Data
717b5aad WD	1	/*
	2	* NS16550 Serial Port
	3	* originally from linux source (arch/ppc/boot/ns16550.h)
200779e3 DZ	4	*
	5	* Cleanup and unification
	6	* (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
	7	*
717b5aad	8	* modified slightly to
6d0f6bcf	9	* have addresses as offsets from CONFIG_SYS_ISA_BASE
717b5aad WD	10	* added a few more definitions
	11	* added prototypes for ns16550.c
	12	* reduced no of com ports to 2
	13	* modifications (c) Rob Taylor, Flying Pig Systems. 2000.
b87dfd28	14	*
f5e0d039 HS	15	* added support for port on 64-bit bus
f5e0d039 HS	16	* by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
717b5aad WD	17	*/
717b5aad WD	18
6d0f6bcf	19	#if (CONFIG_SYS_NS16550_REG_SIZE == 1)
717b5aad WD	20	struct NS16550 {
	21	unsigned char rbr; /* 0 */
	22	unsigned char ier; /* 1 */
	23	unsigned char fcr; /* 2 */
	24	unsigned char lcr; /* 3 */
	25	unsigned char mcr; /* 4 */
	26	unsigned char lsr; /* 5 */
	27	unsigned char msr; /* 6 */
	28	unsigned char scr; /* 7 */
a56bd922 WD	29	#if defined(CONFIG_OMAP730)
	30	unsigned char mdr1; /* 8 */
	31	unsigned char reg9; /* 9 */
	32	unsigned char regA; /* A */
	33	unsigned char regB; /* B */
	34	unsigned char regC; /* C */
	35	unsigned char regD; /* D */
	36	unsigned char regE; /* E */
	37	unsigned char regF; /* F */
	38	unsigned char reg10; /* 10 */
	39	unsigned char ssr; /* 11*/
	40	#endif
717b5aad	41	} __attribute__ ((packed));
6d0f6bcf	42	#elif (CONFIG_SYS_NS16550_REG_SIZE == 2)
717b5aad WD	43	struct NS16550 {
	44	unsigned short rbr; /* 0 */
	45	unsigned short ier; /* 1 */
	46	unsigned short fcr; /* 2 */
	47	unsigned short lcr; /* 3 */
	48	unsigned short mcr; /* 4 */
	49	unsigned short lsr; /* 5 */
	50	unsigned short msr; /* 6 */
	51	unsigned short scr; /* 7 */
	52	} __attribute__ ((packed));
6d0f6bcf	53	#elif (CONFIG_SYS_NS16550_REG_SIZE == 4)
717b5aad	54	struct NS16550 {
22814904 WD	55	unsigned long rbr; /* 0 r */
	56	unsigned long ier; /* 1 rw */
	57	unsigned long fcr; /* 2 w */
	58	unsigned long lcr; /* 3 rw */
	59	unsigned long mcr; /* 4 rw */
	60	unsigned long lsr; /* 5 r */
	61	unsigned long msr; /* 6 r */
	62	unsigned long scr; /* 7 rw */
	63	}; /* No need to pack an already aligned struct */
6d0f6bcf	64	#elif (CONFIG_SYS_NS16550_REG_SIZE == -4)
717b5aad WD	65	struct NS16550 {
	66	unsigned char rbr; /* 0 */
	67	int pad1:24;
	68	unsigned char ier; /* 1 */
	69	int pad2:24;
	70	unsigned char fcr; /* 2 */
	71	int pad3:24;
	72	unsigned char lcr; /* 3 */
	73	int pad4:24;
	74	unsigned char mcr; /* 4 */
	75	int pad5:24;
	76	unsigned char lsr; /* 5 */
	77	int pad6:24;
	78	unsigned char msr; /* 6 */
	79	int pad7:24;
	80	unsigned char scr; /* 7 */
	81	int pad8:24;
8ed96046	82	#if defined(CONFIG_OMAP)
2e5983d2	83	unsigned char mdr1; /* mode select reset TL16C750*/
6f21347d WD	84	#endif
6f21347d WD	85	#ifdef CONFIG_OMAP1510
2e5983d2 WD	86	int pad9:24;
	87	unsigned long pad[10];
	88	unsigned char osc_12m_sel;
	89	int pad10:24;
	90	#endif
717b5aad	91	} __attribute__ ((packed));
6d0f6bcf	92	#elif (CONFIG_SYS_NS16550_REG_SIZE == -8)
f5e0d039 HS	93	struct NS16550 {
	94	unsigned char rbr; /* 0 */
	95	unsigned char pad0[7];
	96	unsigned char ier; /* 1 */
	97	unsigned char pad1[7];
	98	unsigned char fcr; /* 2 */
	99	unsigned char pad2[7];
	100	unsigned char lcr; /* 3 */
	101	unsigned char pad3[7];
	102	unsigned char mcr; /* 4 */
	103	unsigned char pad4[7];
	104	unsigned char lsr; /* 5 */
	105	unsigned char pad5[7];
	106	unsigned char msr; /* 6 */
	107	unsigned char pad6[7];
	108	unsigned char scr; /* 7 */
	109	unsigned char pad7[7];
	110	} __attribute__ ((packed));
717b5aad WD	111	#else
	112	#error "Please define NS16550 registers size."
	113	#endif
	114
	115	#define thr rbr
	116	#define iir fcr
	117	#define dll rbr
	118	#define dlm ier
	119
	120	typedef volatile struct NS16550 *NS16550_t;
	121
200779e3 DZ	122	/*
	123	* These are the definitions for the FIFO Control Register
	124	*/
	125	#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
	126	#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
	127	#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
	128	#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
	129	#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
	130	#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
	131	#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
	132	#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
	133	#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
	134
	135	#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
	136	#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
	137
	138	/*
	139	* These are the definitions for the Modem Control Register
	140	*/
	141	#define UART_MCR_DTR 0x01 /* DTR */
	142	#define UART_MCR_RTS 0x02 /* RTS */
	143	#define UART_MCR_OUT1 0x04 /* Out 1 */
	144	#define UART_MCR_OUT2 0x08 /* Out 2 */
	145	#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
	146
	147	#define UART_MCR_DMA_EN 0x04
	148	#define UART_MCR_TX_DFR 0x08
	149
	150	/*
	151	* These are the definitions for the Line Control Register
	152	*
	153	* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
	154	* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
	155	*/
	156	#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
	157	#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
	158	#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
	159	#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
	160	#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
	161	#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
	162	#define UART_LCR_PEN 0x08 /* Parity eneble */
	163	#define UART_LCR_EPS 0x10 /* Even Parity Select */
	164	#define UART_LCR_STKP 0x20 /* Stick Parity */
	165	#define UART_LCR_SBRK 0x40 /* Set Break */
	166	#define UART_LCR_BKSE 0x80 /* Bank select enable */
	167	#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
	168
	169	/*
	170	* These are the definitions for the Line Status Register
	171	*/
	172	#define UART_LSR_DR 0x01 /* Data ready */
	173	#define UART_LSR_OE 0x02 /* Overrun */
	174	#define UART_LSR_PE 0x04 /* Parity error */
	175	#define UART_LSR_FE 0x08 /* Framing error */
	176	#define UART_LSR_BI 0x10 /* Break */
	177	#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
	178	#define UART_LSR_TEMT 0x40 /* Xmitter empty */
	179	#define UART_LSR_ERR 0x80 /* Error */
	180
	181	#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
	182	#define UART_MSR_RI 0x40 /* Ring Indicator */
	183	#define UART_MSR_DSR 0x20 /* Data Set Ready */
	184	#define UART_MSR_CTS 0x10 /* Clear to Send */
	185	#define UART_MSR_DDCD 0x08 /* Delta DCD */
186	#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
187	#define UART_MSR_DDSR 0x02 /* Delta DSR */
188	#define UART_MSR_DCTS 0x01 /* Delta CTS */
189
190	/*
191	* These are the definitions for the Interrupt Identification Register
192	*/
193	#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
194	#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
195
196	#define UART_IIR_MSI 0x00 /* Modem status interrupt */
197	#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
198	#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
199	#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
200
201	/*
202	* These are the definitions for the Interrupt Enable Register
203	*/
204	#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
205	#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
206	#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
207	#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
208
7b5611cd	209
2e5983d2	210	#ifdef CONFIG_OMAP1510
200779e3	211	#define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */
2e5983d2 WD	212	#endif
2e5983d2 WD	213
717b5aad	214	/* useful defaults for LCR */
200779e3	215	#define UART_LCR_8N1 0x03
717b5aad WD	216
	217	void NS16550_init (NS16550_t com_port, int baud_divisor);
	218	void NS16550_putc (NS16550_t com_port, char c);
	219	char NS16550_getc (NS16550_t com_port);
	220	int NS16550_tstc (NS16550_t com_port);
	221	void NS16550_reinit (NS16550_t com_port, int baud_divisor);