[people/ms/u-boot.git] / include / ns16550.h

/*
 * NS16550 Serial Port
 * originally from linux source (arch/powerpc/boot/ns16550.h)
 *
 * Cleanup and unification
 * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
 *
 * modified slightly to
 * have addresses as offsets from CONFIG_SYS_ISA_BASE
 * added a few more definitions
 * added prototypes for ns16550.c
 * reduced no of com ports to 2
 * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
 *
 * added support for port on 64-bit bus
 * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
 */

/*
 * Note that the following macro magic uses the fact that the compiler
 * will not allocate storage for arrays of size 0
 */

#include <linux/types.h>

#ifdef CONFIG_DM_SERIAL
/*
 * For driver model we always use one byte per register, and sort out the
 * differences in the driver
 */
#define CONFIG_SYS_NS16550_REG_SIZE (-1)
#endif

#if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0)
#error "Please define NS16550 registers size."
#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL)
#define UART_REG(x) u32 x
#elif (CONFIG_SYS_NS16550_REG_SIZE > 0)
#define UART_REG(x)						   \
	unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
	unsigned char x;
#elif (CONFIG_SYS_NS16550_REG_SIZE < 0)
#define UART_REG(x)							\
	unsigned char x;						\
	unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
#endif

/**
 * struct ns16550_platdata - information about a NS16550 port
 *
 * @base:		Base register address
 * @reg_shift:		Shift size of registers (0=byte, 1=16bit, 2=32bit...)
 * @clock:		UART base clock speed in Hz
 *
 * @buf:		Pointer to the RX interrupt buffer
 * @rd_ptr:		Read pointer in the RX interrupt buffer
 * @wr_ptr:		Write pointer in the RX interrupt buffer
 */
struct ns16550_platdata {
	unsigned long base;
	int reg_shift;
	int clock;
	int reg_offset;
	u32 fcr;

	int irq;

	char *buf;
	int rd_ptr;
	int wr_ptr;
};

struct udevice;

struct NS16550 {
	UART_REG(rbr);		/* 0 */
	UART_REG(ier);		/* 1 */
	UART_REG(fcr);		/* 2 */
	UART_REG(lcr);		/* 3 */
	UART_REG(mcr);		/* 4 */
	UART_REG(lsr);		/* 5 */
	UART_REG(msr);		/* 6 */
	UART_REG(spr);		/* 7 */
#ifdef CONFIG_SOC_DA8XX
	UART_REG(reg8);		/* 8 */
	UART_REG(reg9);		/* 9 */
	UART_REG(revid1);	/* A */
	UART_REG(revid2);	/* B */
	UART_REG(pwr_mgmt);	/* C */
	UART_REG(mdr1);		/* D */
#else
	UART_REG(mdr1);		/* 8 */
	UART_REG(reg9);		/* 9 */
	UART_REG(regA);		/* A */
	UART_REG(regB);		/* B */
	UART_REG(regC);		/* C */
	UART_REG(regD);		/* D */
	UART_REG(regE);		/* E */
	UART_REG(uasr);		/* F */
	UART_REG(scr);		/* 10*/
	UART_REG(ssr);		/* 11*/
#endif
#ifdef CONFIG_DM_SERIAL
	struct ns16550_platdata *plat;
#endif
};

#define thr rbr
#define iir fcr
#define dll rbr
#define dlm ier

typedef struct NS16550 *NS16550_t;

/*
 * These are the definitions for the FIFO Control Register
 */
#define UART_FCR_FIFO_EN	0x01 /* Fifo enable */
#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */

#define UART_FCR_RXSR		0x02 /* Receiver soft reset */
#define UART_FCR_TXSR		0x04 /* Transmitter soft reset */

/* Ingenic JZ47xx specific UART-enable bit. */
#define UART_FCR_UME		0x10

/* Clear & enable FIFOs */
#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \
			UART_FCR_RXSR |	\
			UART_FCR_TXSR)

/*
 * These are the definitions for the Modem Control Register
 */
#define UART_MCR_DTR	0x01		/* DTR   */
#define UART_MCR_RTS	0x02		/* RTS   */
#define UART_MCR_OUT1	0x04		/* Out 1 */
#define UART_MCR_OUT2	0x08		/* Out 2 */
#define UART_MCR_LOOP	0x10		/* Enable loopback test mode */
#define UART_MCR_AFE	0x20		/* Enable auto-RTS/CTS */

#define UART_MCR_DMA_EN	0x04
#define UART_MCR_TX_DFR	0x08

/*
 * These are the definitions for the Line Control Register
 *
 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
 */
#define UART_LCR_WLS_MSK 0x03		/* character length select mask */
#define UART_LCR_WLS_5	0x00		/* 5 bit character length */
#define UART_LCR_WLS_6	0x01		/* 6 bit character length */
#define UART_LCR_WLS_7	0x02		/* 7 bit character length */
#define UART_LCR_WLS_8	0x03		/* 8 bit character length */
#define UART_LCR_STB	0x04		/* # stop Bits, off=1, on=1.5 or 2) */
#define UART_LCR_PEN	0x08		/* Parity eneble */
#define UART_LCR_EPS	0x10		/* Even Parity Select */
#define UART_LCR_STKP	0x20		/* Stick Parity */
#define UART_LCR_SBRK	0x40		/* Set Break */
#define UART_LCR_BKSE	0x80		/* Bank select enable */
#define UART_LCR_DLAB	0x80		/* Divisor latch access bit */

/*
 * These are the definitions for the Line Status Register
 */
#define UART_LSR_DR	0x01		/* Data ready */
#define UART_LSR_OE	0x02		/* Overrun */
#define UART_LSR_PE	0x04		/* Parity error */
#define UART_LSR_FE	0x08		/* Framing error */
#define UART_LSR_BI	0x10		/* Break */
#define UART_LSR_THRE	0x20		/* Xmit holding register empty */
#define UART_LSR_TEMT	0x40		/* Xmitter empty */
#define UART_LSR_ERR	0x80		/* Error */

#define UART_MSR_DCD	0x80		/* Data Carrier Detect */
#define UART_MSR_RI	0x40		/* Ring Indicator */
#define UART_MSR_DSR	0x20		/* Data Set Ready */
#define UART_MSR_CTS	0x10		/* Clear to Send */
#define UART_MSR_DDCD	0x08		/* Delta DCD */
#define UART_MSR_TERI	0x04		/* Trailing edge ring indicator */
#define UART_MSR_DDSR	0x02		/* Delta DSR */
#define UART_MSR_DCTS	0x01		/* Delta CTS */

/*
 * These are the definitions for the Interrupt Identification Register
 */
#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */

#define UART_IIR_MSI	0x00	/* Modem status interrupt */
#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */

/*
 * These are the definitions for the Interrupt Enable Register
 */
#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */

/* useful defaults for LCR */
#define UART_LCR_8N1	0x03

void NS16550_init(NS16550_t com_port, int baud_divisor);
void NS16550_putc(NS16550_t com_port, char c);
char NS16550_getc(NS16550_t com_port);
int NS16550_tstc(NS16550_t com_port);
void NS16550_reinit(NS16550_t com_port, int baud_divisor);

/**
 * ns16550_calc_divisor() - calculate the divisor given clock and baud rate
 *
 * Given the UART input clock and required baudrate, calculate the divisor
 * that should be used.
 *
 * @port:	UART port
 * @clock:	UART input clock speed in Hz
 * @baudrate:	Required baud rate
 * @return baud rate divisor that should be used
 */
int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate);

/**
 * ns16550_serial_ofdata_to_platdata() - convert DT to platform data
 *
 * Decode a device tree node for an ns16550 device. This includes the
 * register base address and register shift properties. The caller must set
 * up the clock frequency.
 *
 * @dev:	dev to decode platform data for
 * @return:	0 if OK, -EINVAL on error
 */
int ns16550_serial_ofdata_to_platdata(struct udevice *dev);

/**
 * ns16550_serial_probe() - probe a serial port
 *
 * This sets up the serial port ready for use, except for the baud rate
 * @return 0, or -ve on error
 */
int ns16550_serial_probe(struct udevice *dev);

/**
 * struct ns16550_serial_ops - ns16550 serial operations
 *
 * These should be used by the client driver for the driver's 'ops' member
 */
extern const struct dm_serial_ops ns16550_serial_ops;
Commit	Line	Data
717b5aad WD	1	/*
717b5aad WD	2	* NS16550 Serial Port
a47a12be	3	* originally from linux source (arch/powerpc/boot/ns16550.h)
200779e3 DZ	4	*
	5	* Cleanup and unification
	6	* (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
	7	*
717b5aad	8	* modified slightly to
6d0f6bcf	9	* have addresses as offsets from CONFIG_SYS_ISA_BASE
717b5aad WD	10	* added a few more definitions
	11	* added prototypes for ns16550.c
	12	* reduced no of com ports to 2
	13	* modifications (c) Rob Taylor, Flying Pig Systems. 2000.
b87dfd28	14	*
f5e0d039 HS	15	* added support for port on 64-bit bus
f5e0d039 HS	16	* by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
717b5aad WD	17	*/
717b5aad WD	18
453c0d75 DZ	19	/*
	20	* Note that the following macro magic uses the fact that the compiler
	21	* will not allocate storage for arrays of size 0
	22	*/
	23
79df1208 DA	24	#include <linux/types.h>
79df1208 DA	25
12e431b2 SG	26	#ifdef CONFIG_DM_SERIAL
	27	/*
	28	* For driver model we always use one byte per register, and sort out the
	29	* differences in the driver
	30	*/
	31	#define CONFIG_SYS_NS16550_REG_SIZE (-1)
	32	#endif
	33
453c0d75	34	#if !defined(CONFIG_SYS_NS16550_REG_SIZE) \|\| (CONFIG_SYS_NS16550_REG_SIZE == 0)
717b5aad	35	#error "Please define NS16550 registers size."
90914008	36	#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL)
79df1208	37	#define UART_REG(x) u32 x
453c0d75 DZ	38	#elif (CONFIG_SYS_NS16550_REG_SIZE > 0)
	39	#define UART_REG(x) \
	40	unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
	41	unsigned char x;
	42	#elif (CONFIG_SYS_NS16550_REG_SIZE < 0)
	43	#define UART_REG(x) \
	44	unsigned char x; \
	45	unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
717b5aad WD	46	#endif
717b5aad WD	47
12e431b2 SG	48	/**
	49	* struct ns16550_platdata - information about a NS16550 port
	50	*
	51	* @base: Base register address
	52	* @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...)
	53	* @clock: UART base clock speed in Hz
6822cf3e SR	54	*
	55	* @buf: Pointer to the RX interrupt buffer
	56	* @rd_ptr: Read pointer in the RX interrupt buffer
	57	* @wr_ptr: Write pointer in the RX interrupt buffer
12e431b2 SG	58	*/
12e431b2 SG	59	struct ns16550_platdata {
167efe01	60	unsigned long base;
12e431b2 SG	61	int reg_shift;
12e431b2 SG	62	int clock;
59b35ddd	63	int reg_offset;
65f83802	64	u32 fcr;
6822cf3e SR	65
	66	int irq;
	67
	68	char *buf;
	69	int rd_ptr;
	70	int wr_ptr;
12e431b2 SG	71	};
	72
	73	struct udevice;
	74
453c0d75 DZ	75	struct NS16550 {
	76	UART_REG(rbr); /* 0 */
	77	UART_REG(ier); /* 1 */
	78	UART_REG(fcr); /* 2 */
	79	UART_REG(lcr); /* 3 */
	80	UART_REG(mcr); /* 4 */
	81	UART_REG(lsr); /* 5 */
	82	UART_REG(msr); /* 6 */
	83	UART_REG(spr); /* 7 */
99b603e7 MK	84	#ifdef CONFIG_SOC_DA8XX
	85	UART_REG(reg8); /* 8 */
	86	UART_REG(reg9); /* 9 */
	87	UART_REG(revid1); /* A */
	88	UART_REG(revid2); /* B */
	89	UART_REG(pwr_mgmt); /* C */
	90	UART_REG(mdr1); /* D */
	91	#else
453c0d75 DZ	92	UART_REG(mdr1); /* 8 */
	93	UART_REG(reg9); /* 9 */
	94	UART_REG(regA); /* A */
	95	UART_REG(regB); /* B */
	96	UART_REG(regC); /* C */
	97	UART_REG(regD); /* D */
	98	UART_REG(regE); /* E */
	99	UART_REG(uasr); /* F */
	100	UART_REG(scr); /* 10*/
	101	UART_REG(ssr); /* 11*/
99b603e7	102	#endif
12e431b2 SG	103	#ifdef CONFIG_DM_SERIAL
	104	struct ns16550_platdata *plat;
	105	#endif
453c0d75 DZ	106	};
453c0d75 DZ	107
717b5aad WD	108	#define thr rbr
	109	#define iir fcr
	110	#define dll rbr
	111	#define dlm ier
	112
f8df9d0d	113	typedef struct NS16550 *NS16550_t;
717b5aad	114
200779e3 DZ	115	/*
	116	* These are the definitions for the FIFO Control Register
	117	*/
f8df9d0d	118	#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
200779e3 DZ	119	#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
	120	#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
	121	#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
	122	#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
	123	#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
	124	#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
	125	#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
	126	#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
	127
	128	#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
	129	#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
	130
0b060eef MV	131	/* Ingenic JZ47xx specific UART-enable bit. */
	132	#define UART_FCR_UME 0x10
	133
17fa0326 HS	134	/* Clear & enable FIFOs */
	135	#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN \| \
	136	UART_FCR_RXSR \| \
	137	UART_FCR_TXSR)
	138
200779e3 DZ	139	/*
	140	* These are the definitions for the Modem Control Register
	141	*/
	142	#define UART_MCR_DTR 0x01 /* DTR */
	143	#define UART_MCR_RTS 0x02 /* RTS */
	144	#define UART_MCR_OUT1 0x04 /* Out 1 */
	145	#define UART_MCR_OUT2 0x08 /* Out 2 */
	146	#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
d57dee57	147	#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
200779e3 DZ	148
	149	#define UART_MCR_DMA_EN 0x04
	150	#define UART_MCR_TX_DFR 0x08
	151
	152	/*
	153	* These are the definitions for the Line Control Register
	154	*
	155	* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
	156	* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
	157	*/
	158	#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
	159	#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
	160	#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
	161	#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
	162	#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
f8df9d0d	163	#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
200779e3 DZ	164	#define UART_LCR_PEN 0x08 /* Parity eneble */
	165	#define UART_LCR_EPS 0x10 /* Even Parity Select */
	166	#define UART_LCR_STKP 0x20 /* Stick Parity */
	167	#define UART_LCR_SBRK 0x40 /* Set Break */
	168	#define UART_LCR_BKSE 0x80 /* Bank select enable */
	169	#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
	170
	171	/*
	172	* These are the definitions for the Line Status Register
	173	*/
	174	#define UART_LSR_DR 0x01 /* Data ready */
	175	#define UART_LSR_OE 0x02 /* Overrun */
	176	#define UART_LSR_PE 0x04 /* Parity error */
	177	#define UART_LSR_FE 0x08 /* Framing error */
	178	#define UART_LSR_BI 0x10 /* Break */
	179	#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
	180	#define UART_LSR_TEMT 0x40 /* Xmitter empty */
	181	#define UART_LSR_ERR 0x80 /* Error */
	182
	183	#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
	184	#define UART_MSR_RI 0x40 /* Ring Indicator */
	185	#define UART_MSR_DSR 0x20 /* Data Set Ready */
	186	#define UART_MSR_CTS 0x10 /* Clear to Send */
	187	#define UART_MSR_DDCD 0x08 /* Delta DCD */
	188	#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
	189	#define UART_MSR_DDSR 0x02 /* Delta DSR */
	190	#define UART_MSR_DCTS 0x01 /* Delta CTS */
	191
	192	/*
	193	* These are the definitions for the Interrupt Identification Register
	194	*/
	195	#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
	196	#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
	197
	198	#define UART_IIR_MSI 0x00 /* Modem status interrupt */
	199	#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
	200	#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
	201	#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
	202
	203	/*
	204	* These are the definitions for the Interrupt Enable Register
	205	*/
	206	#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
	207	#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
	208	#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
	209	#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
	210
717b5aad	211	/* useful defaults for LCR */
200779e3	212	#define UART_LCR_8N1 0x03
717b5aad	213
f8df9d0d SG	214	void NS16550_init(NS16550_t com_port, int baud_divisor);
	215	void NS16550_putc(NS16550_t com_port, char c);
	216	char NS16550_getc(NS16550_t com_port);
	217	int NS16550_tstc(NS16550_t com_port);
	218	void NS16550_reinit(NS16550_t com_port, int baud_divisor);
fa54eb12 SG	219
	220	/**
	221	* ns16550_calc_divisor() - calculate the divisor given clock and baud rate
	222	*
	223	* Given the UART input clock and required baudrate, calculate the divisor
	224	* that should be used.
	225	*
	226	* @port: UART port
	227	* @clock: UART input clock speed in Hz
	228	* @baudrate: Required baud rate
	229	* @return baud rate divisor that should be used
	230	*/
	231	int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate);
12e431b2 SG	232
	233	/**
	234	* ns16550_serial_ofdata_to_platdata() - convert DT to platform data
	235	*
	236	* Decode a device tree node for an ns16550 device. This includes the
	237	* register base address and register shift properties. The caller must set
	238	* up the clock frequency.
	239	*
	240	* @dev: dev to decode platform data for
	241	* @return: 0 if OK, -EINVAL on error
	242	*/
	243	int ns16550_serial_ofdata_to_platdata(struct udevice *dev);
	244
	245	/**
	246	* ns16550_serial_probe() - probe a serial port
	247	*
	248	* This sets up the serial port ready for use, except for the baud rate
	249	* @return 0, or -ve on error
	250	*/
	251	int ns16550_serial_probe(struct udevice *dev);
	252
	253	/**
	254	* struct ns16550_serial_ops - ns16550 serial operations
	255	*
	256	* These should be used by the client driver for the driver's 'ops' member
	257	*/
	258	extern const struct dm_serial_ops ns16550_serial_ops;