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* tc-score.c (data_op2): Check invalid operands.
[thirdparty/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
b138abaa
NC		 12006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
2
3 * score-inst.h (enum score_insn_type): Add Insn_internal.
4
52006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
6
7 * score-inst.h (enum score_insn_type): Add Insn_internal.
8
92006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
10 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
11 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
12 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
13 Alan Modra <amodra@bigpond.net.au>
14
15 * spu-insns.h: New file.
16 * spu.h: New file.
17
182006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
19
20 * ppc.h (PPC_OPCODE_CELL): Define.
21
222006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
23
24 * i386.h : Modify opcode to support for the change in POPCNT opcode
25 in amdfam10 architecture.
26
272006-09-28 H.J. Lu <hongjiu.lu@intel.com>
28
29 * i386.h: Replace CpuMNI with CpuSSSE3.
30
312006-09-26 Mark Shinwell <shinwell@codesourcery.com>
32 Joseph Myers <joseph@codesourcery.com>
33 Ian Lance Taylor <ian@wasabisystems.com>
34 Ben Elliston <bje@wasabisystems.com>
35
36 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
37
382006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
39
40 * score-datadep.h: New file.
41 * score-inst.h: New file.
42
432006-07-14 H.J. Lu <hongjiu.lu@intel.com>
44
45 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
46 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
47 movdq2q and movq2dq.
48
492006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
50 Michael Meissner <michael.meissner@amd.com>
51
52 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
53
542006-06-12 H.J. Lu <hongjiu.lu@intel.com>
55
56 * i386.h (i386_optab): Add "nop" with memory reference.
57
582006-06-12 H.J. Lu <hongjiu.lu@intel.com>
59
60 * i386.h (i386_optab): Update comment for 64bit NOP.
61
622006-06-06 Ben Elliston <bje@au.ibm.com>
63 Anton Blanchard <anton@samba.org>
64
65 * ppc.h (PPC_OPCODE_POWER6): Define.
66 Adjust whitespace.
67
682006-06-05 Thiemo Seufer <ths@mips.com>
69
70 * mips.h: Improve description of MT flags.
71
722006-05-25 Richard Sandiford <richard@codesourcery.com>
73
74 * m68k.h (mcf_mask): Define.
75
762006-05-05 Thiemo Seufer <ths@mips.com>
77 David Ung <davidu@mips.com>
78
79 * mips.h (enum): Add macro M_CACHE_AB.
80
812006-05-04 Thiemo Seufer <ths@mips.com>
82 Nigel Stephens <nigel@mips.com>
83 David Ung <davidu@mips.com>
84
85 * mips.h: Add INSN_SMARTMIPS define.
86
872006-04-30 Thiemo Seufer <ths@mips.com>
88 David Ung <davidu@mips.com>
89
90 * mips.h: Defines udi bits and masks. Add description of
91 characters which may appear in the args field of udi
92 instructions.
93
942006-04-26 Thiemo Seufer <ths@networkno.de>
95
96 * mips.h: Improve comments describing the bitfield instruction
97 fields.
98
992006-04-26 Julian Brown <julian@codesourcery.com>
100
101 * arm.h (FPU_VFP_EXT_V3): Define constant.
102 (FPU_NEON_EXT_V1): Likewise.
103 (FPU_VFP_HARD): Update.
104 (FPU_VFP_V3): Define macro.
105 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
106
1072006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
108
109 * avr.h (AVR_ISA_PWMx): New.
110
1112006-03-28 Nathan Sidwell <nathan@codesourcery.com>
112
113 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
114 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
115 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
116 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
117 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
118
1192006-03-10 Paul Brook <paul@codesourcery.com>
120
121 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
122
1232006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
124
125 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
126 first. Correct mask of bb "B" opcode.
127
1282006-02-27 H.J. Lu <hongjiu.lu@intel.com>
129
130 * i386.h (i386_optab): Support Intel Merom New Instructions.
131
1322006-02-24 Paul Brook <paul@codesourcery.com>
133
134 * arm.h: Add V7 feature bits.
135
1362006-02-23 H.J. Lu <hongjiu.lu@intel.com>
137
138 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
139
1402006-01-31 Paul Brook <paul@codesourcery.com>
141 Richard Earnshaw <rearnsha@arm.com>
142
143 * arm.h: Use ARM_CPU_FEATURE.
144 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
145 (arm_feature_set): Change to a structure.
146 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
147 ARM_FEATURE): New macros.
148
1492005-12-07 Hans-Peter Nilsson <hp@axis.com>
150
151 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
152 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
153 (ADD_PC_INCR_OPCODE): Don't define.
154
1552005-12-06 H.J. Lu <hongjiu.lu@intel.com>
156
157 PR gas/1874
158 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
159
1602005-11-14 David Ung <davidu@mips.com>
161
162 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
163 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
164 save/restore encoding of the args field.
165
1662005-10-28 Dave Brolley <brolley@redhat.com>
167
168 Contribute the following changes:
169 2005-02-16 Dave Brolley <brolley@redhat.com>
170
171 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
172 cgen_isa_mask_* to cgen_bitset_*.
173 * cgen.h: Likewise.
174
175 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
176
177 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
178 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
179 (CGEN_CPU_TABLE): Make isas a ponter.
180
181 2003-09-29 Dave Brolley <brolley@redhat.com>
182
183 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
184 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
185 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
186
187 2002-12-13 Dave Brolley <brolley@redhat.com>
188
189 * cgen.h (symcat.h): #include it.
190 (cgen-bitset.h): #include it.
191 (CGEN_ATTR_VALUE_TYPE): Now a union.
192 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
193 (CGEN_ATTR_ENTRY): 'value' now unsigned.
194 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
195 * cgen-bitset.h: New file.
196
1972005-09-30 Catherine Moore <clm@cm00re.com>
198
199 * bfin.h: New file.
200
2012005-10-24 Jan Beulich <jbeulich@novell.com>
202
203 * ia64.h (enum ia64_opnd): Move memory operand out of set of
204 indirect operands.
205
2062005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
207
208 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
209 Add FLAG_STRICT to pa10 ftest opcode.
210
2112005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
212
213 * hppa.h (pa_opcodes): Remove lha entries.
214
2152005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
216
217 * hppa.h (FLAG_STRICT): Revise comment.
218 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
219 before corresponding pa11 opcodes. Add strict pa10 register-immediate
220 entries for "fdc".
221
2222005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
223
224 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
225
2262005-09-06 Chao-ying Fu <fu@mips.com>
227
228 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
229 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
230 define.
231 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
232 (INSN_ASE_MASK): Update to include INSN_MT.
233 (INSN_MT): New define for MT ASE.
234
2352005-08-25 Chao-ying Fu <fu@mips.com>
236
237 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
238 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
239 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
240 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
241 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
242 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
243 instructions.
244 (INSN_DSP): New define for DSP ASE.
245
2462005-08-18 Alan Modra <amodra@bigpond.net.au>
247
248 * a29k.h: Delete.
249
2502005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
251
252 * ppc.h (PPC_OPCODE_E300): Define.
253
2542005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
255
256 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
257
2582005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
259
260 PR gas/336
261 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
262 and pitlb.
263
2642005-07-27 Jan Beulich <jbeulich@novell.com>
265
266 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
267 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
268 Add movq-s as 64-bit variants of movd-s.
269
2702005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
271
272 * hppa.h: Fix punctuation in comment.
273
274 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
275 implicit space-register addressing. Set space-register bits on opcodes
276 using implicit space-register addressing. Add various missing pa20
277 long-immediate opcodes. Remove various opcodes using implicit 3-bit
278 space-register addressing. Use "fE" instead of "fe" in various
279 fstw opcodes.
280
2812005-07-18 Jan Beulich <jbeulich@novell.com>
282
283 * i386.h (i386_optab): Operands of aam and aad are unsigned.
284
2852007-07-15 H.J. Lu <hongjiu.lu@intel.com>
286
287 * i386.h (i386_optab): Support Intel VMX Instructions.
288
2892005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
290
291 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
292
2932005-07-05 Jan Beulich <jbeulich@novell.com>
294
295 * i386.h (i386_optab): Add new insns.
296
2972005-07-01 Nick Clifton <nickc@redhat.com>
298
299 * sparc.h: Add typedefs to structure declarations.
300
3012005-06-20 H.J. Lu <hongjiu.lu@intel.com>
302
303 PR 1013
304 * i386.h (i386_optab): Update comments for 64bit addressing on
305 mov. Allow 64bit addressing for mov and movq.
306
3072005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
308
309 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
310 respectively, in various floating-point load and store patterns.
311
3122005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
313
314 * hppa.h (FLAG_STRICT): Correct comment.
315 (pa_opcodes): Update load and store entries to allow both PA 1.X and
316 PA 2.0 mneumonics when equivalent. Entries with cache control
317 completers now require PA 1.1. Adjust whitespace.
318
3192005-05-19 Anton Blanchard <anton@samba.org>
320
321 * ppc.h (PPC_OPCODE_POWER5): Define.
322
3232005-05-10 Nick Clifton <nickc@redhat.com>
324
325 * Update the address and phone number of the FSF organization in
326 the GPL notices in the following files:
327 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
328 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
329 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
330 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
331 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
332 tic54x.h, tic80.h, v850.h, vax.h
333
3342005-05-09 Jan Beulich <jbeulich@novell.com>
335
336 * i386.h (i386_optab): Add ht and hnt.
337
3382005-04-18 Mark Kettenis <kettenis@gnu.org>
339
340 * i386.h: Insert hyphens into selected VIA PadLock extensions.
341 Add xcrypt-ctr. Provide aliases without hyphens.
342
3432005-04-13 H.J. Lu <hongjiu.lu@intel.com>
344
345 Moved from ../ChangeLog
346
347 2005-04-12 Paul Brook <paul@codesourcery.com>
348 * m88k.h: Rename psr macros to avoid conflicts.
349
350 2005-03-12 Zack Weinberg <zack@codesourcery.com>
351 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
352 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
353 and ARM_ARCH_V6ZKT2.
354
355 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
356 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
357 Remove redundant instruction types.
358 (struct argument): X_op - new field.
359 (struct cst4_entry): Remove.
360 (no_op_insn): Declare.
361
362 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
363 * crx.h (enum argtype): Rename types, remove unused types.
364
365 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
366 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
367 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
368 (enum operand_type): Rearrange operands, edit comments.
369 replace us<N> with ui<N> for unsigned immediate.
370 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
371 displacements (respectively).
372 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
373 (instruction type): Add NO_TYPE_INS.
374 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
375 (operand_entry): New field - 'flags'.
376 (operand flags): New.
377
378 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
379 * crx.h (operand_type): Remove redundant types i3, i4,
380 i5, i8, i12.
381 Add new unsigned immediate types us3, us4, us5, us16.
382
3832005-04-12 Mark Kettenis <kettenis@gnu.org>
384
385 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
386 adjust them accordingly.
387
3882005-04-01 Jan Beulich <jbeulich@novell.com>
389
390 * i386.h (i386_optab): Add rdtscp.
391
3922005-03-29 H.J. Lu <hongjiu.lu@intel.com>
393
394 * i386.h (i386_optab): Don't allow the `l' suffix for moving
395 between memory and segment register. Allow movq for moving between
396 general-purpose register and segment register.
397
3982005-02-09 Jan Beulich <jbeulich@novell.com>
399
400 PR gas/707
401 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
402 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
403 fnstsw.
404
4052006-02-07 Nathan Sidwell <nathan@codesourcery.com>
406
407 * m68k.h (m68008, m68ec030, m68882): Remove.
408 (m68k_mask): New.
409 (cpu_m68k, cpu_cf): New.
410 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
411 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
412
4132005-01-25 Alexandre Oliva <aoliva@redhat.com>
414
415 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
416 * cgen.h (enum cgen_parse_operand_type): Add
417 CGEN_PARSE_OPERAND_SYMBOLIC.
418
4192005-01-21 Fred Fish <fnf@specifixinc.com>
420
421 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
422 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
423 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
424
4252005-01-19 Fred Fish <fnf@specifixinc.com>
426
427 * mips.h (struct mips_opcode): Add new pinfo2 member.
428 (INSN_ALIAS): New define for opcode table entries that are
429 specific instances of another entry, such as 'move' for an 'or'
430 with a zero operand.
431 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
432 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
433
4342004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
435
436 * mips.h (CPU_RM9000): Define.
437 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
438
4392004-11-25 Jan Beulich <jbeulich@novell.com>
440
441 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
442 to/from test registers are illegal in 64-bit mode. Add missing
443 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
444 (previously one had to explicitly encode a rex64 prefix). Re-enable
445 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
446 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
447
4482004-11-23 Jan Beulich <jbeulich@novell.com>
449
450 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
451 available only with SSE2. Change the MMX additions introduced by SSE
452 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
453 instructions by their now designated identifier (since combining i686
454 and 3DNow! does not really imply 3DNow!A).
455
4562004-11-19 Alan Modra <amodra@bigpond.net.au>
457
458 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
459 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
460
4612004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
462 Vineet Sharma <vineets@noida.hcltech.com>
463
464 * maxq.h: New file: Disassembly information for the maxq port.
465
4662004-11-05 H.J. Lu <hongjiu.lu@intel.com>
467
468 * i386.h (i386_optab): Put back "movzb".
469
4702004-11-04 Hans-Peter Nilsson <hp@axis.com>
471
472 * cris.h (enum cris_insn_version_usage): Tweak formatting and
473 comments. Remove member cris_ver_sim. Add members
474 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
475 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
476 (struct cris_support_reg, struct cris_cond15): New types.
477 (cris_conds15): Declare.
478 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
479 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
480 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
481 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
482 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
483 SIZE_FIELD_UNSIGNED.
484
4852004-11-04 Jan Beulich <jbeulich@novell.com>
486
487 * i386.h (sldx_Suf): Remove.
488 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
489 (q_FP): Define, implying no REX64.
490 (x_FP, sl_FP): Imply FloatMF.
491 (i386_optab): Split reg and mem forms of moving from segment registers
492 so that the memory forms can ignore the 16-/32-bit operand size
493 distinction. Adjust a few others for Intel mode. Remove *FP uses from
494 all non-floating-point instructions. Unite 32- and 64-bit forms of
495 movsx, movzx, and movd. Adjust floating point operations for the above
496 changes to the *FP macros. Add DefaultSize to floating point control
497 insns operating on larger memory ranges. Remove left over comments
498 hinting at certain insns being Intel-syntax ones where the ones
499 actually meant are already gone.
500
5012004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
502
503 * crx.h: Add COPS_REG_INS - Coprocessor Special register
504 instruction type.
505
5062004-09-30 Paul Brook <paul@codesourcery.com>
507
508 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
509 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
510
5112004-09-11 Theodore A. Roth <troth@openavr.org>
512
513 * avr.h: Add support for
514 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
515
5162004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
517
518 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
519
5202004-08-24 Dmitry Diky <diwil@spec.ru>
521
522 * msp430.h (msp430_opc): Add new instructions.
523 (msp430_rcodes): Declare new instructions.
524 (msp430_hcodes): Likewise..
525
5262004-08-13 Nick Clifton <nickc@redhat.com>
527
528 PR/301
529 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
530 processors.
531
5322004-08-30 Michal Ludvig <mludvig@suse.cz>
533
534 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
535
5362004-07-22 H.J. Lu <hongjiu.lu@intel.com>
537
538 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
539
5402004-07-21 Jan Beulich <jbeulich@novell.com>
541
542 * i386.h: Adjust instruction descriptions to better match the
543 specification.
544
5452004-07-16 Richard Earnshaw <rearnsha@arm.com>
546
547 * arm.h: Remove all old content. Replace with architecture defines
548 from gas/config/tc-arm.c.
549
5502004-07-09 Andreas Schwab <schwab@suse.de>
551
552 * m68k.h: Fix comment.
553
5542004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
555
556 * crx.h: New file.
557
5582004-06-24 Alan Modra <amodra@bigpond.net.au>
559
560 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
561
5622004-05-24 Peter Barada <peter@the-baradas.com>
563
564 * m68k.h: Add 'size' to m68k_opcode.
565
5662004-05-05 Peter Barada <peter@the-baradas.com>
567
568 * m68k.h: Switch from ColdFire chip name to core variant.
569
5702004-04-22 Peter Barada <peter@the-baradas.com>
571
572 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
573 descriptions for new EMAC cases.
574 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
575 handle Motorola MAC syntax.
576 Allow disassembly of ColdFire V4e object files.
577
5782004-03-16 Alan Modra <amodra@bigpond.net.au>
579
580 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
581
5822004-03-12 Jakub Jelinek <jakub@redhat.com>
583
584 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
585
5862004-03-12 Michal Ludvig <mludvig@suse.cz>
587
588 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
589
5902004-03-12 Michal Ludvig <mludvig@suse.cz>
591
592 * i386.h (i386_optab): Added xstore/xcrypt insns.
593
5942004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
595
596 * h8300.h (32bit ldc/stc): Add relaxing support.
597
5982004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
599
600 * h8300.h (BITOP): Pass MEMRELAX flag.
601
6022004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
603
604 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
605 except for the H8S.
606
607For older changes see ChangeLog-9103
608\f
609Local Variables:
610mode: change-log
611left-margin: 8
612fill-column: 74
613version-control: never
614End:
e9f53129
AM		 6152006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
616 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
617 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
618 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
619 Alan Modra <amodra@bigpond.net.au>
620
621 * spu-insns.h: New file.
622 * spu.h: New file.
623
ede602d7
AM		 6242006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
625
626 * ppc.h (PPC_OPCODE_CELL): Define.
627
7918206c
MM		 6282006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
629
630 * i386.h : Modify opcode to support for the change in POPCNT opcode
631 in amdfam10 architecture.
632
ef05d495
L		 6332006-09-28 H.J. Lu <hongjiu.lu@intel.com>
634
635 * i386.h: Replace CpuMNI with CpuSSSE3.
636
2d447fca
JM		 6372006-09-26 Mark Shinwell <shinwell@codesourcery.com>
638 Joseph Myers <joseph@codesourcery.com>
639 Ian Lance Taylor <ian@wasabisystems.com>
640 Ben Elliston <bje@wasabisystems.com>
641
642 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
643
1c0d3aa6
NC		 6442006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
645
646 * score-datadep.h: New file.
647 * score-inst.h: New file.
648
c2f0420e
L		 6492006-07-14 H.J. Lu <hongjiu.lu@intel.com>
650
651 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
652 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
653 movdq2q and movq2dq.
654
050dfa73
MM		 6552006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
656 Michael Meissner <michael.meissner@amd.com>
657
658 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
659
15965411
L		 6602006-06-12 H.J. Lu <hongjiu.lu@intel.com>
661
662 * i386.h (i386_optab): Add "nop" with memory reference.
663
46e883c5
L		 6642006-06-12 H.J. Lu <hongjiu.lu@intel.com>
665
666 * i386.h (i386_optab): Update comment for 64bit NOP.
667
9622b051
AM		 6682006-06-06 Ben Elliston <bje@au.ibm.com>
669 Anton Blanchard <anton@samba.org>
670
671 * ppc.h (PPC_OPCODE_POWER6): Define.
672 Adjust whitespace.
673
a9e24354
TS		 6742006-06-05 Thiemo Seufer <ths@mips.com>
675
676 * mips.h: Improve description of MT flags.
677
a596001e
RS		 6782006-05-25 Richard Sandiford <richard@codesourcery.com>
679
680 * m68k.h (mcf_mask): Define.
681
d43b4baf
TS		 6822006-05-05 Thiemo Seufer <ths@mips.com>
683 David Ung <davidu@mips.com>
684
685 * mips.h (enum): Add macro M_CACHE_AB.
686
39a7806d
TS		 6872006-05-04 Thiemo Seufer <ths@mips.com>
688 Nigel Stephens <nigel@mips.com>
689 David Ung <davidu@mips.com>
690
691 * mips.h: Add INSN_SMARTMIPS define.
692
9bcd4f99
TS		 6932006-04-30 Thiemo Seufer <ths@mips.com>
694 David Ung <davidu@mips.com>
695
696 * mips.h: Defines udi bits and masks. Add description of
697 characters which may appear in the args field of udi
698 instructions.
699
ef0ee844
TS		 7002006-04-26 Thiemo Seufer <ths@networkno.de>
701
702 * mips.h: Improve comments describing the bitfield instruction
703 fields.
704
f7675147
L		 7052006-04-26 Julian Brown <julian@codesourcery.com>
706
707 * arm.h (FPU_VFP_EXT_V3): Define constant.
708 (FPU_NEON_EXT_V1): Likewise.
709 (FPU_VFP_HARD): Update.
710 (FPU_VFP_V3): Define macro.
711 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
712
ef0ee844 7132006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 714
715 * avr.h (AVR_ISA_PWMx): New.
716
2da12c60
NS		 7172006-03-28 Nathan Sidwell <nathan@codesourcery.com>
718
719 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
720 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
721 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
722 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
723 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
724
0715c387
PB		 7252006-03-10 Paul Brook <paul@codesourcery.com>
726
727 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
728
34bdd094
DA		 7292006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
730
731 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
732 first. Correct mask of bb "B" opcode.
733
331d2d0d
L		 7342006-02-27 H.J. Lu <hongjiu.lu@intel.com>
735
736 * i386.h (i386_optab): Support Intel Merom New Instructions.
737
62b3e311
PB		 7382006-02-24 Paul Brook <paul@codesourcery.com>
739
740 * arm.h: Add V7 feature bits.
741
59cf82fe
L		 7422006-02-23 H.J. Lu <hongjiu.lu@intel.com>
743
744 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
745
e74cfd16
PB		 7462006-01-31 Paul Brook <paul@codesourcery.com>
747 Richard Earnshaw <rearnsha@arm.com>
748
749 * arm.h: Use ARM_CPU_FEATURE.
750 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
751 (arm_feature_set): Change to a structure.
752 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
753 ARM_FEATURE): New macros.
754
5b3f8a92
HPN		 7552005-12-07 Hans-Peter Nilsson <hp@axis.com>
756
757 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
758 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
759 (ADD_PC_INCR_OPCODE): Don't define.
760
cb712a9e
L		 7612005-12-06 H.J. Lu <hongjiu.lu@intel.com>
762
763 PR gas/1874
764 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
765
0499d65b
TS		 7662005-11-14 David Ung <davidu@mips.com>
767
768 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
769 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
770 save/restore encoding of the args field.
771
ea5ca089
DB		 7722005-10-28 Dave Brolley <brolley@redhat.com>
773
774 Contribute the following changes:
775 2005-02-16 Dave Brolley <brolley@redhat.com>
776
777 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
778 cgen_isa_mask_* to cgen_bitset_*.
779 * cgen.h: Likewise.
780
16175d96
DB		 781 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
782
783 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
784 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
785 (CGEN_CPU_TABLE): Make isas a ponter.
786
787 2003-09-29 Dave Brolley <brolley@redhat.com>
788
789 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
790 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
791 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
792
793 2002-12-13 Dave Brolley <brolley@redhat.com>
794
795 * cgen.h (symcat.h): #include it.
796 (cgen-bitset.h): #include it.
797 (CGEN_ATTR_VALUE_TYPE): Now a union.
798 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
799 (CGEN_ATTR_ENTRY): 'value' now unsigned.
800 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
801 * cgen-bitset.h: New file.
802
3c9b82ba
NC		 8032005-09-30 Catherine Moore <clm@cm00re.com>
804
805 * bfin.h: New file.
806
6a2375c6
JB		 8072005-10-24 Jan Beulich <jbeulich@novell.com>
808
809 * ia64.h (enum ia64_opnd): Move memory operand out of set of
810 indirect operands.
811
c06a12f8
DA		 8122005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
813
814 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
815 Add FLAG_STRICT to pa10 ftest opcode.
816
4d443107
DA		 8172005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
818
819 * hppa.h (pa_opcodes): Remove lha entries.
820
f0a3b40f
DA		 8212005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
822
823 * hppa.h (FLAG_STRICT): Revise comment.
824 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
825 before corresponding pa11 opcodes. Add strict pa10 register-immediate
826 entries for "fdc".
827
1b7e1362
DA		 8282005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
829
830 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
831
089b39de
CF		 8322005-09-06 Chao-ying Fu <fu@mips.com>
833
834 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
835 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
836 define.
837 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
838 (INSN_ASE_MASK): Update to include INSN_MT.
839 (INSN_MT): New define for MT ASE.
840
93c34b9b
CF		 8412005-08-25 Chao-ying Fu <fu@mips.com>
842
843 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
844 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
845 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
846 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
847 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
848 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
849 instructions.
850 (INSN_DSP): New define for DSP ASE.
851
848cf006
AM		 8522005-08-18 Alan Modra <amodra@bigpond.net.au>
853
854 * a29k.h: Delete.
855
36ae0db3
DJ		 8562005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
857
858 * ppc.h (PPC_OPCODE_E300): Define.
859
8c929562
MS		 8602005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
861
862 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
863
f7b8cccc
DA		 8642005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
865
866 PR gas/336
867 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
868 and pitlb.
869
8b5328ac
JB		 8702005-07-27 Jan Beulich <jbeulich@novell.com>
871
872 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
873 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
874 Add movq-s as 64-bit variants of movd-s.
875
f417d200
DA		 8762005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
877
18b3bdfc
DA		 878 * hppa.h: Fix punctuation in comment.
879
f417d200
DA		 880 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
881 implicit space-register addressing. Set space-register bits on opcodes
882 using implicit space-register addressing. Add various missing pa20
883 long-immediate opcodes. Remove various opcodes using implicit 3-bit
884 space-register addressing. Use "fE" instead of "fe" in various
885 fstw opcodes.
886
9a145ce6
JB		 8872005-07-18 Jan Beulich <jbeulich@novell.com>
888
889 * i386.h (i386_optab): Operands of aam and aad are unsigned.
890
90700ea2
L		 8912007-07-15 H.J. Lu <hongjiu.lu@intel.com>
892
893 * i386.h (i386_optab): Support Intel VMX Instructions.
894
48f130a8
DA		 8952005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
896
897 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
898
30123838
JB		 8992005-07-05 Jan Beulich <jbeulich@novell.com>
900
901 * i386.h (i386_optab): Add new insns.
902
47b0e7ad
NC		 9032005-07-01 Nick Clifton <nickc@redhat.com>
904
905 * sparc.h: Add typedefs to structure declarations.
906
b300c311
L		 9072005-06-20 H.J. Lu <hongjiu.lu@intel.com>
908
909 PR 1013
910 * i386.h (i386_optab): Update comments for 64bit addressing on
911 mov. Allow 64bit addressing for mov and movq.
912
2db495be
DA		 9132005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
914
915 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
916 respectively, in various floating-point load and store patterns.
917
caa05036
DA		 9182005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
919
920 * hppa.h (FLAG_STRICT): Correct comment.
921 (pa_opcodes): Update load and store entries to allow both PA 1.X and
922 PA 2.0 mneumonics when equivalent. Entries with cache control
923 completers now require PA 1.1. Adjust whitespace.
924
f4411256
AM		 9252005-05-19 Anton Blanchard <anton@samba.org>
926
927 * ppc.h (PPC_OPCODE_POWER5): Define.
928
e172dbf8
NC		 9292005-05-10 Nick Clifton <nickc@redhat.com>
930
931 * Update the address and phone number of the FSF organization in
932 the GPL notices in the following files:
933 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
934 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
935 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
936 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
937 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
938 tic54x.h, tic80.h, v850.h, vax.h
939
e44823cf
JB		 9402005-05-09 Jan Beulich <jbeulich@novell.com>
941
942 * i386.h (i386_optab): Add ht and hnt.
943
791fe849
MK		 9442005-04-18 Mark Kettenis <kettenis@gnu.org>
945
946 * i386.h: Insert hyphens into selected VIA PadLock extensions.
947 Add xcrypt-ctr. Provide aliases without hyphens.
948
faa7ef87
L		 9492005-04-13 H.J. Lu <hongjiu.lu@intel.com>
950
a63027e5
L		 951 Moved from ../ChangeLog
952
faa7ef87
L		 953 2005-04-12 Paul Brook <paul@codesourcery.com>
954 * m88k.h: Rename psr macros to avoid conflicts.
955
956 2005-03-12 Zack Weinberg <zack@codesourcery.com>
957 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
958 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
959 and ARM_ARCH_V6ZKT2.
960
961 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
962 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
963 Remove redundant instruction types.
964 (struct argument): X_op - new field.
965 (struct cst4_entry): Remove.
966 (no_op_insn): Declare.
967
968 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
969 * crx.h (enum argtype): Rename types, remove unused types.
970
971 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
972 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
973 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
974 (enum operand_type): Rearrange operands, edit comments.
975 replace us<N> with ui<N> for unsigned immediate.
976 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
977 displacements (respectively).
978 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
979 (instruction type): Add NO_TYPE_INS.
980 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
981 (operand_entry): New field - 'flags'.
982 (operand flags): New.
983
984 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
985 * crx.h (operand_type): Remove redundant types i3, i4,
986 i5, i8, i12.
987 Add new unsigned immediate types us3, us4, us5, us16.
988
bc4bd9ab
MK		 9892005-04-12 Mark Kettenis <kettenis@gnu.org>
990
991 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
992 adjust them accordingly.
993
373ff435
JB		 9942005-04-01 Jan Beulich <jbeulich@novell.com>
995
996 * i386.h (i386_optab): Add rdtscp.
997
4cc91dba
L		 9982005-03-29 H.J. Lu <hongjiu.lu@intel.com>
999
1000 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1001 between memory and segment register. Allow movq for moving between
1002 general-purpose register and segment register.
4cc91dba 1003
9ae09ff9
JB		 10042005-02-09 Jan Beulich <jbeulich@novell.com>
1005
1006 PR gas/707
1007 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1008 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1009 fnstsw.
1010
638e7a64
NS		 10112006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1012
1013 * m68k.h (m68008, m68ec030, m68882): Remove.
1014 (m68k_mask): New.
1015 (cpu_m68k, cpu_cf): New.
1016 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1017 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1018
90219bd0
AO		 10192005-01-25 Alexandre Oliva <aoliva@redhat.com>
1020
1021 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1022 * cgen.h (enum cgen_parse_operand_type): Add
1023 CGEN_PARSE_OPERAND_SYMBOLIC.
1024
239cb185
FF		 10252005-01-21 Fred Fish <fnf@specifixinc.com>
1026
1027 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1028 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1029 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1030
dc9a9f39
FF		 10312005-01-19 Fred Fish <fnf@specifixinc.com>
1032
1033 * mips.h (struct mips_opcode): Add new pinfo2 member.
1034 (INSN_ALIAS): New define for opcode table entries that are
1035 specific instances of another entry, such as 'move' for an 'or'
1036 with a zero operand.
1037 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1038 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1039
98e7aba8
ILT		 10402004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1041
1042 * mips.h (CPU_RM9000): Define.
1043 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1044
37edbb65
JB		 10452004-11-25 Jan Beulich <jbeulich@novell.com>
1046
1047 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1048 to/from test registers are illegal in 64-bit mode. Add missing
1049 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1050 (previously one had to explicitly encode a rex64 prefix). Re-enable
1051 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1052 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1053
10542004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 1055
1056 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1057 available only with SSE2. Change the MMX additions introduced by SSE
1058 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1059 instructions by their now designated identifier (since combining i686
1060 and 3DNow! does not really imply 3DNow!A).
1061
f5c7edf4
AM		 10622004-11-19 Alan Modra <amodra@bigpond.net.au>
1063
1064 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1065 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1066
7499d566
NC		 10672004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1068 Vineet Sharma <vineets@noida.hcltech.com>
1069
1070 * maxq.h: New file: Disassembly information for the maxq port.
1071
bcb9eebe
L		 10722004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1073
1074 * i386.h (i386_optab): Put back "movzb".
1075
94bb3d38
HPN		 10762004-11-04 Hans-Peter Nilsson <hp@axis.com>
1077
1078 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1079 comments. Remove member cris_ver_sim. Add members
1080 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1081 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1082 (struct cris_support_reg, struct cris_cond15): New types.
1083 (cris_conds15): Declare.
1084 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1085 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1086 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1087 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1088 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1089 SIZE_FIELD_UNSIGNED.
1090
37edbb65 10912004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 1092
1093 * i386.h (sldx_Suf): Remove.
1094 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1095 (q_FP): Define, implying no REX64.
1096 (x_FP, sl_FP): Imply FloatMF.
1097 (i386_optab): Split reg and mem forms of moving from segment registers
1098 so that the memory forms can ignore the 16-/32-bit operand size
1099 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1100 all non-floating-point instructions. Unite 32- and 64-bit forms of
1101 movsx, movzx, and movd. Adjust floating point operations for the above
1102 changes to the *FP macros. Add DefaultSize to floating point control
1103 insns operating on larger memory ranges. Remove left over comments
1104 hinting at certain insns being Intel-syntax ones where the ones
1105 actually meant are already gone.
1106
48c9f030
NC		 11072004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1108
1109 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1110 instruction type.
1111
0dd132b6
NC		 11122004-09-30 Paul Brook <paul@codesourcery.com>
1113
1114 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1115 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1116
23794b24
MM		 11172004-09-11 Theodore A. Roth <troth@openavr.org>
1118
1119 * avr.h: Add support for
1120 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1121
2a309db0
AM		 11222004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1123
1124 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1125
b18c562e
NC		 11262004-08-24 Dmitry Diky <diwil@spec.ru>
1127
1128 * msp430.h (msp430_opc): Add new instructions.
1129 (msp430_rcodes): Declare new instructions.
1130 (msp430_hcodes): Likewise..
1131
45d313cd
NC		 11322004-08-13 Nick Clifton <nickc@redhat.com>
1133
1134 PR/301
1135 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1136 processors.
1137
30d1c836
ML		 11382004-08-30 Michal Ludvig <mludvig@suse.cz>
1139
1140 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1141
9a45f1c2
L		 11422004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1143
1144 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1145
543613e9
NC		 11462004-07-21 Jan Beulich <jbeulich@novell.com>
1147
1148 * i386.h: Adjust instruction descriptions to better match the
1149 specification.
1150
b781e558
RE		 11512004-07-16 Richard Earnshaw <rearnsha@arm.com>
1152
1153 * arm.h: Remove all old content. Replace with architecture defines
1154 from gas/config/tc-arm.c.
1155
8577e690
AS		 11562004-07-09 Andreas Schwab <schwab@suse.de>
1157
1158 * m68k.h: Fix comment.
1159
1fe1f39c
NC		 11602004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1161
1162 * crx.h: New file.
1163
1d9f512f
AM		 11642004-06-24 Alan Modra <amodra@bigpond.net.au>
1165
1166 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1167
be8c092b
NC		 11682004-05-24 Peter Barada <peter@the-baradas.com>
1169
1170 * m68k.h: Add 'size' to m68k_opcode.
1171
6b6e92f4
NC		 11722004-05-05 Peter Barada <peter@the-baradas.com>
1173
1174 * m68k.h: Switch from ColdFire chip name to core variant.
1175
11762004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 1177
1178 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1179 descriptions for new EMAC cases.
1180 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1181 handle Motorola MAC syntax.
1182 Allow disassembly of ColdFire V4e object files.
1183
fdd12ef3
AM		 11842004-03-16 Alan Modra <amodra@bigpond.net.au>
1185
1186 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1187
3922a64c
L		 11882004-03-12 Jakub Jelinek <jakub@redhat.com>
1189
1190 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1191
1f45d988
ML		 11922004-03-12 Michal Ludvig <mludvig@suse.cz>
1193
1194 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1195
0f10071e
ML		 11962004-03-12 Michal Ludvig <mludvig@suse.cz>
1197
1198 * i386.h (i386_optab): Added xstore/xcrypt insns.
1199
3255318a
NC		 12002004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1201
1202 * h8300.h (32bit ldc/stc): Add relaxing support.
1203
ca9a79a1 12042004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 1205
ca9a79a1
NC		 1206 * h8300.h (BITOP): Pass MEMRELAX flag.
1207
875a0b14
NC		 12082004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1209
1210 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1211 except for the H8S.
252b5132 1212
c9e214e5 1213For older changes see ChangeLog-9103
252b5132
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1215Local Variables:
c9e214e5
AM		 1216mode: change-log
1217left-margin: 8
1218fill-column: 74
252b5132
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1220End:
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