[thirdparty/binutils-gdb.git] / include / opcode / ChangeLog

2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.

2005-09-06  Chao-ying Fu  <fu@mips.com>

	* mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
	OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
	define.
	Document !, $, *, &, g, +t, +T operand formats for MT instructions.
	(INSN_ASE_MASK): Update to include INSN_MT.
	(INSN_MT): New define for MT ASE.

2005-08-25  Chao-ying Fu  <fu@mips.com>

	* mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
	OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
	OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
	OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
	OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
	Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
	instructions.
	(INSN_DSP): New define for DSP ASE.

2005-08-18  Alan Modra  <amodra@bigpond.net.au>

	* a29k.h: Delete.

2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>

	* ppc.h (PPC_OPCODE_E300): Define.

2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>

	* s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.

2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	PR gas/336
 	* hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
	and pitlb.

2005-07-27  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add comment to movd. Use LongMem for all
	movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
	Add movq-s as 64-bit variants of movd-s.

2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h: Fix punctuation in comment.

	* hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
	implicit space-register addressing.  Set space-register bits on opcodes
	using implicit space-register addressing.  Add various missing pa20
	long-immediate opcodes.  Remove various opcodes using implicit 3-bit
	space-register addressing.  Use "fE" instead of "fe" in various
	fstw opcodes.

2005-07-18  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Operands of aam and aad are unsigned.

2007-07-15  H.J. Lu <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Support Intel VMX Instructions.

2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.

2005-07-05  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add new insns.

2005-07-01  Nick Clifton  <nickc@redhat.com>

	* sparc.h: Add typedefs to structure declarations.

2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>

	PR 1013
	* i386.h (i386_optab): Update comments for 64bit addressing on
	mov. Allow 64bit addressing for mov and movq.

2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
	respectively, in various floating-point load and store patterns.

2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h (FLAG_STRICT): Correct comment.
	(pa_opcodes): Update load and store entries to allow both PA 1.X and
	PA 2.0 mneumonics when equivalent.  Entries with cache control
	completers now require PA 1.1.  Adjust whitespace.

2005-05-19  Anton Blanchard  <anton@samba.org>

	* ppc.h (PPC_OPCODE_POWER5): Define.

2005-05-10  Nick Clifton  <nickc@redhat.com>

	* Update the address and phone number of the FSF organization in
	the GPL notices in the following files:
	a29k.h,	alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
	crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
	i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
	mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
	pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
	tic54x.h, tic80.h, v850.h, vax.h

2005-05-09  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add ht and hnt.

2005-04-18  Mark Kettenis  <kettenis@gnu.org>

	* i386.h: Insert hyphens into selected VIA PadLock extensions.
	Add xcrypt-ctr.  Provide aliases without hyphens.

2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>

	Moved from ../ChangeLog

	2005-04-12  Paul Brook  <paul@codesourcery.com>
	* m88k.h: Rename psr macros to avoid conflicts.

	2005-03-12  Zack Weinberg  <zack@codesourcery.com>
	* arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
	Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
	and ARM_ARCH_V6ZKT2.

	2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
	Remove redundant instruction types.
	(struct argument): X_op - new field.
	(struct cst4_entry): Remove.
	(no_op_insn): Declare.

	2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (enum argtype): Rename types, remove unused types.

	2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
	(enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
	(enum operand_type): Rearrange operands, edit comments.
	replace us<N> with ui<N> for unsigned immediate.
	replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
	displacements (respectively).
	replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
	(instruction type): Add NO_TYPE_INS.
	(instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
	(operand_entry): New field - 'flags'.
	(operand flags): New.

	2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (operand_type): Remove redundant types i3, i4,
	i5, i8, i12.
	Add new unsigned immediate types us3, us4, us5, us16.

2005-04-12  Mark Kettenis  <kettenis@gnu.org>

	* i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
	adjust them accordingly.

2005-04-01  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add rdtscp.

2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Don't allow the `l' suffix for moving
	between memory and segment register. Allow movq for moving between
	general-purpose register and segment register.

2005-02-09  Jan Beulich  <jbeulich@novell.com>

	PR gas/707
	* i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
	FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
	fnstsw.

2005-01-25  Alexandre Oliva  <aoliva@redhat.com>

	2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
	* cgen.h (enum cgen_parse_operand_type): Add
	CGEN_PARSE_OPERAND_SYMBOLIC.

2005-01-21  Fred Fish  <fnf@specifixinc.com>

	* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
	Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
	Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.

2005-01-19  Fred Fish  <fnf@specifixinc.com>

	* mips.h (struct mips_opcode): Add new pinfo2 member.
	(INSN_ALIAS): New define for opcode table entries that are
	specific instances of another entry, such as 'move' for an 'or'
	with a zero operand.
	(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
	(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.

2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>

	* mips.h (CPU_RM9000): Define.
	(OPCODE_IS_MEMBER): Handle CPU_RM9000.

2004-11-25 Jan Beulich  <jbeulich@novell.com>

	* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
	to/from test registers are illegal in 64-bit mode. Add missing
	NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
	(previously one had to explicitly encode a rex64 prefix). Re-enable
	lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
	support it there. Add cmpxchg16b as per Intel's 64-bit documentation.

2004-11-23 Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
	available only with SSE2. Change the MMX additions introduced by SSE
	and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
	instructions by their now designated identifier (since combining i686
	and 3DNow! does not really imply 3DNow!A).

2004-11-19  Alan Modra  <amodra@bigpond.net.au>

	* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
	struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.

2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
	    Vineet Sharma      <vineets@noida.hcltech.com>

	* maxq.h: New file: Disassembly information for the maxq port.

2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Put back "movzb".

2004-11-04  Hans-Peter Nilsson  <hp@axis.com>

	* cris.h (enum cris_insn_version_usage): Tweak formatting and
	comments.  Remove member cris_ver_sim.  Add members
	cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
	cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
	(struct cris_support_reg, struct cris_cond15): New types.
	(cris_conds15): Declare.
	(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
	(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
	(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
	(NOP_Z_BITS): Define in terms of NOP_OPCODE.
	(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
	SIZE_FIELD_UNSIGNED.

2004-11-04 Jan Beulich  <jbeulich@novell.com>

	* i386.h (sldx_Suf): Remove.
	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
	(q_FP): Define, implying no REX64.
	(x_FP, sl_FP): Imply FloatMF.
	(i386_optab): Split reg and mem forms of moving from segment registers
	so that the memory forms can ignore the 16-/32-bit operand size
	distinction. Adjust a few others for Intel mode. Remove *FP uses from
	all non-floating-point instructions. Unite 32- and 64-bit forms of
	movsx, movzx, and movd. Adjust floating point operations for the above
	changes to the *FP macros. Add DefaultSize to floating point control
	insns operating on larger memory ranges. Remove left over comments
	hinting at certain insns being Intel-syntax ones where the ones
	actually meant are already gone.

2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>

	* crx.h: Add COPS_REG_INS - Coprocessor Special register
	instruction type.

2004-09-30  Paul Brook  <paul@codesourcery.com>

	* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
	(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.

2004-09-11  Theodore A. Roth  <troth@openavr.org>

	* avr.h: Add support for
	atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.

2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>

	* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.

2004-08-24  Dmitry Diky  <diwil@spec.ru>

	* msp430.h (msp430_opc): Add new instructions.
	(msp430_rcodes): Declare new instructions.
	(msp430_hcodes): Likewise..

2004-08-13  Nick Clifton  <nickc@redhat.com>

	PR/301
	* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
	processors.

2004-08-30  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.

2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.

2004-07-21  Jan Beulich  <jbeulich@novell.com>

	* i386.h: Adjust instruction descriptions to better match the
	specification.

2004-07-16  Richard Earnshaw  <rearnsha@arm.com>

	* arm.h: Remove all old content.  Replace with architecture defines
	from gas/config/tc-arm.c.

2004-07-09  Andreas Schwab  <schwab@suse.de>

	* m68k.h: Fix comment.

2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>

	* crx.h: New file.

2004-06-24  Alan Modra  <amodra@bigpond.net.au>

	* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.

2004-05-24  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Add 'size' to m68k_opcode.

2004-05-05  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Switch from ColdFire chip name to core variant.

2004-04-22  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Add mcfmac/mcfemac definitions.  Update operand
	descriptions for new EMAC cases.
	Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
	handle Motorola MAC syntax.
	Allow disassembly of ColdFire V4e object files.

2004-03-16  Alan Modra  <amodra@bigpond.net.au>

	* ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.

2004-03-12  Jakub Jelinek  <jakub@redhat.com>

	* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.

2004-03-12  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added xstore as an alias for xstorerng.

2004-03-12  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added xstore/xcrypt insns.

2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (32bit ldc/stc): Add relaxing support.

2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (BITOP): Pass MEMRELAX flag.

2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
	except for the H8S.

For older changes see ChangeLog-9103
\f
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Commit	Line	Data
1b7e1362 DA	1	2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	2
	3	* hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
	4
089b39de CF	5	2005-09-06 Chao-ying Fu <fu@mips.com>
	6
	7	* mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
	8	OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
	9	define.
	10	Document !, $, *, &, g, +t, +T operand formats for MT instructions.
	11	(INSN_ASE_MASK): Update to include INSN_MT.
	12	(INSN_MT): New define for MT ASE.
	13
93c34b9b CF	14	2005-08-25 Chao-ying Fu <fu@mips.com>
	15
	16	* mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
	17	OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
	18	OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
	19	OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
	20	OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
	21	Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
	22	instructions.
	23	(INSN_DSP): New define for DSP ASE.
	24
848cf006 AM	25	2005-08-18 Alan Modra <amodra@bigpond.net.au>
	26
	27	* a29k.h: Delete.
	28
36ae0db3 DJ	29	2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
	30
	31	* ppc.h (PPC_OPCODE_E300): Define.
	32
8c929562 MS	33	2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
	34
	35	* s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
	36
f7b8cccc DA	37	2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	38
	39	PR gas/336
	40	* hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
	41	and pitlb.
	42
8b5328ac JB	43	2005-07-27 Jan Beulich <jbeulich@novell.com>
	44
	45	* i386.h (i386_optab): Add comment to movd. Use LongMem for all
	46	movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
	47	Add movq-s as 64-bit variants of movd-s.
	48
f417d200 DA	49	2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
f417d200 DA	50
18b3bdfc DA	51	* hppa.h: Fix punctuation in comment.
18b3bdfc DA	52
f417d200 DA	53	* hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
	54	implicit space-register addressing. Set space-register bits on opcodes
	55	using implicit space-register addressing. Add various missing pa20
	56	long-immediate opcodes. Remove various opcodes using implicit 3-bit
	57	space-register addressing. Use "fE" instead of "fe" in various
	58	fstw opcodes.
	59
9a145ce6 JB	60	2005-07-18 Jan Beulich <jbeulich@novell.com>
	61
	62	* i386.h (i386_optab): Operands of aam and aad are unsigned.
	63
90700ea2 L	64	2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
	65
	66	* i386.h (i386_optab): Support Intel VMX Instructions.
	67
48f130a8 DA	68	2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	69
	70	* hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
	71
30123838 JB	72	2005-07-05 Jan Beulich <jbeulich@novell.com>
	73
	74	* i386.h (i386_optab): Add new insns.
	75
47b0e7ad NC	76	2005-07-01 Nick Clifton <nickc@redhat.com>
	77
	78	* sparc.h: Add typedefs to structure declarations.
	79
b300c311 L	80	2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
	81
	82	PR 1013
	83	* i386.h (i386_optab): Update comments for 64bit addressing on
	84	mov. Allow 64bit addressing for mov and movq.
	85
2db495be DA	86	2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	87
	88	* hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
	89	respectively, in various floating-point load and store patterns.
	90
caa05036 DA	91	2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	92
	93	* hppa.h (FLAG_STRICT): Correct comment.
	94	(pa_opcodes): Update load and store entries to allow both PA 1.X and
	95	PA 2.0 mneumonics when equivalent. Entries with cache control
	96	completers now require PA 1.1. Adjust whitespace.
	97
f4411256 AM	98	2005-05-19 Anton Blanchard <anton@samba.org>
	99
	100	* ppc.h (PPC_OPCODE_POWER5): Define.
	101
e172dbf8 NC	102	2005-05-10 Nick Clifton <nickc@redhat.com>
	103
	104	* Update the address and phone number of the FSF organization in
	105	the GPL notices in the following files:
	106	a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
	107	crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
	108	i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
	109	mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
	110	pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
	111	tic54x.h, tic80.h, v850.h, vax.h
	112
e44823cf JB	113	2005-05-09 Jan Beulich <jbeulich@novell.com>
	114
	115	* i386.h (i386_optab): Add ht and hnt.
	116
791fe849 MK	117	2005-04-18 Mark Kettenis <kettenis@gnu.org>
	118
	119	* i386.h: Insert hyphens into selected VIA PadLock extensions.
	120	Add xcrypt-ctr. Provide aliases without hyphens.
	121
faa7ef87 L	122	2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
faa7ef87 L	123
a63027e5 L	124	Moved from ../ChangeLog
a63027e5 L	125
faa7ef87 L	126	2005-04-12 Paul Brook <paul@codesourcery.com>
	127	* m88k.h: Rename psr macros to avoid conflicts.
	128
	129	2005-03-12 Zack Weinberg <zack@codesourcery.com>
	130	* arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
	131	Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
	132	and ARM_ARCH_V6ZKT2.
	133
	134	2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
	135	* crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
	136	Remove redundant instruction types.
	137	(struct argument): X_op - new field.
	138	(struct cst4_entry): Remove.
	139	(no_op_insn): Declare.
	140
	141	2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
	142	* crx.h (enum argtype): Rename types, remove unused types.
	143
	144	2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
	145	* crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
	146	(enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
	147	(enum operand_type): Rearrange operands, edit comments.
	148	replace us<N> with ui<N> for unsigned immediate.
	149	replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
	150	displacements (respectively).
	151	replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
	152	(instruction type): Add NO_TYPE_INS.
	153	(instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
	154	(operand_entry): New field - 'flags'.
	155	(operand flags): New.
	156
	157	2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
	158	* crx.h (operand_type): Remove redundant types i3, i4,
	159	i5, i8, i12.
	160	Add new unsigned immediate types us3, us4, us5, us16.
	161
bc4bd9ab MK	162	2005-04-12 Mark Kettenis <kettenis@gnu.org>
	163
	164	* i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
	165	adjust them accordingly.
	166
373ff435 JB	167	2005-04-01 Jan Beulich <jbeulich@novell.com>
	168
	169	* i386.h (i386_optab): Add rdtscp.
	170
4cc91dba L	171	2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
	172
	173	* i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca AS	174	between memory and segment register. Allow movq for moving between
418a8fca AS	175	general-purpose register and segment register.
4cc91dba	176
9ae09ff9 JB	177	2005-02-09 Jan Beulich <jbeulich@novell.com>
	178
	179	PR gas/707
	180	* i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
	181	FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
	182	fnstsw.
	183
90219bd0 AO	184	2005-01-25 Alexandre Oliva <aoliva@redhat.com>
	185
	186	2004-11-10 Alexandre Oliva <aoliva@redhat.com>
	187	* cgen.h (enum cgen_parse_operand_type): Add
	188	CGEN_PARSE_OPERAND_SYMBOLIC.
	189
239cb185 FF	190	2005-01-21 Fred Fish <fnf@specifixinc.com>
	191
	192	* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
	193	Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
	194	Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
	195
dc9a9f39 FF	196	2005-01-19 Fred Fish <fnf@specifixinc.com>
	197
	198	* mips.h (struct mips_opcode): Add new pinfo2 member.
	199	(INSN_ALIAS): New define for opcode table entries that are
	200	specific instances of another entry, such as 'move' for an 'or'
	201	with a zero operand.
	202	(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
	203	(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
	204
98e7aba8 ILT	205	2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
	206
	207	* mips.h (CPU_RM9000): Define.
	208	(OPCODE_IS_MEMBER): Handle CPU_RM9000.
	209
37edbb65 JB	210	2004-11-25 Jan Beulich <jbeulich@novell.com>
	211
	212	* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
	213	to/from test registers are illegal in 64-bit mode. Add missing
	214	NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
	215	(previously one had to explicitly encode a rex64 prefix). Re-enable
	216	lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
	217	support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
	218
	219	2004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e JB	220
	221	* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
	222	available only with SSE2. Change the MMX additions introduced by SSE
	223	and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
	224	instructions by their now designated identifier (since combining i686
	225	and 3DNow! does not really imply 3DNow!A).
	226
f5c7edf4 AM	227	2004-11-19 Alan Modra <amodra@bigpond.net.au>
	228
	229	* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
	230	struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
	231
7499d566 NC	232	2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
	233	Vineet Sharma <vineets@noida.hcltech.com>
	234
	235	* maxq.h: New file: Disassembly information for the maxq port.
	236
bcb9eebe L	237	2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
	238
	239	* i386.h (i386_optab): Put back "movzb".
	240
94bb3d38 HPN	241	2004-11-04 Hans-Peter Nilsson <hp@axis.com>
	242
	243	* cris.h (enum cris_insn_version_usage): Tweak formatting and
	244	comments. Remove member cris_ver_sim. Add members
	245	cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
	246	cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
	247	(struct cris_support_reg, struct cris_cond15): New types.
	248	(cris_conds15): Declare.
	249	(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
	250	(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
	251	(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
	252	(NOP_Z_BITS): Define in terms of NOP_OPCODE.
	253	(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
	254	SIZE_FIELD_UNSIGNED.
	255
37edbb65	256	2004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a JB	257
	258	* i386.h (sldx_Suf): Remove.
	259	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
	260	(q_FP): Define, implying no REX64.
	261	(x_FP, sl_FP): Imply FloatMF.
	262	(i386_optab): Split reg and mem forms of moving from segment registers
	263	so that the memory forms can ignore the 16-/32-bit operand size
	264	distinction. Adjust a few others for Intel mode. Remove *FP uses from
	265	all non-floating-point instructions. Unite 32- and 64-bit forms of
	266	movsx, movzx, and movd. Adjust floating point operations for the above
	267	changes to the *FP macros. Add DefaultSize to floating point control
	268	insns operating on larger memory ranges. Remove left over comments
	269	hinting at certain insns being Intel-syntax ones where the ones
	270	actually meant are already gone.
	271
48c9f030 NC	272	2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
	273
	274	* crx.h: Add COPS_REG_INS - Coprocessor Special register
	275	instruction type.
	276
0dd132b6 NC	277	2004-09-30 Paul Brook <paul@codesourcery.com>
	278
	279	* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
	280	(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
	281
23794b24 MM	282	2004-09-11 Theodore A. Roth <troth@openavr.org>
	283
	284	* avr.h: Add support for
	285	atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
	286
2a309db0 AM	287	2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
	288
	289	* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
	290
b18c562e NC	291	2004-08-24 Dmitry Diky <diwil@spec.ru>
	292
	293	* msp430.h (msp430_opc): Add new instructions.
	294	(msp430_rcodes): Declare new instructions.
	295	(msp430_hcodes): Likewise..
	296
45d313cd NC	297	2004-08-13 Nick Clifton <nickc@redhat.com>
	298
	299	PR/301
	300	* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
	301	processors.
	302
30d1c836 ML	303	2004-08-30 Michal Ludvig <mludvig@suse.cz>
	304
	305	* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
	306
9a45f1c2 L	307	2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
	308
	309	* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
	310
543613e9 NC	311	2004-07-21 Jan Beulich <jbeulich@novell.com>
	312
	313	* i386.h: Adjust instruction descriptions to better match the
	314	specification.
	315
b781e558 RE	316	2004-07-16 Richard Earnshaw <rearnsha@arm.com>
	317
	318	* arm.h: Remove all old content. Replace with architecture defines
	319	from gas/config/tc-arm.c.
	320
8577e690 AS	321	2004-07-09 Andreas Schwab <schwab@suse.de>
	322
	323	* m68k.h: Fix comment.
	324
1fe1f39c NC	325	2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
	326
	327	* crx.h: New file.
	328
1d9f512f AM	329	2004-06-24 Alan Modra <amodra@bigpond.net.au>
	330
	331	* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
	332
be8c092b NC	333	2004-05-24 Peter Barada <peter@the-baradas.com>
	334
	335	* m68k.h: Add 'size' to m68k_opcode.
	336
6b6e92f4 NC	337	2004-05-05 Peter Barada <peter@the-baradas.com>
	338
	339	* m68k.h: Switch from ColdFire chip name to core variant.
	340
	341	2004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b NC	342
	343	* m68k.h: Add mcfmac/mcfemac definitions. Update operand
	344	descriptions for new EMAC cases.
	345	Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
	346	handle Motorola MAC syntax.
	347	Allow disassembly of ColdFire V4e object files.
	348
fdd12ef3 AM	349	2004-03-16 Alan Modra <amodra@bigpond.net.au>
	350
	351	* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
	352
3922a64c L	353	2004-03-12 Jakub Jelinek <jakub@redhat.com>
	354
	355	* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
	356
1f45d988 ML	357	2004-03-12 Michal Ludvig <mludvig@suse.cz>
	358
	359	* i386.h (i386_optab): Added xstore as an alias for xstorerng.
	360
0f10071e ML	361	2004-03-12 Michal Ludvig <mludvig@suse.cz>
	362
	363	* i386.h (i386_optab): Added xstore/xcrypt insns.
	364
3255318a NC	365	2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
	366
	367	* h8300.h (32bit ldc/stc): Add relaxing support.
	368
ca9a79a1	369	2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3	370
ca9a79a1 NC	371	* h8300.h (BITOP): Pass MEMRELAX flag.
ca9a79a1 NC	372
875a0b14 NC	373	2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
	374
	375	* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
	376	except for the H8S.
252b5132	377
c9e214e5	378	For older changes see ChangeLog-9103
252b5132 RH	379	\f
252b5132 RH	380	Local Variables:
c9e214e5 AM	381	mode: change-log
	382	left-margin: 8
	383	fill-column: 74
252b5132 RH	384	version-control: never
252b5132 RH	385	End: