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AArch64: Refactor err_type.
[thirdparty/binutils-gdb.git] / include / opcode / aarch64.h
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a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
219d1afa 3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
c0e7cef7
NC		 40#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
41#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
b6b9ca0c
TC		 42#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
43#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
44#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
a06ea964 45#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 46#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 47#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 48#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
49#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
50#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 51#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 52#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 53#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 54#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 55#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 56#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 57#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 58#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 59#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 60#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
d74d4880 61#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
f482d304 62#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
65a55fbb 63#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
d0f7791c 64#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
a06ea964
NC		 65
66/* Architectures are the sum of the base and extensions. */
67#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
68 AARCH64_FEATURE_FP \
69 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 70#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
71 AARCH64_FEATURE_CRC \
250aafa4 72 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 73 | AARCH64_FEATURE_LSE \
74 | AARCH64_FEATURE_PAN \
75 | AARCH64_FEATURE_LOR \
76 | AARCH64_FEATURE_RDMA)
1924ff75 77#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 78 AARCH64_FEATURE_V8_2 \
1924ff75
SN		 79 | AARCH64_FEATURE_RAS)
80#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 81 AARCH64_FEATURE_V8_3 \
f482d304
RS		 82 | AARCH64_FEATURE_RCPC \
83 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c 84#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
981b557a 85 AARCH64_FEATURE_V8_4 \
d0f7791c
TC		 86 | AARCH64_FEATURE_DOTPROD \
87 | AARCH64_FEATURE_F16_FML)
88f0ea34 88
a06ea964
NC		 89#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
90#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
91
92/* CPU-specific features. */
21b81e67 93typedef unsigned long long aarch64_feature_set;
a06ea964 94
93d8990c
SN		 95#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
96 ((~(CPU) & (FEAT)) == 0)
97
98#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 99 (((CPU) & (FEAT)) != 0)
100
93d8990c
SN		 101#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
102 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
103
a06ea964
NC		 104#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
105 do \
106 { \
107 (TARG) = (F1) | (F2); \
108 } \
109 while (0)
110
111#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
112 do \
113 { \
114 (TARG) = (F1) &~ (F2); \
115 } \
116 while (0)
117
118#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
119
a06ea964
NC		 120enum aarch64_operand_class
121{
122 AARCH64_OPND_CLASS_NIL,
123 AARCH64_OPND_CLASS_INT_REG,
124 AARCH64_OPND_CLASS_MODIFIED_REG,
125 AARCH64_OPND_CLASS_FP_REG,
126 AARCH64_OPND_CLASS_SIMD_REG,
127 AARCH64_OPND_CLASS_SIMD_ELEMENT,
128 AARCH64_OPND_CLASS_SISD_REG,
129 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 130 AARCH64_OPND_CLASS_SVE_REG,
131 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 132 AARCH64_OPND_CLASS_ADDRESS,
133 AARCH64_OPND_CLASS_IMMEDIATE,
134 AARCH64_OPND_CLASS_SYSTEM,
68a64283 135 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 136};
137
138/* Operand code that helps both parsing and coding.
139 Keep AARCH64_OPERANDS synced. */
140
141enum aarch64_opnd
142{
143 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
144
145 AARCH64_OPND_Rd, /* Integer register as destination. */
146 AARCH64_OPND_Rn, /* Integer register as source. */
147 AARCH64_OPND_Rm, /* Integer register as source. */
148 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
149 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
150 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
151 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
152 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
153
154 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
155 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 156 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 157 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 158 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
159 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
160
161 AARCH64_OPND_Fd, /* Floating-point Fd. */
162 AARCH64_OPND_Fn, /* Floating-point Fn. */
163 AARCH64_OPND_Fm, /* Floating-point Fm. */
164 AARCH64_OPND_Fa, /* Floating-point Fa. */
165 AARCH64_OPND_Ft, /* Floating-point Ft. */
166 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
167
168 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
169 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
170 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
171
f42f1a1d 172 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
a06ea964
NC		 173 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
174 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
175 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
176 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
177 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
178 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
179 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
180 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
369c9167
TC		 181 AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
182 qualifier is S_H. */
a06ea964
NC		 183 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
184 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
185 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
186 structure to all lanes. */
187 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
188
a6a51754
RL		 189 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
190 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 191
192 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
f42f1a1d 193 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
a06ea964
NC		 194 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
195 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
196 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
197 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
198 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
199 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
200 (no encoding). */
201 AARCH64_OPND_IMM0, /* Immediate for #0. */
202 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
203 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
204 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
205 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
206 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
207 AARCH64_OPND_IMM, /* Immediate. */
f42f1a1d 208 AARCH64_OPND_IMM_2, /* Immediate. */
a06ea964
NC		 209 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
210 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
211 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
212 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
213 AARCH64_OPND_BIT_NUM, /* Immediate. */
214 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
215 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 216 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 217 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
218 each condition flag. */
219
220 AARCH64_OPND_LIMM, /* Logical Immediate. */
221 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
222 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
223 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
224 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 225 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
226 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
227 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 228
229 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 230 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 231
232 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
233 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
234 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
235 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
236 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
237
238 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
239 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
240 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
241 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
242 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
243 negative or unaligned and there is
244 no writeback allowed. This operand code
245 is only used to support the programmer-
246 friendly feature of using LDR/STR as the
247 the mnemonic name for LDUR/STUR instructions
248 wherever there is no ambiguity. */
3f06e550 249 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
a06ea964
NC		 250 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
251 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
f42f1a1d 252 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
a06ea964
NC		 253 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
254
255 AARCH64_OPND_SYSREG, /* System register operand. */
256 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
257 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
258 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
259 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
260 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
261 AARCH64_OPND_BARRIER, /* Barrier operand. */
262 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
263 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 264 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
f11ad6bc 265
582e12bf 266 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
98907a70
RS		 267 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
268 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
269 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
270 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
271 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
272 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 273 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
274 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
275 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
276 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
c8d59609 277 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
4df068de
RS		 278 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
279 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
280 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
281 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
282 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
283 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
284 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
285 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
286 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
287 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
288 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
289 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
290 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
291 Bit 14 controls S/U choice. */
292 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
293 Bit 22 controls S/U choice. */
294 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
295 Bit 14 controls S/U choice. */
296 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
297 Bit 22 controls S/U choice. */
298 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
299 Bit 14 controls S/U choice. */
300 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
301 Bit 22 controls S/U choice. */
302 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
303 Bit 14 controls S/U choice. */
304 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
305 Bit 22 controls S/U choice. */
306 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
307 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
308 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
309 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
310 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
311 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
312 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 313 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
314 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 315 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
316 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
317 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
318 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS		 319 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
320 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
e950b345
RS		 321 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
322 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
323 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 324 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 325 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 326 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 327 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
328 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
329 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
330 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
331 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
332 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
333 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
334 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 335 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
336 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 337 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
338 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
339 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
340 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
341 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
342 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
343 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
344 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
345 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
346 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
347 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
348 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 349 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
350 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
351 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
352 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 353 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
354 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
355 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
356 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
357 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS		 358 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
359 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
360 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS		 361 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
362 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
363 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
364 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
365 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
f42f1a1d 366 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
a06ea964
NC		 367};
368
369/* Qualifier constrains an operand. It either specifies a variant of an
370 operand type or limits values available to an operand type.
371
372 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
373
374enum aarch64_opnd_qualifier
375{
376 /* Indicating no further qualification on an operand. */
377 AARCH64_OPND_QLF_NIL,
378
379 /* Qualifying an operand which is a general purpose (integer) register;
380 indicating the operand data size or a specific register. */
381 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
382 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
383 AARCH64_OPND_QLF_WSP, /* WSP. */
384 AARCH64_OPND_QLF_SP, /* SP. */
385
386 /* Qualifying an operand which is a floating-point register, a SIMD
387 vector element or a SIMD vector element list; indicating operand data
388 size or the size of each SIMD vector element in the case of a SIMD
389 vector element list.
390 These qualifiers are also used to qualify an address operand to
391 indicate the size of data element a load/store instruction is
392 accessing.
393 They are also used for the immediate shift operand in e.g. SSHR. Such
394 a use is only for the ease of operand encoding/decoding and qualifier
395 sequence matching; such a use should not be applied widely; use the value
396 constraint qualifiers for immediate operands wherever possible. */
397 AARCH64_OPND_QLF_S_B,
398 AARCH64_OPND_QLF_S_H,
399 AARCH64_OPND_QLF_S_S,
400 AARCH64_OPND_QLF_S_D,
401 AARCH64_OPND_QLF_S_Q,
00c2093f
TC		 402 /* This type qualifier has a special meaning in that it means that 4 x 1 byte
403 are selected by the instruction. Other than that it has no difference
404 with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical
405 reasons and is an exception from normal AArch64 disassembly scheme. */
406 AARCH64_OPND_QLF_S_4B,
a06ea964
NC		 407
408 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
409 register list; indicating register shape.
410 They are also used for the immediate shift operand in e.g. SSHR. Such
411 a use is only for the ease of operand encoding/decoding and qualifier
412 sequence matching; such a use should not be applied widely; use the value
413 constraint qualifiers for immediate operands wherever possible. */
a3b3345a 414 AARCH64_OPND_QLF_V_4B,
a06ea964
NC		 415 AARCH64_OPND_QLF_V_8B,
416 AARCH64_OPND_QLF_V_16B,
3067d3b9 417 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 418 AARCH64_OPND_QLF_V_4H,
419 AARCH64_OPND_QLF_V_8H,
420 AARCH64_OPND_QLF_V_2S,
421 AARCH64_OPND_QLF_V_4S,
422 AARCH64_OPND_QLF_V_1D,
423 AARCH64_OPND_QLF_V_2D,
424 AARCH64_OPND_QLF_V_1Q,
425
d50c751e
RS		 426 AARCH64_OPND_QLF_P_Z,
427 AARCH64_OPND_QLF_P_M,
428
a06ea964 429 /* Constraint on value. */
a6a51754 430 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 431 AARCH64_OPND_QLF_imm_0_7,
432 AARCH64_OPND_QLF_imm_0_15,
433 AARCH64_OPND_QLF_imm_0_31,
434 AARCH64_OPND_QLF_imm_0_63,
435 AARCH64_OPND_QLF_imm_1_32,
436 AARCH64_OPND_QLF_imm_1_64,
437
438 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
439 or shift-ones. */
440 AARCH64_OPND_QLF_LSL,
441 AARCH64_OPND_QLF_MSL,
442
443 /* Special qualifier helping retrieve qualifier information during the
444 decoding time (currently not in use). */
445 AARCH64_OPND_QLF_RETRIEVE,
446};
447\f
448/* Instruction class. */
449
450enum aarch64_insn_class
451{
452 addsub_carry,
453 addsub_ext,
454 addsub_imm,
455 addsub_shift,
456 asimdall,
457 asimddiff,
458 asimdelem,
459 asimdext,
460 asimdimm,
461 asimdins,
462 asimdmisc,
463 asimdperm,
464 asimdsame,
465 asimdshf,
466 asimdtbl,
467 asisddiff,
468 asisdelem,
469 asisdlse,
470 asisdlsep,
471 asisdlso,
472 asisdlsop,
473 asisdmisc,
474 asisdone,
475 asisdpair,
476 asisdsame,
477 asisdshf,
478 bitfield,
479 branch_imm,
480 branch_reg,
481 compbranch,
482 condbranch,
483 condcmp_imm,
484 condcmp_reg,
485 condsel,
486 cryptoaes,
487 cryptosha2,
488 cryptosha3,
489 dp_1src,
490 dp_2src,
491 dp_3src,
492 exception,
493 extract,
494 float2fix,
495 float2int,
496 floatccmp,
497 floatcmp,
498 floatdp1,
499 floatdp2,
500 floatdp3,
501 floatimm,
502 floatsel,
503 ldst_immpost,
504 ldst_immpre,
505 ldst_imm9, /* immpost or immpre */
3f06e550 506 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 507 ldst_pos,
508 ldst_regoff,
509 ldst_unpriv,
510 ldst_unscaled,
511 ldstexcl,
512 ldstnapair_offs,
513 ldstpair_off,
514 ldstpair_indexed,
515 loadlit,
516 log_imm,
517 log_shift,
ee804238 518 lse_atomic,
a06ea964
NC		 519 movewide,
520 pcreladdr,
521 ic_system,
116b6019
RS		 522 sve_cpy,
523 sve_index,
524 sve_limm,
525 sve_misc,
526 sve_movprfx,
527 sve_pred_zm,
528 sve_shift_pred,
529 sve_shift_unpred,
530 sve_size_bhs,
531 sve_size_bhsd,
532 sve_size_hsd,
533 sve_size_sd,
a06ea964 534 testbranch,
f42f1a1d
TC		 535 cryptosm3,
536 cryptosm4,
65a55fbb 537 dotproduct,
a06ea964
NC		 538};
539
540/* Opcode enumerators. */
541
542enum aarch64_op
543{
544 OP_NIL,
545 OP_STRB_POS,
546 OP_LDRB_POS,
547 OP_LDRSB_POS,
548 OP_STRH_POS,
549 OP_LDRH_POS,
550 OP_LDRSH_POS,
551 OP_STR_POS,
552 OP_LDR_POS,
553 OP_STRF_POS,
554 OP_LDRF_POS,
555 OP_LDRSW_POS,
556 OP_PRFM_POS,
557
558 OP_STURB,
559 OP_LDURB,
560 OP_LDURSB,
561 OP_STURH,
562 OP_LDURH,
563 OP_LDURSH,
564 OP_STUR,
565 OP_LDUR,
566 OP_STURV,
567 OP_LDURV,
568 OP_LDURSW,
569 OP_PRFUM,
570
571 OP_LDR_LIT,
572 OP_LDRV_LIT,
573 OP_LDRSW_LIT,
574 OP_PRFM_LIT,
575
576 OP_ADD,
577 OP_B,
578 OP_BL,
579
580 OP_MOVN,
581 OP_MOVZ,
582 OP_MOVK,
583
584 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
585 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
586 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
587
588 OP_MOV_V, /* MOV alias for moving vector register. */
589
590 OP_ASR_IMM,
591 OP_LSR_IMM,
592 OP_LSL_IMM,
593
594 OP_BIC,
595
596 OP_UBFX,
597 OP_BFXIL,
598 OP_SBFX,
599 OP_SBFIZ,
600 OP_BFI,
d685192a 601 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 602 OP_UBFIZ,
603 OP_UXTB,
604 OP_UXTH,
605 OP_UXTW,
606
a06ea964
NC		 607 OP_CINC,
608 OP_CINV,
609 OP_CNEG,
610 OP_CSET,
611 OP_CSETM,
612
613 OP_FCVT,
614 OP_FCVTN,
615 OP_FCVTN2,
616 OP_FCVTL,
617 OP_FCVTL2,
618 OP_FCVTXN_S, /* Scalar version. */
619
620 OP_ROR_IMM,
621
e30181a5
YZ		 622 OP_SXTL,
623 OP_SXTL2,
624 OP_UXTL,
625 OP_UXTL2,
626
c0890d26
RS		 627 OP_MOV_P_P,
628 OP_MOV_Z_P_Z,
629 OP_MOV_Z_V,
630 OP_MOV_Z_Z,
631 OP_MOV_Z_Zi,
632 OP_MOVM_P_P_P,
633 OP_MOVS_P_P,
634 OP_MOVZS_P_P_P,
635 OP_MOVZ_P_P_P,
636 OP_NOTS_P_P_P_Z,
637 OP_NOT_P_P_P_Z,
638
c2c4ff8d
SN		 639 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
640
a06ea964
NC		 641 OP_TOTAL_NUM, /* Pseudo. */
642};
643
1d482394
TC		 644/* Error types. */
645enum err_type
646{
647 ERR_OK,
648 ERR_UND,
649 ERR_UNP,
650 ERR_NYI,
651 ERR_NR_ENTRIES
652};
653
a06ea964
NC		 654/* Maximum number of operands an instruction can have. */
655#define AARCH64_MAX_OPND_NUM 6
656/* Maximum number of qualifier sequences an instruction can have. */
657#define AARCH64_MAX_QLF_SEQ_NUM 10
658/* Operand qualifier typedef; optimized for the size. */
659typedef unsigned char aarch64_opnd_qualifier_t;
660/* Operand qualifier sequence typedef. */
661typedef aarch64_opnd_qualifier_t \
662 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
663
664/* FIXME: improve the efficiency. */
665static inline bfd_boolean
666empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
667{
668 int i;
669 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
670 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
671 return FALSE;
672 return TRUE;
673}
674
7e84b55d
TC		 675/* Forward declare error reporting type. */
676typedef struct aarch64_operand_error aarch64_operand_error;
677/* Forward declare instruction sequence type. */
678typedef struct aarch64_instr_sequence aarch64_instr_sequence;
679/* Forward declare instruction definition. */
680typedef struct aarch64_inst aarch64_inst;
681
a06ea964
NC		 682/* This structure holds information for a particular opcode. */
683
684struct aarch64_opcode
685{
686 /* The name of the mnemonic. */
687 const char *name;
688
689 /* The opcode itself. Those bits which will be filled in with
690 operands are zeroes. */
691 aarch64_insn opcode;
692
693 /* The opcode mask. This is used by the disassembler. This is a
694 mask containing ones indicating those bits which must match the
695 opcode field, and zeroes indicating those bits which need not
696 match (and are presumably filled in by operands). */
697 aarch64_insn mask;
698
699 /* Instruction class. */
700 enum aarch64_insn_class iclass;
701
702 /* Enumerator identifier. */
703 enum aarch64_op op;
704
705 /* Which architecture variant provides this instruction. */
706 const aarch64_feature_set *avariant;
707
708 /* An array of operand codes. Each code is an index into the
709 operand table. They appear in the order which the operands must
710 appear in assembly code, and are terminated by a zero. */
711 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
712
713 /* A list of operand qualifier code sequence. Each operand qualifier
714 code qualifies the corresponding operand code. Each operand
715 qualifier sequence specifies a valid opcode variant and related
716 constraint on operands. */
717 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
718
719 /* Flags providing information about this instruction */
eae424ae
TC		 720 uint64_t flags;
721
722 /* Extra constraints on the instruction that the verifier checks. */
723 uint32_t constraints;
4bd13cde 724
0c608d6b
RS		 725 /* If nonzero, this operand and operand 0 are both registers and
726 are required to have the same register number. */
727 unsigned char tied_operand;
728
4bd13cde
NC		 729 /* If non-NULL, a function to verify that a given instruction is valid. */
730 bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
a06ea964
NC		 731};
732
733typedef struct aarch64_opcode aarch64_opcode;
734
735/* Table describing all the AArch64 opcodes. */
736extern aarch64_opcode aarch64_opcode_table[];
737
738/* Opcode flags. */
739#define F_ALIAS (1 << 0)
740#define F_HAS_ALIAS (1 << 1)
741/* Disassembly preference priority 1-3 (the larger the higher). If nothing
742 is specified, it is the priority 0 by default, i.e. the lowest priority. */
743#define F_P1 (1 << 2)
744#define F_P2 (2 << 2)
745#define F_P3 (3 << 2)
746/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
747#define F_COND (1 << 4)
748/* Instruction has the field of 'sf'. */
749#define F_SF (1 << 5)
750/* Instruction has the field of 'size:Q'. */
751#define F_SIZEQ (1 << 6)
752/* Floating-point instruction has the field of 'type'. */
753#define F_FPTYPE (1 << 7)
754/* AdvSIMD scalar instruction has the field of 'size'. */
755#define F_SSIZE (1 << 8)
756/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
757#define F_T (1 << 9)
758/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
759#define F_GPRSIZE_IN_Q (1 << 10)
760/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
761#define F_LDS_SIZE (1 << 11)
762/* Optional operand; assume maximum of 1 operand can be optional. */
763#define F_OPD0_OPT (1 << 12)
764#define F_OPD1_OPT (2 << 12)
765#define F_OPD2_OPT (3 << 12)
766#define F_OPD3_OPT (4 << 12)
767#define F_OPD4_OPT (5 << 12)
768/* Default value for the optional operand when omitted from the assembly. */
769#define F_DEFAULT(X) (((X) & 0x1f) << 15)
770/* Instruction that is an alias of another instruction needs to be
771 encoded/decoded by converting it to/from the real form, followed by
772 the encoding/decoding according to the rules of the real opcode.
773 This compares to the direct coding using the alias's information.
774 N.B. this flag requires F_ALIAS to be used together. */
775#define F_CONV (1 << 20)
776/* Use together with F_ALIAS to indicate an alias opcode is a programmer
777 friendly pseudo instruction available only in the assembly code (thus will
778 not show up in the disassembly). */
779#define F_PSEUDO (1 << 21)
780/* Instruction has miscellaneous encoding/decoding rules. */
781#define F_MISC (1 << 22)
782/* Instruction has the field of 'N'; used in conjunction with F_SF. */
783#define F_N (1 << 23)
784/* Opcode dependent field. */
785#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 786/* Instruction has the field of 'sz'. */
787#define F_LSE_SZ (1 << 27)
4989adac
RS		 788/* Require an exact qualifier match, even for NIL qualifiers. */
789#define F_STRICT (1ULL << 28)
f9830ec1
TC		 790/* This system instruction is used to read system registers. */
791#define F_SYS_READ (1ULL << 29)
792/* This system instruction is used to write system registers. */
793#define F_SYS_WRITE (1ULL << 30)
eae424ae
TC		 794/* This instruction has an extra constraint on it that imposes a requirement on
795 subsequent instructions. */
796#define F_SCAN (1ULL << 31)
797/* Next bit is 32. */
798
799/* Instruction constraints. */
800/* This instruction has a predication constraint on the instruction at PC+4. */
801#define C_SCAN_MOVPRFX (1U << 0)
802/* This instruction's operation width is determined by the operand with the
803 largest element size. */
804#define C_MAX_ELEM (1U << 1)
805/* Next bit is 2. */
a06ea964
NC		 806
807static inline bfd_boolean
808alias_opcode_p (const aarch64_opcode *opcode)
809{
810 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
811}
812
813static inline bfd_boolean
814opcode_has_alias (const aarch64_opcode *opcode)
815{
816 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
817}
818
819/* Priority for disassembling preference. */
820static inline int
821opcode_priority (const aarch64_opcode *opcode)
822{
823 return (opcode->flags >> 2) & 0x3;
824}
825
826static inline bfd_boolean
827pseudo_opcode_p (const aarch64_opcode *opcode)
828{
829 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
830}
831
832static inline bfd_boolean
833optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
834{
835 return (((opcode->flags >> 12) & 0x7) == idx + 1)
836 ? TRUE : FALSE;
837}
838
839static inline aarch64_insn
840get_optional_operand_default_value (const aarch64_opcode *opcode)
841{
842 return (opcode->flags >> 15) & 0x1f;
843}
844
845static inline unsigned int
846get_opcode_dependent_value (const aarch64_opcode *opcode)
847{
848 return (opcode->flags >> 24) & 0x7;
849}
850
851static inline bfd_boolean
852opcode_has_special_coder (const aarch64_opcode *opcode)
853{
ee804238 854 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 855 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
856 : FALSE;
857}
858\f
859struct aarch64_name_value_pair
860{
861 const char * name;
862 aarch64_insn value;
863};
864
865extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 866extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
867extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 868extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 869
49eec193
YZ		 870typedef struct
871{
872 const char * name;
873 aarch64_insn value;
874 uint32_t flags;
875} aarch64_sys_reg;
876
877extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 878extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 879extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 880extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
881 const aarch64_sys_reg *);
882extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
883 const aarch64_sys_reg *);
49eec193 884
a06ea964
NC		 885typedef struct
886{
875880c6 887 const char *name;
a06ea964 888 uint32_t value;
ea2deeec 889 uint32_t flags ;
a06ea964
NC		 890} aarch64_sys_ins_reg;
891
ea2deeec 892extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 893extern bfd_boolean
894aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
895 const aarch64_sys_ins_reg *);
ea2deeec 896
a06ea964
NC		 897extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
898extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
899extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
900extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
901
902/* Shift/extending operator kinds.
903 N.B. order is important; keep aarch64_operand_modifiers synced. */
904enum aarch64_modifier_kind
905{
906 AARCH64_MOD_NONE,
907 AARCH64_MOD_MSL,
908 AARCH64_MOD_ROR,
909 AARCH64_MOD_ASR,
910 AARCH64_MOD_LSR,
911 AARCH64_MOD_LSL,
912 AARCH64_MOD_UXTB,
913 AARCH64_MOD_UXTH,
914 AARCH64_MOD_UXTW,
915 AARCH64_MOD_UXTX,
916 AARCH64_MOD_SXTB,
917 AARCH64_MOD_SXTH,
918 AARCH64_MOD_SXTW,
919 AARCH64_MOD_SXTX,
2442d846 920 AARCH64_MOD_MUL,
98907a70 921 AARCH64_MOD_MUL_VL,
a06ea964
NC		 922};
923
924bfd_boolean
925aarch64_extend_operator_p (enum aarch64_modifier_kind);
926
927enum aarch64_modifier_kind
928aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
929/* Condition. */
930
931typedef struct
932{
933 /* A list of names with the first one as the disassembly preference;
934 terminated by NULL if fewer than 3. */
bb7eff52 935 const char *names[4];
a06ea964
NC		 936 aarch64_insn value;
937} aarch64_cond;
938
939extern const aarch64_cond aarch64_conds[16];
940
941const aarch64_cond* get_cond_from_value (aarch64_insn value);
942const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
943\f
944/* Structure representing an operand. */
945
946struct aarch64_opnd_info
947{
948 enum aarch64_opnd type;
949 aarch64_opnd_qualifier_t qualifier;
950 int idx;
951
952 union
953 {
954 struct
955 {
956 unsigned regno;
957 } reg;
958 struct
959 {
dab26bf4
RS		 960 unsigned int regno;
961 int64_t index;
a06ea964
NC		 962 } reglane;
963 /* e.g. LVn. */
964 struct
965 {
966 unsigned first_regno : 5;
967 unsigned num_regs : 3;
968 /* 1 if it is a list of reg element. */
969 unsigned has_index : 1;
970 /* Lane index; valid only when has_index is 1. */
dab26bf4 971 int64_t index;
a06ea964
NC		 972 } reglist;
973 /* e.g. immediate or pc relative address offset. */
974 struct
975 {
976 int64_t value;
977 unsigned is_fp : 1;
978 } imm;
979 /* e.g. address in STR (register offset). */
980 struct
981 {
982 unsigned base_regno;
983 struct
984 {
985 union
986 {
987 int imm;
988 unsigned regno;
989 };
990 unsigned is_reg;
991 } offset;
992 unsigned pcrel : 1; /* PC-relative. */
993 unsigned writeback : 1;
994 unsigned preind : 1; /* Pre-indexed. */
995 unsigned postind : 1; /* Post-indexed. */
996 } addr;
561a72d4
TC		 997
998 struct
999 {
1000 /* The encoding of the system register. */
1001 aarch64_insn value;
1002
1003 /* The system register flags. */
1004 uint32_t flags;
1005 } sysreg;
1006
a06ea964 1007 const aarch64_cond *cond;
a06ea964
NC		 1008 /* The encoding of the PSTATE field. */
1009 aarch64_insn pstatefield;
1010 const aarch64_sys_ins_reg *sysins_op;
1011 const struct aarch64_name_value_pair *barrier;
9ed608f9 1012 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 1013 const struct aarch64_name_value_pair *prfop;
1014 };
1015
1016 /* Operand shifter; in use when the operand is a register offset address,
1017 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
1018 struct
1019 {
1020 enum aarch64_modifier_kind kind;
a06ea964
NC		 1021 unsigned operator_present: 1; /* Only valid during encoding. */
1022 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1023 unsigned amount_present: 1;
2442d846 1024 int64_t amount;
a06ea964
NC		 1025 } shifter;
1026
1027 unsigned skip:1; /* Operand is not completed if there is a fixup needed
1028 to be done on it. In some (but not all) of these
1029 cases, we need to tell libopcodes to skip the
1030 constraint checking and the encoding for this
1031 operand, so that the libopcodes can pick up the
1032 right opcode before the operand is fixed-up. This
1033 flag should only be used during the
1034 assembling/encoding. */
1035 unsigned present:1; /* Whether this operand is present in the assembly
1036 line; not used during the disassembly. */
1037};
1038
1039typedef struct aarch64_opnd_info aarch64_opnd_info;
1040
1041/* Structure representing an instruction.
1042
1043 It is used during both the assembling and disassembling. The assembler
1044 fills an aarch64_inst after a successful parsing and then passes it to the
1045 encoding routine to do the encoding. During the disassembling, the
1046 disassembler calls the decoding routine to decode a binary instruction; on a
1047 successful return, such a structure will be filled with information of the
1048 instruction; then the disassembler uses the information to print out the
1049 instruction. */
1050
1051struct aarch64_inst
1052{
1053 /* The value of the binary instruction. */
1054 aarch64_insn value;
1055
1056 /* Corresponding opcode entry. */
1057 const aarch64_opcode *opcode;
1058
1059 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1060 const aarch64_cond *cond;
1061
1062 /* Operands information. */
1063 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1064};
1065
1066typedef struct aarch64_inst aarch64_inst;
1067\f
1068/* Diagnosis related declaration and interface. */
1069
1070/* Operand error kind enumerators.
1071
1072 AARCH64_OPDE_RECOVERABLE
1073 Less severe error found during the parsing, very possibly because that
1074 GAS has picked up a wrong instruction template for the parsing.
1075
1076 AARCH64_OPDE_SYNTAX_ERROR
1077 General syntax error; it can be either a user error, or simply because
1078 that GAS is trying a wrong instruction template.
1079
1080 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1081 Definitely a user syntax error.
1082
1083 AARCH64_OPDE_INVALID_VARIANT
1084 No syntax error, but the operands are not a valid combination, e.g.
1085 FMOV D0,S0
1086
0c608d6b
RS		 1087 AARCH64_OPDE_UNTIED_OPERAND
1088 The asm failed to use the same register for a destination operand
1089 and a tied source operand.
1090
a06ea964
NC		 1091 AARCH64_OPDE_OUT_OF_RANGE
1092 Error about some immediate value out of a valid range.
1093
1094 AARCH64_OPDE_UNALIGNED
1095 Error about some immediate value not properly aligned (i.e. not being a
1096 multiple times of a certain value).
1097
1098 AARCH64_OPDE_REG_LIST
1099 Error about the register list operand having unexpected number of
1100 registers.
1101
1102 AARCH64_OPDE_OTHER_ERROR
1103 Error of the highest severity and used for any severe issue that does not
1104 fall into any of the above categories.
1105
1106 The enumerators are only interesting to GAS. They are declared here (in
1107 libopcodes) because that some errors are detected (and then notified to GAS)
1108 by libopcodes (rather than by GAS solely).
1109
1110 The first three errors are only deteced by GAS while the
1111 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1112 only libopcodes has the information about the valid variants of each
1113 instruction.
1114
1115 The enumerators have an increasing severity. This is helpful when there are
1116 multiple instruction templates available for a given mnemonic name (e.g.
1117 FMOV); this mechanism will help choose the most suitable template from which
1118 the generated diagnostics can most closely describe the issues, if any. */
1119
1120enum aarch64_operand_error_kind
1121{
1122 AARCH64_OPDE_NIL,
1123 AARCH64_OPDE_RECOVERABLE,
1124 AARCH64_OPDE_SYNTAX_ERROR,
1125 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1126 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1127 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1128 AARCH64_OPDE_OUT_OF_RANGE,
1129 AARCH64_OPDE_UNALIGNED,
1130 AARCH64_OPDE_REG_LIST,
1131 AARCH64_OPDE_OTHER_ERROR
1132};
1133
1134/* N.B. GAS assumes that this structure work well with shallow copy. */
1135struct aarch64_operand_error
1136{
1137 enum aarch64_operand_error_kind kind;
1138 int index;
1139 const char *error;
1140 int data[3]; /* Some data for extra information. */
7d02540a 1141 bfd_boolean non_fatal;
a06ea964
NC		 1142};
1143
7e84b55d
TC		 1144/* AArch64 sequence structure used to track instructions with F_SCAN
1145 dependencies for both assembler and disassembler. */
1146struct aarch64_instr_sequence
1147{
1148 /* The instruction that caused this sequence to be opened. */
1149 aarch64_inst *instr;
1150 /* The number of instructions the above instruction allows to be kept in the
1151 sequence before an automatic close is done. */
1152 int num_insns;
1153 /* The instructions currently added to the sequence. */
1154 aarch64_inst **current_insns;
1155 /* The number of instructions already in the sequence. */
1156 int next_insn;
1157};
a06ea964
NC		 1158
1159/* Encoding entrypoint. */
1160
1161extern int
1162aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1163 aarch64_insn *, aarch64_opnd_qualifier_t *,
7e84b55d 1164 aarch64_operand_error *, aarch64_instr_sequence *);
a06ea964
NC		 1165
1166extern const aarch64_opcode *
1167aarch64_replace_opcode (struct aarch64_inst *,
1168 const aarch64_opcode *);
1169
1170/* Given the opcode enumerator OP, return the pointer to the corresponding
1171 opcode entry. */
1172
1173extern const aarch64_opcode *
1174aarch64_get_opcode (enum aarch64_op);
1175
1176/* Generate the string representation of an operand. */
1177extern void
1178aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
7d02540a
TC		 1179 const aarch64_opnd_info *, int, int *, bfd_vma *,
1180 char **);
a06ea964
NC		 1181
1182/* Miscellaneous interface. */
1183
1184extern int
1185aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1186
1187extern aarch64_opnd_qualifier_t
1188aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1189 const aarch64_opnd_qualifier_t, int);
1190
1191extern int
1192aarch64_num_of_operands (const aarch64_opcode *);
1193
1194extern int
1195aarch64_stack_pointer_p (const aarch64_opnd_info *);
1196
e141d84e
YQ		 1197extern int
1198aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1199
1d482394 1200extern enum err_type
561a72d4
TC		 1201aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
1202 aarch64_operand_error *errors);
36f4aab1 1203
a06ea964
NC		 1204/* Given an operand qualifier, return the expected data element size
1205 of a qualified operand. */
1206extern unsigned char
1207aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1208
1209extern enum aarch64_operand_class
1210aarch64_get_operand_class (enum aarch64_opnd);
1211
1212extern const char *
1213aarch64_get_operand_name (enum aarch64_opnd);
1214
1215extern const char *
1216aarch64_get_operand_desc (enum aarch64_opnd);
1217
e950b345
RS		 1218extern bfd_boolean
1219aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1220
a06ea964
NC		 1221#ifdef DEBUG_AARCH64
1222extern int debug_dump;
1223
1224extern void
1225aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1226
1227#define DEBUG_TRACE(M, ...) \
1228 { \
1229 if (debug_dump) \
1230 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1231 }
1232
1233#define DEBUG_TRACE_IF(C, M, ...) \
1234 { \
1235 if (debug_dump && (C)) \
1236 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1237 }
1238#else /* !DEBUG_AARCH64 */
1239#define DEBUG_TRACE(M, ...) ;
1240#define DEBUG_TRACE_IF(C, M, ...) ;
1241#endif /* DEBUG_AARCH64 */
1242
245d2e3f
RS		 1243extern const char *const aarch64_sve_pattern_array[32];
1244extern const char *const aarch64_sve_prfop_array[16];
1245
d3e12b29
YQ		 1246#ifdef __cplusplus
1247}
1248#endif
1249
a06ea964 1250#endif /* OPCODE_AARCH64_H */
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