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a06ea964 NC |
1 | /* AArch64 assembler/disassembler support. |
2 | ||
6f2750fe | 3 | Copyright (C) 2009-2016 Free Software Foundation, Inc. |
a06ea964 NC |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GNU Binutils. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the license, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; see the file COPYING3. If not, | |
20 | see <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #ifndef OPCODE_AARCH64_H | |
23 | #define OPCODE_AARCH64_H | |
24 | ||
25 | #include "bfd.h" | |
26 | #include "bfd_stdint.h" | |
27 | #include <assert.h> | |
28 | #include <stdlib.h> | |
29 | ||
d3e12b29 YQ |
30 | #ifdef __cplusplus |
31 | extern "C" { | |
32 | #endif | |
33 | ||
a06ea964 NC |
34 | /* The offset for pc-relative addressing is currently defined to be 0. */ |
35 | #define AARCH64_PCREL_OFFSET 0 | |
36 | ||
37 | typedef uint32_t aarch64_insn; | |
38 | ||
39 | /* The following bitmasks control CPU features. */ | |
40 | #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ | |
acb787b0 | 41 | #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */ |
a06ea964 NC |
42 | #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ |
43 | #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ | |
44 | #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ | |
e60bb1dd | 45 | #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ |
ee804238 | 46 | #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */ |
f21cce2c | 47 | #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */ |
290806fd | 48 | #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */ |
9e1f0fa7 | 49 | #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */ |
250aafa4 | 50 | #define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */ |
af117b3c | 51 | #define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */ |
c8a6db6f | 52 | #define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */ |
73af8ed6 | 53 | #define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */ |
a06ea964 NC |
54 | |
55 | /* Architectures are the sum of the base and extensions. */ | |
56 | #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ | |
57 | AARCH64_FEATURE_FP \ | |
58 | | AARCH64_FEATURE_SIMD) | |
88f0ea34 MW |
59 | #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ |
60 | AARCH64_FEATURE_FP \ | |
61 | | AARCH64_FEATURE_SIMD \ | |
af117b3c | 62 | | AARCH64_FEATURE_CRC \ |
250aafa4 | 63 | | AARCH64_FEATURE_V8_1 \ |
88f0ea34 MW |
64 | | AARCH64_FEATURE_LSE \ |
65 | | AARCH64_FEATURE_PAN \ | |
66 | | AARCH64_FEATURE_LOR \ | |
67 | | AARCH64_FEATURE_RDMA) | |
acb787b0 MW |
68 | #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ |
69 | AARCH64_FEATURE_V8_2 \ | |
87018195 | 70 | | AARCH64_FEATURE_F16 \ |
c8a6db6f | 71 | | AARCH64_FEATURE_RAS \ |
acb787b0 | 72 | | AARCH64_FEATURE_FP \ |
af117b3c MW |
73 | | AARCH64_FEATURE_SIMD \ |
74 | | AARCH64_FEATURE_CRC \ | |
75 | | AARCH64_FEATURE_V8_1 \ | |
acb787b0 MW |
76 | | AARCH64_FEATURE_LSE \ |
77 | | AARCH64_FEATURE_PAN \ | |
78 | | AARCH64_FEATURE_LOR \ | |
79 | | AARCH64_FEATURE_RDMA) | |
88f0ea34 | 80 | |
a06ea964 NC |
81 | #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) |
82 | #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ | |
83 | ||
84 | /* CPU-specific features. */ | |
85 | typedef unsigned long aarch64_feature_set; | |
86 | ||
93d8990c SN |
87 | #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \ |
88 | ((~(CPU) & (FEAT)) == 0) | |
89 | ||
90 | #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \ | |
a06ea964 NC |
91 | (((CPU) & (FEAT)) != 0) |
92 | ||
93d8990c SN |
93 | #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ |
94 | AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT) | |
95 | ||
a06ea964 NC |
96 | #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ |
97 | do \ | |
98 | { \ | |
99 | (TARG) = (F1) | (F2); \ | |
100 | } \ | |
101 | while (0) | |
102 | ||
103 | #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ | |
104 | do \ | |
105 | { \ | |
106 | (TARG) = (F1) &~ (F2); \ | |
107 | } \ | |
108 | while (0) | |
109 | ||
110 | #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) | |
111 | ||
a06ea964 NC |
112 | enum aarch64_operand_class |
113 | { | |
114 | AARCH64_OPND_CLASS_NIL, | |
115 | AARCH64_OPND_CLASS_INT_REG, | |
116 | AARCH64_OPND_CLASS_MODIFIED_REG, | |
117 | AARCH64_OPND_CLASS_FP_REG, | |
118 | AARCH64_OPND_CLASS_SIMD_REG, | |
119 | AARCH64_OPND_CLASS_SIMD_ELEMENT, | |
120 | AARCH64_OPND_CLASS_SISD_REG, | |
121 | AARCH64_OPND_CLASS_SIMD_REGLIST, | |
122 | AARCH64_OPND_CLASS_CP_REG, | |
f11ad6bc RS |
123 | AARCH64_OPND_CLASS_SVE_REG, |
124 | AARCH64_OPND_CLASS_PRED_REG, | |
a06ea964 NC |
125 | AARCH64_OPND_CLASS_ADDRESS, |
126 | AARCH64_OPND_CLASS_IMMEDIATE, | |
127 | AARCH64_OPND_CLASS_SYSTEM, | |
68a64283 | 128 | AARCH64_OPND_CLASS_COND, |
a06ea964 NC |
129 | }; |
130 | ||
131 | /* Operand code that helps both parsing and coding. | |
132 | Keep AARCH64_OPERANDS synced. */ | |
133 | ||
134 | enum aarch64_opnd | |
135 | { | |
136 | AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ | |
137 | ||
138 | AARCH64_OPND_Rd, /* Integer register as destination. */ | |
139 | AARCH64_OPND_Rn, /* Integer register as source. */ | |
140 | AARCH64_OPND_Rm, /* Integer register as source. */ | |
141 | AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ | |
142 | AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ | |
143 | AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ | |
144 | AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ | |
145 | AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ | |
146 | ||
147 | AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ | |
148 | AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ | |
ee804238 | 149 | AARCH64_OPND_PAIRREG, /* Paired register operand. */ |
a06ea964 NC |
150 | AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ |
151 | AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ | |
152 | ||
153 | AARCH64_OPND_Fd, /* Floating-point Fd. */ | |
154 | AARCH64_OPND_Fn, /* Floating-point Fn. */ | |
155 | AARCH64_OPND_Fm, /* Floating-point Fm. */ | |
156 | AARCH64_OPND_Fa, /* Floating-point Fa. */ | |
157 | AARCH64_OPND_Ft, /* Floating-point Ft. */ | |
158 | AARCH64_OPND_Ft2, /* Floating-point Ft2. */ | |
159 | ||
160 | AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ | |
161 | AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ | |
162 | AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ | |
163 | ||
164 | AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ | |
165 | AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ | |
166 | AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ | |
167 | AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ | |
168 | AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ | |
169 | AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ | |
170 | AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ | |
171 | AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ | |
172 | AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ | |
173 | AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ | |
174 | AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single | |
175 | structure to all lanes. */ | |
176 | AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ | |
177 | ||
178 | AARCH64_OPND_Cn, /* Co-processor register in CRn field. */ | |
179 | AARCH64_OPND_Cm, /* Co-processor register in CRm field. */ | |
180 | ||
181 | AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ | |
182 | AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ | |
183 | AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ | |
184 | AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ | |
185 | AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ | |
186 | AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ | |
187 | AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction | |
188 | (no encoding). */ | |
189 | AARCH64_OPND_IMM0, /* Immediate for #0. */ | |
190 | AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ | |
191 | AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ | |
192 | AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ | |
193 | AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ | |
194 | AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ | |
195 | AARCH64_OPND_IMM, /* Immediate. */ | |
196 | AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ | |
197 | AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ | |
198 | AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ | |
199 | AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ | |
200 | AARCH64_OPND_BIT_NUM, /* Immediate. */ | |
201 | AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ | |
202 | AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ | |
203 | AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for | |
204 | each condition flag. */ | |
205 | ||
206 | AARCH64_OPND_LIMM, /* Logical Immediate. */ | |
207 | AARCH64_OPND_AIMM, /* Arithmetic immediate. */ | |
208 | AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ | |
209 | AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ | |
210 | AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ | |
211 | ||
212 | AARCH64_OPND_COND, /* Standard condition as the last operand. */ | |
68a64283 | 213 | AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ |
a06ea964 NC |
214 | |
215 | AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ | |
216 | AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ | |
217 | AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ | |
218 | AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ | |
219 | AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ | |
220 | ||
221 | AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ | |
222 | AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ | |
223 | AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ | |
224 | AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ | |
225 | AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is | |
226 | negative or unaligned and there is | |
227 | no writeback allowed. This operand code | |
228 | is only used to support the programmer- | |
229 | friendly feature of using LDR/STR as the | |
230 | the mnemonic name for LDUR/STUR instructions | |
231 | wherever there is no ambiguity. */ | |
232 | AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ | |
233 | AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ | |
234 | AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ | |
235 | ||
236 | AARCH64_OPND_SYSREG, /* System register operand. */ | |
237 | AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ | |
238 | AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ | |
239 | AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ | |
240 | AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ | |
241 | AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ | |
242 | AARCH64_OPND_BARRIER, /* Barrier operand. */ | |
243 | AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ | |
244 | AARCH64_OPND_PRFOP, /* Prefetch operation. */ | |
1e6f4800 | 245 | AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ |
f11ad6bc | 246 | |
245d2e3f | 247 | AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */ |
2442d846 | 248 | AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */ |
245d2e3f | 249 | AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */ |
f11ad6bc RS |
250 | AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */ |
251 | AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */ | |
252 | AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */ | |
253 | AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */ | |
254 | AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */ | |
255 | AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */ | |
256 | AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */ | |
257 | AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */ | |
258 | AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */ | |
259 | AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */ | |
260 | AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */ | |
261 | AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */ | |
262 | AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */ | |
263 | AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ | |
264 | AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ | |
265 | AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ | |
266 | AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ | |
267 | AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ | |
a06ea964 NC |
268 | }; |
269 | ||
270 | /* Qualifier constrains an operand. It either specifies a variant of an | |
271 | operand type or limits values available to an operand type. | |
272 | ||
273 | N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ | |
274 | ||
275 | enum aarch64_opnd_qualifier | |
276 | { | |
277 | /* Indicating no further qualification on an operand. */ | |
278 | AARCH64_OPND_QLF_NIL, | |
279 | ||
280 | /* Qualifying an operand which is a general purpose (integer) register; | |
281 | indicating the operand data size or a specific register. */ | |
282 | AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ | |
283 | AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ | |
284 | AARCH64_OPND_QLF_WSP, /* WSP. */ | |
285 | AARCH64_OPND_QLF_SP, /* SP. */ | |
286 | ||
287 | /* Qualifying an operand which is a floating-point register, a SIMD | |
288 | vector element or a SIMD vector element list; indicating operand data | |
289 | size or the size of each SIMD vector element in the case of a SIMD | |
290 | vector element list. | |
291 | These qualifiers are also used to qualify an address operand to | |
292 | indicate the size of data element a load/store instruction is | |
293 | accessing. | |
294 | They are also used for the immediate shift operand in e.g. SSHR. Such | |
295 | a use is only for the ease of operand encoding/decoding and qualifier | |
296 | sequence matching; such a use should not be applied widely; use the value | |
297 | constraint qualifiers for immediate operands wherever possible. */ | |
298 | AARCH64_OPND_QLF_S_B, | |
299 | AARCH64_OPND_QLF_S_H, | |
300 | AARCH64_OPND_QLF_S_S, | |
301 | AARCH64_OPND_QLF_S_D, | |
302 | AARCH64_OPND_QLF_S_Q, | |
303 | ||
304 | /* Qualifying an operand which is a SIMD vector register or a SIMD vector | |
305 | register list; indicating register shape. | |
306 | They are also used for the immediate shift operand in e.g. SSHR. Such | |
307 | a use is only for the ease of operand encoding/decoding and qualifier | |
308 | sequence matching; such a use should not be applied widely; use the value | |
309 | constraint qualifiers for immediate operands wherever possible. */ | |
310 | AARCH64_OPND_QLF_V_8B, | |
311 | AARCH64_OPND_QLF_V_16B, | |
3067d3b9 | 312 | AARCH64_OPND_QLF_V_2H, |
a06ea964 NC |
313 | AARCH64_OPND_QLF_V_4H, |
314 | AARCH64_OPND_QLF_V_8H, | |
315 | AARCH64_OPND_QLF_V_2S, | |
316 | AARCH64_OPND_QLF_V_4S, | |
317 | AARCH64_OPND_QLF_V_1D, | |
318 | AARCH64_OPND_QLF_V_2D, | |
319 | AARCH64_OPND_QLF_V_1Q, | |
320 | ||
d50c751e RS |
321 | AARCH64_OPND_QLF_P_Z, |
322 | AARCH64_OPND_QLF_P_M, | |
323 | ||
a06ea964 NC |
324 | /* Constraint on value. */ |
325 | AARCH64_OPND_QLF_imm_0_7, | |
326 | AARCH64_OPND_QLF_imm_0_15, | |
327 | AARCH64_OPND_QLF_imm_0_31, | |
328 | AARCH64_OPND_QLF_imm_0_63, | |
329 | AARCH64_OPND_QLF_imm_1_32, | |
330 | AARCH64_OPND_QLF_imm_1_64, | |
331 | ||
332 | /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros | |
333 | or shift-ones. */ | |
334 | AARCH64_OPND_QLF_LSL, | |
335 | AARCH64_OPND_QLF_MSL, | |
336 | ||
337 | /* Special qualifier helping retrieve qualifier information during the | |
338 | decoding time (currently not in use). */ | |
339 | AARCH64_OPND_QLF_RETRIEVE, | |
340 | }; | |
341 | \f | |
342 | /* Instruction class. */ | |
343 | ||
344 | enum aarch64_insn_class | |
345 | { | |
346 | addsub_carry, | |
347 | addsub_ext, | |
348 | addsub_imm, | |
349 | addsub_shift, | |
350 | asimdall, | |
351 | asimddiff, | |
352 | asimdelem, | |
353 | asimdext, | |
354 | asimdimm, | |
355 | asimdins, | |
356 | asimdmisc, | |
357 | asimdperm, | |
358 | asimdsame, | |
359 | asimdshf, | |
360 | asimdtbl, | |
361 | asisddiff, | |
362 | asisdelem, | |
363 | asisdlse, | |
364 | asisdlsep, | |
365 | asisdlso, | |
366 | asisdlsop, | |
367 | asisdmisc, | |
368 | asisdone, | |
369 | asisdpair, | |
370 | asisdsame, | |
371 | asisdshf, | |
372 | bitfield, | |
373 | branch_imm, | |
374 | branch_reg, | |
375 | compbranch, | |
376 | condbranch, | |
377 | condcmp_imm, | |
378 | condcmp_reg, | |
379 | condsel, | |
380 | cryptoaes, | |
381 | cryptosha2, | |
382 | cryptosha3, | |
383 | dp_1src, | |
384 | dp_2src, | |
385 | dp_3src, | |
386 | exception, | |
387 | extract, | |
388 | float2fix, | |
389 | float2int, | |
390 | floatccmp, | |
391 | floatcmp, | |
392 | floatdp1, | |
393 | floatdp2, | |
394 | floatdp3, | |
395 | floatimm, | |
396 | floatsel, | |
397 | ldst_immpost, | |
398 | ldst_immpre, | |
399 | ldst_imm9, /* immpost or immpre */ | |
400 | ldst_pos, | |
401 | ldst_regoff, | |
402 | ldst_unpriv, | |
403 | ldst_unscaled, | |
404 | ldstexcl, | |
405 | ldstnapair_offs, | |
406 | ldstpair_off, | |
407 | ldstpair_indexed, | |
408 | loadlit, | |
409 | log_imm, | |
410 | log_shift, | |
ee804238 | 411 | lse_atomic, |
a06ea964 NC |
412 | movewide, |
413 | pcreladdr, | |
414 | ic_system, | |
415 | testbranch, | |
416 | }; | |
417 | ||
418 | /* Opcode enumerators. */ | |
419 | ||
420 | enum aarch64_op | |
421 | { | |
422 | OP_NIL, | |
423 | OP_STRB_POS, | |
424 | OP_LDRB_POS, | |
425 | OP_LDRSB_POS, | |
426 | OP_STRH_POS, | |
427 | OP_LDRH_POS, | |
428 | OP_LDRSH_POS, | |
429 | OP_STR_POS, | |
430 | OP_LDR_POS, | |
431 | OP_STRF_POS, | |
432 | OP_LDRF_POS, | |
433 | OP_LDRSW_POS, | |
434 | OP_PRFM_POS, | |
435 | ||
436 | OP_STURB, | |
437 | OP_LDURB, | |
438 | OP_LDURSB, | |
439 | OP_STURH, | |
440 | OP_LDURH, | |
441 | OP_LDURSH, | |
442 | OP_STUR, | |
443 | OP_LDUR, | |
444 | OP_STURV, | |
445 | OP_LDURV, | |
446 | OP_LDURSW, | |
447 | OP_PRFUM, | |
448 | ||
449 | OP_LDR_LIT, | |
450 | OP_LDRV_LIT, | |
451 | OP_LDRSW_LIT, | |
452 | OP_PRFM_LIT, | |
453 | ||
454 | OP_ADD, | |
455 | OP_B, | |
456 | OP_BL, | |
457 | ||
458 | OP_MOVN, | |
459 | OP_MOVZ, | |
460 | OP_MOVK, | |
461 | ||
462 | OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ | |
463 | OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ | |
464 | OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ | |
465 | ||
466 | OP_MOV_V, /* MOV alias for moving vector register. */ | |
467 | ||
468 | OP_ASR_IMM, | |
469 | OP_LSR_IMM, | |
470 | OP_LSL_IMM, | |
471 | ||
472 | OP_BIC, | |
473 | ||
474 | OP_UBFX, | |
475 | OP_BFXIL, | |
476 | OP_SBFX, | |
477 | OP_SBFIZ, | |
478 | OP_BFI, | |
d685192a | 479 | OP_BFC, /* ARMv8.2. */ |
a06ea964 NC |
480 | OP_UBFIZ, |
481 | OP_UXTB, | |
482 | OP_UXTH, | |
483 | OP_UXTW, | |
484 | ||
a06ea964 NC |
485 | OP_CINC, |
486 | OP_CINV, | |
487 | OP_CNEG, | |
488 | OP_CSET, | |
489 | OP_CSETM, | |
490 | ||
491 | OP_FCVT, | |
492 | OP_FCVTN, | |
493 | OP_FCVTN2, | |
494 | OP_FCVTL, | |
495 | OP_FCVTL2, | |
496 | OP_FCVTXN_S, /* Scalar version. */ | |
497 | ||
498 | OP_ROR_IMM, | |
499 | ||
e30181a5 YZ |
500 | OP_SXTL, |
501 | OP_SXTL2, | |
502 | OP_UXTL, | |
503 | OP_UXTL2, | |
504 | ||
a06ea964 NC |
505 | OP_TOTAL_NUM, /* Pseudo. */ |
506 | }; | |
507 | ||
508 | /* Maximum number of operands an instruction can have. */ | |
509 | #define AARCH64_MAX_OPND_NUM 6 | |
510 | /* Maximum number of qualifier sequences an instruction can have. */ | |
511 | #define AARCH64_MAX_QLF_SEQ_NUM 10 | |
512 | /* Operand qualifier typedef; optimized for the size. */ | |
513 | typedef unsigned char aarch64_opnd_qualifier_t; | |
514 | /* Operand qualifier sequence typedef. */ | |
515 | typedef aarch64_opnd_qualifier_t \ | |
516 | aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; | |
517 | ||
518 | /* FIXME: improve the efficiency. */ | |
519 | static inline bfd_boolean | |
520 | empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) | |
521 | { | |
522 | int i; | |
523 | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) | |
524 | if (qualifiers[i] != AARCH64_OPND_QLF_NIL) | |
525 | return FALSE; | |
526 | return TRUE; | |
527 | } | |
528 | ||
529 | /* This structure holds information for a particular opcode. */ | |
530 | ||
531 | struct aarch64_opcode | |
532 | { | |
533 | /* The name of the mnemonic. */ | |
534 | const char *name; | |
535 | ||
536 | /* The opcode itself. Those bits which will be filled in with | |
537 | operands are zeroes. */ | |
538 | aarch64_insn opcode; | |
539 | ||
540 | /* The opcode mask. This is used by the disassembler. This is a | |
541 | mask containing ones indicating those bits which must match the | |
542 | opcode field, and zeroes indicating those bits which need not | |
543 | match (and are presumably filled in by operands). */ | |
544 | aarch64_insn mask; | |
545 | ||
546 | /* Instruction class. */ | |
547 | enum aarch64_insn_class iclass; | |
548 | ||
549 | /* Enumerator identifier. */ | |
550 | enum aarch64_op op; | |
551 | ||
552 | /* Which architecture variant provides this instruction. */ | |
553 | const aarch64_feature_set *avariant; | |
554 | ||
555 | /* An array of operand codes. Each code is an index into the | |
556 | operand table. They appear in the order which the operands must | |
557 | appear in assembly code, and are terminated by a zero. */ | |
558 | enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; | |
559 | ||
560 | /* A list of operand qualifier code sequence. Each operand qualifier | |
561 | code qualifies the corresponding operand code. Each operand | |
562 | qualifier sequence specifies a valid opcode variant and related | |
563 | constraint on operands. */ | |
564 | aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; | |
565 | ||
566 | /* Flags providing information about this instruction */ | |
567 | uint32_t flags; | |
4bd13cde | 568 | |
0c608d6b RS |
569 | /* If nonzero, this operand and operand 0 are both registers and |
570 | are required to have the same register number. */ | |
571 | unsigned char tied_operand; | |
572 | ||
4bd13cde NC |
573 | /* If non-NULL, a function to verify that a given instruction is valid. */ |
574 | bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn); | |
a06ea964 NC |
575 | }; |
576 | ||
577 | typedef struct aarch64_opcode aarch64_opcode; | |
578 | ||
579 | /* Table describing all the AArch64 opcodes. */ | |
580 | extern aarch64_opcode aarch64_opcode_table[]; | |
581 | ||
582 | /* Opcode flags. */ | |
583 | #define F_ALIAS (1 << 0) | |
584 | #define F_HAS_ALIAS (1 << 1) | |
585 | /* Disassembly preference priority 1-3 (the larger the higher). If nothing | |
586 | is specified, it is the priority 0 by default, i.e. the lowest priority. */ | |
587 | #define F_P1 (1 << 2) | |
588 | #define F_P2 (2 << 2) | |
589 | #define F_P3 (3 << 2) | |
590 | /* Flag an instruction that is truly conditional executed, e.g. b.cond. */ | |
591 | #define F_COND (1 << 4) | |
592 | /* Instruction has the field of 'sf'. */ | |
593 | #define F_SF (1 << 5) | |
594 | /* Instruction has the field of 'size:Q'. */ | |
595 | #define F_SIZEQ (1 << 6) | |
596 | /* Floating-point instruction has the field of 'type'. */ | |
597 | #define F_FPTYPE (1 << 7) | |
598 | /* AdvSIMD scalar instruction has the field of 'size'. */ | |
599 | #define F_SSIZE (1 << 8) | |
600 | /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ | |
601 | #define F_T (1 << 9) | |
602 | /* Size of GPR operand in AdvSIMD instructions encoded in Q. */ | |
603 | #define F_GPRSIZE_IN_Q (1 << 10) | |
604 | /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ | |
605 | #define F_LDS_SIZE (1 << 11) | |
606 | /* Optional operand; assume maximum of 1 operand can be optional. */ | |
607 | #define F_OPD0_OPT (1 << 12) | |
608 | #define F_OPD1_OPT (2 << 12) | |
609 | #define F_OPD2_OPT (3 << 12) | |
610 | #define F_OPD3_OPT (4 << 12) | |
611 | #define F_OPD4_OPT (5 << 12) | |
612 | /* Default value for the optional operand when omitted from the assembly. */ | |
613 | #define F_DEFAULT(X) (((X) & 0x1f) << 15) | |
614 | /* Instruction that is an alias of another instruction needs to be | |
615 | encoded/decoded by converting it to/from the real form, followed by | |
616 | the encoding/decoding according to the rules of the real opcode. | |
617 | This compares to the direct coding using the alias's information. | |
618 | N.B. this flag requires F_ALIAS to be used together. */ | |
619 | #define F_CONV (1 << 20) | |
620 | /* Use together with F_ALIAS to indicate an alias opcode is a programmer | |
621 | friendly pseudo instruction available only in the assembly code (thus will | |
622 | not show up in the disassembly). */ | |
623 | #define F_PSEUDO (1 << 21) | |
624 | /* Instruction has miscellaneous encoding/decoding rules. */ | |
625 | #define F_MISC (1 << 22) | |
626 | /* Instruction has the field of 'N'; used in conjunction with F_SF. */ | |
627 | #define F_N (1 << 23) | |
628 | /* Opcode dependent field. */ | |
629 | #define F_OD(X) (((X) & 0x7) << 24) | |
ee804238 JW |
630 | /* Instruction has the field of 'sz'. */ |
631 | #define F_LSE_SZ (1 << 27) | |
4989adac RS |
632 | /* Require an exact qualifier match, even for NIL qualifiers. */ |
633 | #define F_STRICT (1ULL << 28) | |
634 | /* Next bit is 29. */ | |
a06ea964 NC |
635 | |
636 | static inline bfd_boolean | |
637 | alias_opcode_p (const aarch64_opcode *opcode) | |
638 | { | |
639 | return (opcode->flags & F_ALIAS) ? TRUE : FALSE; | |
640 | } | |
641 | ||
642 | static inline bfd_boolean | |
643 | opcode_has_alias (const aarch64_opcode *opcode) | |
644 | { | |
645 | return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE; | |
646 | } | |
647 | ||
648 | /* Priority for disassembling preference. */ | |
649 | static inline int | |
650 | opcode_priority (const aarch64_opcode *opcode) | |
651 | { | |
652 | return (opcode->flags >> 2) & 0x3; | |
653 | } | |
654 | ||
655 | static inline bfd_boolean | |
656 | pseudo_opcode_p (const aarch64_opcode *opcode) | |
657 | { | |
658 | return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE; | |
659 | } | |
660 | ||
661 | static inline bfd_boolean | |
662 | optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) | |
663 | { | |
664 | return (((opcode->flags >> 12) & 0x7) == idx + 1) | |
665 | ? TRUE : FALSE; | |
666 | } | |
667 | ||
668 | static inline aarch64_insn | |
669 | get_optional_operand_default_value (const aarch64_opcode *opcode) | |
670 | { | |
671 | return (opcode->flags >> 15) & 0x1f; | |
672 | } | |
673 | ||
674 | static inline unsigned int | |
675 | get_opcode_dependent_value (const aarch64_opcode *opcode) | |
676 | { | |
677 | return (opcode->flags >> 24) & 0x7; | |
678 | } | |
679 | ||
680 | static inline bfd_boolean | |
681 | opcode_has_special_coder (const aarch64_opcode *opcode) | |
682 | { | |
ee804238 | 683 | return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T |
a06ea964 NC |
684 | | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE |
685 | : FALSE; | |
686 | } | |
687 | \f | |
688 | struct aarch64_name_value_pair | |
689 | { | |
690 | const char * name; | |
691 | aarch64_insn value; | |
692 | }; | |
693 | ||
694 | extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; | |
a06ea964 NC |
695 | extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; |
696 | extern const struct aarch64_name_value_pair aarch64_prfops [32]; | |
9ed608f9 | 697 | extern const struct aarch64_name_value_pair aarch64_hint_options []; |
a06ea964 | 698 | |
49eec193 YZ |
699 | typedef struct |
700 | { | |
701 | const char * name; | |
702 | aarch64_insn value; | |
703 | uint32_t flags; | |
704 | } aarch64_sys_reg; | |
705 | ||
706 | extern const aarch64_sys_reg aarch64_sys_regs []; | |
87b8eed7 | 707 | extern const aarch64_sys_reg aarch64_pstatefields []; |
49eec193 | 708 | extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *); |
f21cce2c MW |
709 | extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set, |
710 | const aarch64_sys_reg *); | |
711 | extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set, | |
712 | const aarch64_sys_reg *); | |
49eec193 | 713 | |
a06ea964 NC |
714 | typedef struct |
715 | { | |
875880c6 | 716 | const char *name; |
a06ea964 | 717 | uint32_t value; |
ea2deeec | 718 | uint32_t flags ; |
a06ea964 NC |
719 | } aarch64_sys_ins_reg; |
720 | ||
ea2deeec | 721 | extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *); |
d6bf7ce6 MW |
722 | extern bfd_boolean |
723 | aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, | |
724 | const aarch64_sys_ins_reg *); | |
ea2deeec | 725 | |
a06ea964 NC |
726 | extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; |
727 | extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; | |
728 | extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; | |
729 | extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; | |
730 | ||
731 | /* Shift/extending operator kinds. | |
732 | N.B. order is important; keep aarch64_operand_modifiers synced. */ | |
733 | enum aarch64_modifier_kind | |
734 | { | |
735 | AARCH64_MOD_NONE, | |
736 | AARCH64_MOD_MSL, | |
737 | AARCH64_MOD_ROR, | |
738 | AARCH64_MOD_ASR, | |
739 | AARCH64_MOD_LSR, | |
740 | AARCH64_MOD_LSL, | |
741 | AARCH64_MOD_UXTB, | |
742 | AARCH64_MOD_UXTH, | |
743 | AARCH64_MOD_UXTW, | |
744 | AARCH64_MOD_UXTX, | |
745 | AARCH64_MOD_SXTB, | |
746 | AARCH64_MOD_SXTH, | |
747 | AARCH64_MOD_SXTW, | |
748 | AARCH64_MOD_SXTX, | |
2442d846 | 749 | AARCH64_MOD_MUL, |
a06ea964 NC |
750 | }; |
751 | ||
752 | bfd_boolean | |
753 | aarch64_extend_operator_p (enum aarch64_modifier_kind); | |
754 | ||
755 | enum aarch64_modifier_kind | |
756 | aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); | |
757 | /* Condition. */ | |
758 | ||
759 | typedef struct | |
760 | { | |
761 | /* A list of names with the first one as the disassembly preference; | |
762 | terminated by NULL if fewer than 3. */ | |
763 | const char *names[3]; | |
764 | aarch64_insn value; | |
765 | } aarch64_cond; | |
766 | ||
767 | extern const aarch64_cond aarch64_conds[16]; | |
768 | ||
769 | const aarch64_cond* get_cond_from_value (aarch64_insn value); | |
770 | const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); | |
771 | \f | |
772 | /* Structure representing an operand. */ | |
773 | ||
774 | struct aarch64_opnd_info | |
775 | { | |
776 | enum aarch64_opnd type; | |
777 | aarch64_opnd_qualifier_t qualifier; | |
778 | int idx; | |
779 | ||
780 | union | |
781 | { | |
782 | struct | |
783 | { | |
784 | unsigned regno; | |
785 | } reg; | |
786 | struct | |
787 | { | |
dab26bf4 RS |
788 | unsigned int regno; |
789 | int64_t index; | |
a06ea964 NC |
790 | } reglane; |
791 | /* e.g. LVn. */ | |
792 | struct | |
793 | { | |
794 | unsigned first_regno : 5; | |
795 | unsigned num_regs : 3; | |
796 | /* 1 if it is a list of reg element. */ | |
797 | unsigned has_index : 1; | |
798 | /* Lane index; valid only when has_index is 1. */ | |
dab26bf4 | 799 | int64_t index; |
a06ea964 NC |
800 | } reglist; |
801 | /* e.g. immediate or pc relative address offset. */ | |
802 | struct | |
803 | { | |
804 | int64_t value; | |
805 | unsigned is_fp : 1; | |
806 | } imm; | |
807 | /* e.g. address in STR (register offset). */ | |
808 | struct | |
809 | { | |
810 | unsigned base_regno; | |
811 | struct | |
812 | { | |
813 | union | |
814 | { | |
815 | int imm; | |
816 | unsigned regno; | |
817 | }; | |
818 | unsigned is_reg; | |
819 | } offset; | |
820 | unsigned pcrel : 1; /* PC-relative. */ | |
821 | unsigned writeback : 1; | |
822 | unsigned preind : 1; /* Pre-indexed. */ | |
823 | unsigned postind : 1; /* Post-indexed. */ | |
824 | } addr; | |
825 | const aarch64_cond *cond; | |
826 | /* The encoding of the system register. */ | |
827 | aarch64_insn sysreg; | |
828 | /* The encoding of the PSTATE field. */ | |
829 | aarch64_insn pstatefield; | |
830 | const aarch64_sys_ins_reg *sysins_op; | |
831 | const struct aarch64_name_value_pair *barrier; | |
9ed608f9 | 832 | const struct aarch64_name_value_pair *hint_option; |
a06ea964 NC |
833 | const struct aarch64_name_value_pair *prfop; |
834 | }; | |
835 | ||
836 | /* Operand shifter; in use when the operand is a register offset address, | |
837 | add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ | |
838 | struct | |
839 | { | |
840 | enum aarch64_modifier_kind kind; | |
a06ea964 NC |
841 | unsigned operator_present: 1; /* Only valid during encoding. */ |
842 | /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ | |
843 | unsigned amount_present: 1; | |
2442d846 | 844 | int64_t amount; |
a06ea964 NC |
845 | } shifter; |
846 | ||
847 | unsigned skip:1; /* Operand is not completed if there is a fixup needed | |
848 | to be done on it. In some (but not all) of these | |
849 | cases, we need to tell libopcodes to skip the | |
850 | constraint checking and the encoding for this | |
851 | operand, so that the libopcodes can pick up the | |
852 | right opcode before the operand is fixed-up. This | |
853 | flag should only be used during the | |
854 | assembling/encoding. */ | |
855 | unsigned present:1; /* Whether this operand is present in the assembly | |
856 | line; not used during the disassembly. */ | |
857 | }; | |
858 | ||
859 | typedef struct aarch64_opnd_info aarch64_opnd_info; | |
860 | ||
861 | /* Structure representing an instruction. | |
862 | ||
863 | It is used during both the assembling and disassembling. The assembler | |
864 | fills an aarch64_inst after a successful parsing and then passes it to the | |
865 | encoding routine to do the encoding. During the disassembling, the | |
866 | disassembler calls the decoding routine to decode a binary instruction; on a | |
867 | successful return, such a structure will be filled with information of the | |
868 | instruction; then the disassembler uses the information to print out the | |
869 | instruction. */ | |
870 | ||
871 | struct aarch64_inst | |
872 | { | |
873 | /* The value of the binary instruction. */ | |
874 | aarch64_insn value; | |
875 | ||
876 | /* Corresponding opcode entry. */ | |
877 | const aarch64_opcode *opcode; | |
878 | ||
879 | /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ | |
880 | const aarch64_cond *cond; | |
881 | ||
882 | /* Operands information. */ | |
883 | aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; | |
884 | }; | |
885 | ||
886 | typedef struct aarch64_inst aarch64_inst; | |
887 | \f | |
888 | /* Diagnosis related declaration and interface. */ | |
889 | ||
890 | /* Operand error kind enumerators. | |
891 | ||
892 | AARCH64_OPDE_RECOVERABLE | |
893 | Less severe error found during the parsing, very possibly because that | |
894 | GAS has picked up a wrong instruction template for the parsing. | |
895 | ||
896 | AARCH64_OPDE_SYNTAX_ERROR | |
897 | General syntax error; it can be either a user error, or simply because | |
898 | that GAS is trying a wrong instruction template. | |
899 | ||
900 | AARCH64_OPDE_FATAL_SYNTAX_ERROR | |
901 | Definitely a user syntax error. | |
902 | ||
903 | AARCH64_OPDE_INVALID_VARIANT | |
904 | No syntax error, but the operands are not a valid combination, e.g. | |
905 | FMOV D0,S0 | |
906 | ||
0c608d6b RS |
907 | AARCH64_OPDE_UNTIED_OPERAND |
908 | The asm failed to use the same register for a destination operand | |
909 | and a tied source operand. | |
910 | ||
a06ea964 NC |
911 | AARCH64_OPDE_OUT_OF_RANGE |
912 | Error about some immediate value out of a valid range. | |
913 | ||
914 | AARCH64_OPDE_UNALIGNED | |
915 | Error about some immediate value not properly aligned (i.e. not being a | |
916 | multiple times of a certain value). | |
917 | ||
918 | AARCH64_OPDE_REG_LIST | |
919 | Error about the register list operand having unexpected number of | |
920 | registers. | |
921 | ||
922 | AARCH64_OPDE_OTHER_ERROR | |
923 | Error of the highest severity and used for any severe issue that does not | |
924 | fall into any of the above categories. | |
925 | ||
926 | The enumerators are only interesting to GAS. They are declared here (in | |
927 | libopcodes) because that some errors are detected (and then notified to GAS) | |
928 | by libopcodes (rather than by GAS solely). | |
929 | ||
930 | The first three errors are only deteced by GAS while the | |
931 | AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as | |
932 | only libopcodes has the information about the valid variants of each | |
933 | instruction. | |
934 | ||
935 | The enumerators have an increasing severity. This is helpful when there are | |
936 | multiple instruction templates available for a given mnemonic name (e.g. | |
937 | FMOV); this mechanism will help choose the most suitable template from which | |
938 | the generated diagnostics can most closely describe the issues, if any. */ | |
939 | ||
940 | enum aarch64_operand_error_kind | |
941 | { | |
942 | AARCH64_OPDE_NIL, | |
943 | AARCH64_OPDE_RECOVERABLE, | |
944 | AARCH64_OPDE_SYNTAX_ERROR, | |
945 | AARCH64_OPDE_FATAL_SYNTAX_ERROR, | |
946 | AARCH64_OPDE_INVALID_VARIANT, | |
0c608d6b | 947 | AARCH64_OPDE_UNTIED_OPERAND, |
a06ea964 NC |
948 | AARCH64_OPDE_OUT_OF_RANGE, |
949 | AARCH64_OPDE_UNALIGNED, | |
950 | AARCH64_OPDE_REG_LIST, | |
951 | AARCH64_OPDE_OTHER_ERROR | |
952 | }; | |
953 | ||
954 | /* N.B. GAS assumes that this structure work well with shallow copy. */ | |
955 | struct aarch64_operand_error | |
956 | { | |
957 | enum aarch64_operand_error_kind kind; | |
958 | int index; | |
959 | const char *error; | |
960 | int data[3]; /* Some data for extra information. */ | |
961 | }; | |
962 | ||
963 | typedef struct aarch64_operand_error aarch64_operand_error; | |
964 | ||
965 | /* Encoding entrypoint. */ | |
966 | ||
967 | extern int | |
968 | aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, | |
969 | aarch64_insn *, aarch64_opnd_qualifier_t *, | |
970 | aarch64_operand_error *); | |
971 | ||
972 | extern const aarch64_opcode * | |
973 | aarch64_replace_opcode (struct aarch64_inst *, | |
974 | const aarch64_opcode *); | |
975 | ||
976 | /* Given the opcode enumerator OP, return the pointer to the corresponding | |
977 | opcode entry. */ | |
978 | ||
979 | extern const aarch64_opcode * | |
980 | aarch64_get_opcode (enum aarch64_op); | |
981 | ||
982 | /* Generate the string representation of an operand. */ | |
983 | extern void | |
984 | aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, | |
985 | const aarch64_opnd_info *, int, int *, bfd_vma *); | |
986 | ||
987 | /* Miscellaneous interface. */ | |
988 | ||
989 | extern int | |
990 | aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); | |
991 | ||
992 | extern aarch64_opnd_qualifier_t | |
993 | aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, | |
994 | const aarch64_opnd_qualifier_t, int); | |
995 | ||
996 | extern int | |
997 | aarch64_num_of_operands (const aarch64_opcode *); | |
998 | ||
999 | extern int | |
1000 | aarch64_stack_pointer_p (const aarch64_opnd_info *); | |
1001 | ||
e141d84e YQ |
1002 | extern int |
1003 | aarch64_zero_register_p (const aarch64_opnd_info *); | |
a06ea964 | 1004 | |
36f4aab1 | 1005 | extern int |
43cdf5ae | 1006 | aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean); |
36f4aab1 | 1007 | |
a06ea964 NC |
1008 | /* Given an operand qualifier, return the expected data element size |
1009 | of a qualified operand. */ | |
1010 | extern unsigned char | |
1011 | aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); | |
1012 | ||
1013 | extern enum aarch64_operand_class | |
1014 | aarch64_get_operand_class (enum aarch64_opnd); | |
1015 | ||
1016 | extern const char * | |
1017 | aarch64_get_operand_name (enum aarch64_opnd); | |
1018 | ||
1019 | extern const char * | |
1020 | aarch64_get_operand_desc (enum aarch64_opnd); | |
1021 | ||
1022 | #ifdef DEBUG_AARCH64 | |
1023 | extern int debug_dump; | |
1024 | ||
1025 | extern void | |
1026 | aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); | |
1027 | ||
1028 | #define DEBUG_TRACE(M, ...) \ | |
1029 | { \ | |
1030 | if (debug_dump) \ | |
1031 | aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ | |
1032 | } | |
1033 | ||
1034 | #define DEBUG_TRACE_IF(C, M, ...) \ | |
1035 | { \ | |
1036 | if (debug_dump && (C)) \ | |
1037 | aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ | |
1038 | } | |
1039 | #else /* !DEBUG_AARCH64 */ | |
1040 | #define DEBUG_TRACE(M, ...) ; | |
1041 | #define DEBUG_TRACE_IF(C, M, ...) ; | |
1042 | #endif /* DEBUG_AARCH64 */ | |
1043 | ||
245d2e3f RS |
1044 | extern const char *const aarch64_sve_pattern_array[32]; |
1045 | extern const char *const aarch64_sve_prfop_array[16]; | |
1046 | ||
d3e12b29 YQ |
1047 | #ifdef __cplusplus |
1048 | } | |
1049 | #endif | |
1050 | ||
a06ea964 | 1051 | #endif /* OPCODE_AARCH64_H */ |