]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - include/opcode/aarch64.h
Fix a potential illegal memory access when creating an srec format file.
[thirdparty/binutils-gdb.git] / include / opcode / aarch64.h
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1/* AArch64 assembler/disassembler support.
2
b3adc24a 3 Copyright (C) 2009-2020 Free Software Foundation, Inc.
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4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
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30#ifdef __cplusplus
31extern "C" {
32#endif
33
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34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
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40#define AARCH64_FEATURE_V8 (1ULL << 0) /* All processors. */
41#define AARCH64_FEATURE_V8_6 (1ULL << 1) /* ARMv8.6 processors. */
42#define AARCH64_FEATURE_BFLOAT16 (1ULL << 2) /* Bfloat16 insns. */
95830c98 43#define AARCH64_FEATURE_V8_A (1ULL << 3) /* Armv8-A processors. */
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44#define AARCH64_FEATURE_SVE2 (1ULL << 4) /* SVE2 instructions. */
45#define AARCH64_FEATURE_V8_2 (1ULL << 5) /* ARMv8.2 processors. */
46#define AARCH64_FEATURE_V8_3 (1ULL << 6) /* ARMv8.3 processors. */
47#define AARCH64_FEATURE_SVE2_AES (1ULL << 7)
48#define AARCH64_FEATURE_SVE2_BITPERM (1ULL << 8)
49#define AARCH64_FEATURE_SVE2_SM4 (1ULL << 9)
50#define AARCH64_FEATURE_SVE2_SHA3 (1ULL << 10)
51#define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */
95830c98 52#define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */
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53#define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */
54#define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */
55#define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */
56#define AARCH64_FEATURE_LSE (1ULL << 20) /* LSE instructions. */
57#define AARCH64_FEATURE_PAN (1ULL << 21) /* PAN instructions. */
58#define AARCH64_FEATURE_LOR (1ULL << 22) /* LOR instructions. */
59#define AARCH64_FEATURE_RDMA (1ULL << 23) /* v8.1 SIMD instructions. */
60#define AARCH64_FEATURE_V8_1 (1ULL << 24) /* v8.1 features. */
61#define AARCH64_FEATURE_F16 (1ULL << 25) /* v8.2 FP16 instructions. */
62#define AARCH64_FEATURE_RAS (1ULL << 26) /* RAS Extensions. */
63#define AARCH64_FEATURE_PROFILE (1ULL << 27) /* Statistical Profiling. */
64#define AARCH64_FEATURE_SVE (1ULL << 28) /* SVE instructions. */
65#define AARCH64_FEATURE_RCPC (1ULL << 29) /* RCPC instructions. */
66#define AARCH64_FEATURE_COMPNUM (1ULL << 30) /* Complex # instructions. */
67#define AARCH64_FEATURE_DOTPROD (1ULL << 31) /* Dot Product instructions. */
68#define AARCH64_FEATURE_SM4 (1ULL << 32) /* SM3 & SM4 instructions. */
69#define AARCH64_FEATURE_SHA2 (1ULL << 33) /* SHA2 instructions. */
70#define AARCH64_FEATURE_SHA3 (1ULL << 34) /* SHA3 instructions. */
71#define AARCH64_FEATURE_AES (1ULL << 35) /* AES instructions. */
72#define AARCH64_FEATURE_F16_FML (1ULL << 36) /* v8.2 FP16FML ins. */
73#define AARCH64_FEATURE_V8_5 (1ULL << 37) /* ARMv8.5 processors. */
74#define AARCH64_FEATURE_FLAGMANIP (1ULL << 38) /* Flag Manipulation insns. */
75#define AARCH64_FEATURE_FRINTTS (1ULL << 39) /* FRINT[32,64][Z,X] insns. */
76#define AARCH64_FEATURE_SB (1ULL << 40) /* SB instruction. */
77#define AARCH64_FEATURE_PREDRES (1ULL << 41) /* Execution and Data Prediction Restriction instructions. */
78#define AARCH64_FEATURE_CVADP (1ULL << 42) /* DC CVADP. */
79#define AARCH64_FEATURE_RNG (1ULL << 43) /* Random Number instructions. */
80#define AARCH64_FEATURE_BTI (1ULL << 44) /* BTI instructions. */
81#define AARCH64_FEATURE_SCXTNUM (1ULL << 45) /* SCXTNUM_ELx. */
82#define AARCH64_FEATURE_ID_PFR2 (1ULL << 46) /* ID_PFR2 instructions. */
83#define AARCH64_FEATURE_SSBS (1ULL << 47) /* SSBS mechanism enabled. */
84#define AARCH64_FEATURE_MEMTAG (1ULL << 48) /* Memory Tagging Extension. */
85#define AARCH64_FEATURE_TME (1ULL << 49) /* Transactional Memory Extension. */
86#define AARCH64_FEATURE_I8MM (1ULL << 52) /* Matrix Multiply instructions. */
87#define AARCH64_FEATURE_F32MM (1ULL << 53)
88#define AARCH64_FEATURE_F64MM (1ULL << 54)
7ce2460a 89
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90/* Crypto instructions are the combination of AES and SHA2. */
91#define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
92
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93/* Architectures are the sum of the base and extensions. */
94#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
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95 AARCH64_FEATURE_V8_A \
96 | AARCH64_FEATURE_FP \
a06ea964 97 | AARCH64_FEATURE_SIMD)
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98#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
99 AARCH64_FEATURE_CRC \
250aafa4 100 | AARCH64_FEATURE_V8_1 \
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101 | AARCH64_FEATURE_LSE \
102 | AARCH64_FEATURE_PAN \
103 | AARCH64_FEATURE_LOR \
104 | AARCH64_FEATURE_RDMA)
1924ff75 105#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 106 AARCH64_FEATURE_V8_2 \
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107 | AARCH64_FEATURE_RAS)
108#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 109 AARCH64_FEATURE_V8_3 \
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110 | AARCH64_FEATURE_RCPC \
111 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c 112#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
981b557a 113 AARCH64_FEATURE_V8_4 \
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114 | AARCH64_FEATURE_DOTPROD \
115 | AARCH64_FEATURE_F16_FML)
70d56181 116#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
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117 AARCH64_FEATURE_V8_5 \
118 | AARCH64_FEATURE_FLAGMANIP \
68dfbb92 119 | AARCH64_FEATURE_FRINTTS \
2ac435d4 120 | AARCH64_FEATURE_SB \
3fd229a4 121 | AARCH64_FEATURE_PREDRES \
ff605452 122 | AARCH64_FEATURE_CVADP \
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123 | AARCH64_FEATURE_BTI \
124 | AARCH64_FEATURE_SCXTNUM \
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125 | AARCH64_FEATURE_ID_PFR2 \
126 | AARCH64_FEATURE_SSBS)
8ae2d3d9 127#define AARCH64_ARCH_V8_6 AARCH64_FEATURE (AARCH64_ARCH_V8_5, \
df678013 128 AARCH64_FEATURE_V8_6 \
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129 | AARCH64_FEATURE_BFLOAT16 \
130 | AARCH64_FEATURE_I8MM)
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131#define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
132 AARCH64_FEATURE_V8_R) \
133 & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR))
88f0ea34 134
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135#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
136#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
137
138/* CPU-specific features. */
21b81e67 139typedef unsigned long long aarch64_feature_set;
a06ea964 140
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141#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
142 ((~(CPU) & (FEAT)) == 0)
143
144#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
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145 (((CPU) & (FEAT)) != 0)
146
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147#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
148 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
149
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150#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
151 do \
152 { \
153 (TARG) = (F1) | (F2); \
154 } \
155 while (0)
156
157#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
158 do \
159 { \
160 (TARG) = (F1) &~ (F2); \
161 } \
162 while (0)
163
164#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
165
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166enum aarch64_operand_class
167{
168 AARCH64_OPND_CLASS_NIL,
169 AARCH64_OPND_CLASS_INT_REG,
170 AARCH64_OPND_CLASS_MODIFIED_REG,
171 AARCH64_OPND_CLASS_FP_REG,
172 AARCH64_OPND_CLASS_SIMD_REG,
173 AARCH64_OPND_CLASS_SIMD_ELEMENT,
174 AARCH64_OPND_CLASS_SISD_REG,
175 AARCH64_OPND_CLASS_SIMD_REGLIST,
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176 AARCH64_OPND_CLASS_SVE_REG,
177 AARCH64_OPND_CLASS_PRED_REG,
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178 AARCH64_OPND_CLASS_ADDRESS,
179 AARCH64_OPND_CLASS_IMMEDIATE,
180 AARCH64_OPND_CLASS_SYSTEM,
68a64283 181 AARCH64_OPND_CLASS_COND,
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182};
183
184/* Operand code that helps both parsing and coding.
185 Keep AARCH64_OPERANDS synced. */
186
187enum aarch64_opnd
188{
189 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
190
191 AARCH64_OPND_Rd, /* Integer register as destination. */
192 AARCH64_OPND_Rn, /* Integer register as source. */
193 AARCH64_OPND_Rm, /* Integer register as source. */
194 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
195 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
bd7ceb8d 196 AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */
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197 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
198 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
199 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
200
201 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
202 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 203 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 204 AARCH64_OPND_PAIRREG, /* Paired register operand. */
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205 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
206 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
207
208 AARCH64_OPND_Fd, /* Floating-point Fd. */
209 AARCH64_OPND_Fn, /* Floating-point Fn. */
210 AARCH64_OPND_Fm, /* Floating-point Fm. */
211 AARCH64_OPND_Fa, /* Floating-point Fa. */
212 AARCH64_OPND_Ft, /* Floating-point Ft. */
213 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
214
215 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
216 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
217 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
218
f42f1a1d 219 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
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220 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
221 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
222 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
223 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
224 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
225 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
226 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
227 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
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228 AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
229 qualifier is S_H. */
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230 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
231 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
232 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
233 structure to all lanes. */
234 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
235
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236 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
237 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
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238
239 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
f42f1a1d 240 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
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241 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
242 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
243 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
244 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
245 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
246 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
247 (no encoding). */
248 AARCH64_OPND_IMM0, /* Immediate for #0. */
249 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
250 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
251 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
252 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
253 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
254 AARCH64_OPND_IMM, /* Immediate. */
f42f1a1d 255 AARCH64_OPND_IMM_2, /* Immediate. */
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256 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
257 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
258 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
193614f2 259 AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */
a06ea964 260 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
193614f2 261 AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */
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262 AARCH64_OPND_BIT_NUM, /* Immediate. */
263 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
09c1e68a 264 AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */
a06ea964 265 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 266 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
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267 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
268 each condition flag. */
269
270 AARCH64_OPND_LIMM, /* Logical Immediate. */
271 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
272 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
273 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
274 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
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275 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
276 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
277 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
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278
279 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 280 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
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281
282 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
283 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
284 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
285 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
286 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
287
288 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
289 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
290 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
291 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
292 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
293 negative or unaligned and there is
294 no writeback allowed. This operand code
295 is only used to support the programmer-
296 friendly feature of using LDR/STR as the
297 the mnemonic name for LDUR/STUR instructions
298 wherever there is no ambiguity. */
3f06e550 299 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
fb3265b3
SD
300 AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of
301 16) immediate. */
a06ea964 302 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
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SD
303 AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of
304 16) immediate. */
a06ea964 305 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
f42f1a1d 306 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
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307 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
308
309 AARCH64_OPND_SYSREG, /* System register operand. */
310 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
311 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
312 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
313 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
314 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
2ac435d4 315 AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
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316 AARCH64_OPND_BARRIER, /* Barrier operand. */
317 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
318 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 319 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
ff605452 320 AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
f11ad6bc 321
582e12bf 322 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
8382113f 323 AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn|SP>, #<simm4>*32]. */
98907a70
RS
324 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
325 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
326 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
327 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
328 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
329 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS
330 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
331 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
332 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
333 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
c8d59609 334 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
4df068de
RS
335 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
336 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
337 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
338 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
339 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
340 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
341 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
342 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
c469c864 343 AARCH64_OPND_SVE_ADDR_ZX, /* SVE [Zn.<T>{, <Xm>}]. */
4df068de
RS
344 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
345 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
346 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
347 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
348 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
349 Bit 14 controls S/U choice. */
350 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
351 Bit 22 controls S/U choice. */
352 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
353 Bit 14 controls S/U choice. */
354 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
355 Bit 22 controls S/U choice. */
356 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
357 Bit 14 controls S/U choice. */
358 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
359 Bit 22 controls S/U choice. */
360 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
361 Bit 14 controls S/U choice. */
362 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
363 Bit 22 controls S/U choice. */
364 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
365 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
366 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
367 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
368 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
369 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
370 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS
371 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
372 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS
373 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
374 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
375 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
376 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS
377 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
378 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
adccc507 379 AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */
e950b345
RS
380 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
381 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
382 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 383 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 384 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 385 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS
386 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
387 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
388 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
389 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
390 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
391 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
392 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
393 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS
394 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
395 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS
396 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
397 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
28ed815a 398 AARCH64_OPND_SVE_SHLIMM_UNPRED_22, /* SVE 3 bit shift left unpred. */
e950b345
RS
399 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
400 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
3c17238b 401 AARCH64_OPND_SVE_SHRIMM_UNPRED_22, /* SVE 3 bit shift right unpred. */
e950b345
RS
402 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
403 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
404 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
405 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
406 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
407 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
408 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
409 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS
410 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
411 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
412 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
413 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS
414 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
415 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
416 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
417 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
418 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS
419 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
420 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
116adc27 421 AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */
31e36ab3 422 AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */
582e12bf 423 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS
424 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
425 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
426 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
427 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
428 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
b83b4b13 429 AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
f42f1a1d 430 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
a06ea964
NC
431};
432
433/* Qualifier constrains an operand. It either specifies a variant of an
434 operand type or limits values available to an operand type.
435
436 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
437
438enum aarch64_opnd_qualifier
439{
440 /* Indicating no further qualification on an operand. */
441 AARCH64_OPND_QLF_NIL,
442
443 /* Qualifying an operand which is a general purpose (integer) register;
444 indicating the operand data size or a specific register. */
445 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
446 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
447 AARCH64_OPND_QLF_WSP, /* WSP. */
448 AARCH64_OPND_QLF_SP, /* SP. */
449
450 /* Qualifying an operand which is a floating-point register, a SIMD
451 vector element or a SIMD vector element list; indicating operand data
452 size or the size of each SIMD vector element in the case of a SIMD
453 vector element list.
454 These qualifiers are also used to qualify an address operand to
455 indicate the size of data element a load/store instruction is
456 accessing.
457 They are also used for the immediate shift operand in e.g. SSHR. Such
458 a use is only for the ease of operand encoding/decoding and qualifier
459 sequence matching; such a use should not be applied widely; use the value
460 constraint qualifiers for immediate operands wherever possible. */
461 AARCH64_OPND_QLF_S_B,
462 AARCH64_OPND_QLF_S_H,
463 AARCH64_OPND_QLF_S_S,
464 AARCH64_OPND_QLF_S_D,
465 AARCH64_OPND_QLF_S_Q,
df678013
MM
466 /* These type qualifiers have a special meaning in that they mean 4 x 1 byte
467 or 2 x 2 byte are selected by the instruction. Other than that they have
468 no difference with AARCH64_OPND_QLF_S_B in encoding. They are here purely
469 for syntactical reasons and is an exception from normal AArch64
470 disassembly scheme. */
00c2093f 471 AARCH64_OPND_QLF_S_4B,
df678013 472 AARCH64_OPND_QLF_S_2H,
a06ea964
NC
473
474 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
475 register list; indicating register shape.
476 They are also used for the immediate shift operand in e.g. SSHR. Such
477 a use is only for the ease of operand encoding/decoding and qualifier
478 sequence matching; such a use should not be applied widely; use the value
479 constraint qualifiers for immediate operands wherever possible. */
a3b3345a 480 AARCH64_OPND_QLF_V_4B,
a06ea964
NC
481 AARCH64_OPND_QLF_V_8B,
482 AARCH64_OPND_QLF_V_16B,
3067d3b9 483 AARCH64_OPND_QLF_V_2H,
a06ea964
NC
484 AARCH64_OPND_QLF_V_4H,
485 AARCH64_OPND_QLF_V_8H,
486 AARCH64_OPND_QLF_V_2S,
487 AARCH64_OPND_QLF_V_4S,
488 AARCH64_OPND_QLF_V_1D,
489 AARCH64_OPND_QLF_V_2D,
490 AARCH64_OPND_QLF_V_1Q,
491
d50c751e
RS
492 AARCH64_OPND_QLF_P_Z,
493 AARCH64_OPND_QLF_P_M,
fb3265b3
SD
494
495 /* Used in scaled signed immediate that are scaled by a Tag granule
496 like in stg, st2g, etc. */
497 AARCH64_OPND_QLF_imm_tag,
d50c751e 498
a06ea964 499 /* Constraint on value. */
a6a51754 500 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC
501 AARCH64_OPND_QLF_imm_0_7,
502 AARCH64_OPND_QLF_imm_0_15,
503 AARCH64_OPND_QLF_imm_0_31,
504 AARCH64_OPND_QLF_imm_0_63,
505 AARCH64_OPND_QLF_imm_1_32,
506 AARCH64_OPND_QLF_imm_1_64,
507
508 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
509 or shift-ones. */
510 AARCH64_OPND_QLF_LSL,
511 AARCH64_OPND_QLF_MSL,
512
513 /* Special qualifier helping retrieve qualifier information during the
514 decoding time (currently not in use). */
515 AARCH64_OPND_QLF_RETRIEVE,
516};
517\f
518/* Instruction class. */
519
520enum aarch64_insn_class
521{
8382113f 522 aarch64_misc,
a06ea964
NC
523 addsub_carry,
524 addsub_ext,
525 addsub_imm,
526 addsub_shift,
527 asimdall,
528 asimddiff,
529 asimdelem,
530 asimdext,
531 asimdimm,
532 asimdins,
533 asimdmisc,
534 asimdperm,
535 asimdsame,
536 asimdshf,
537 asimdtbl,
538 asisddiff,
539 asisdelem,
540 asisdlse,
541 asisdlsep,
542 asisdlso,
543 asisdlsop,
544 asisdmisc,
545 asisdone,
546 asisdpair,
547 asisdsame,
548 asisdshf,
549 bitfield,
550 branch_imm,
551 branch_reg,
552 compbranch,
553 condbranch,
554 condcmp_imm,
555 condcmp_reg,
556 condsel,
557 cryptoaes,
558 cryptosha2,
559 cryptosha3,
560 dp_1src,
561 dp_2src,
562 dp_3src,
563 exception,
564 extract,
565 float2fix,
566 float2int,
567 floatccmp,
568 floatcmp,
569 floatdp1,
570 floatdp2,
571 floatdp3,
572 floatimm,
573 floatsel,
574 ldst_immpost,
575 ldst_immpre,
576 ldst_imm9, /* immpost or immpre */
3f06e550 577 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC
578 ldst_pos,
579 ldst_regoff,
580 ldst_unpriv,
581 ldst_unscaled,
582 ldstexcl,
583 ldstnapair_offs,
584 ldstpair_off,
585 ldstpair_indexed,
586 loadlit,
587 log_imm,
588 log_shift,
ee804238 589 lse_atomic,
a06ea964
NC
590 movewide,
591 pcreladdr,
592 ic_system,
116b6019
RS
593 sve_cpy,
594 sve_index,
595 sve_limm,
596 sve_misc,
597 sve_movprfx,
598 sve_pred_zm,
599 sve_shift_pred,
600 sve_shift_unpred,
601 sve_size_bhs,
602 sve_size_bhsd,
603 sve_size_hsd,
3bd82c86 604 sve_size_hsd2,
116b6019 605 sve_size_sd,
3c705960 606 sve_size_bh,
0a57e14f 607 sve_size_sd2,
41be57ca 608 sve_size_13,
3c17238b 609 sve_shift_tsz_hsd,
1be5f94f 610 sve_shift_tsz_bhsd,
fd1dc4a0 611 sve_size_tsz_bhs,
a06ea964 612 testbranch,
f42f1a1d
TC
613 cryptosm3,
614 cryptosm4,
65a55fbb 615 dotproduct,
df678013 616 bfloat16,
a06ea964
NC
617};
618
619/* Opcode enumerators. */
620
621enum aarch64_op
622{
623 OP_NIL,
624 OP_STRB_POS,
625 OP_LDRB_POS,
626 OP_LDRSB_POS,
627 OP_STRH_POS,
628 OP_LDRH_POS,
629 OP_LDRSH_POS,
630 OP_STR_POS,
631 OP_LDR_POS,
632 OP_STRF_POS,
633 OP_LDRF_POS,
634 OP_LDRSW_POS,
635 OP_PRFM_POS,
636
637 OP_STURB,
638 OP_LDURB,
639 OP_LDURSB,
640 OP_STURH,
641 OP_LDURH,
642 OP_LDURSH,
643 OP_STUR,
644 OP_LDUR,
645 OP_STURV,
646 OP_LDURV,
647 OP_LDURSW,
648 OP_PRFUM,
649
650 OP_LDR_LIT,
651 OP_LDRV_LIT,
652 OP_LDRSW_LIT,
653 OP_PRFM_LIT,
654
655 OP_ADD,
656 OP_B,
657 OP_BL,
658
659 OP_MOVN,
660 OP_MOVZ,
661 OP_MOVK,
662
663 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
664 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
665 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
666
667 OP_MOV_V, /* MOV alias for moving vector register. */
668
669 OP_ASR_IMM,
670 OP_LSR_IMM,
671 OP_LSL_IMM,
672
673 OP_BIC,
674
675 OP_UBFX,
676 OP_BFXIL,
677 OP_SBFX,
678 OP_SBFIZ,
679 OP_BFI,
d685192a 680 OP_BFC, /* ARMv8.2. */
a06ea964
NC
681 OP_UBFIZ,
682 OP_UXTB,
683 OP_UXTH,
684 OP_UXTW,
685
a06ea964
NC
686 OP_CINC,
687 OP_CINV,
688 OP_CNEG,
689 OP_CSET,
690 OP_CSETM,
691
692 OP_FCVT,
693 OP_FCVTN,
694 OP_FCVTN2,
695 OP_FCVTL,
696 OP_FCVTL2,
697 OP_FCVTXN_S, /* Scalar version. */
698
699 OP_ROR_IMM,
700
e30181a5
YZ
701 OP_SXTL,
702 OP_SXTL2,
703 OP_UXTL,
704 OP_UXTL2,
705
c0890d26
RS
706 OP_MOV_P_P,
707 OP_MOV_Z_P_Z,
708 OP_MOV_Z_V,
709 OP_MOV_Z_Z,
710 OP_MOV_Z_Zi,
711 OP_MOVM_P_P_P,
712 OP_MOVS_P_P,
713 OP_MOVZS_P_P_P,
714 OP_MOVZ_P_P_P,
715 OP_NOTS_P_P_P_Z,
716 OP_NOT_P_P_P_Z,
717
c2c4ff8d
SN
718 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
719
a06ea964
NC
720 OP_TOTAL_NUM, /* Pseudo. */
721};
722
1d482394
TC
723/* Error types. */
724enum err_type
725{
726 ERR_OK,
727 ERR_UND,
728 ERR_UNP,
729 ERR_NYI,
a68f4cd2 730 ERR_VFI,
1d482394
TC
731 ERR_NR_ENTRIES
732};
733
a06ea964
NC
734/* Maximum number of operands an instruction can have. */
735#define AARCH64_MAX_OPND_NUM 6
736/* Maximum number of qualifier sequences an instruction can have. */
737#define AARCH64_MAX_QLF_SEQ_NUM 10
738/* Operand qualifier typedef; optimized for the size. */
739typedef unsigned char aarch64_opnd_qualifier_t;
740/* Operand qualifier sequence typedef. */
741typedef aarch64_opnd_qualifier_t \
742 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
743
744/* FIXME: improve the efficiency. */
745static inline bfd_boolean
746empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
747{
748 int i;
749 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
750 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
751 return FALSE;
752 return TRUE;
753}
754
7e84b55d
TC
755/* Forward declare error reporting type. */
756typedef struct aarch64_operand_error aarch64_operand_error;
757/* Forward declare instruction sequence type. */
758typedef struct aarch64_instr_sequence aarch64_instr_sequence;
759/* Forward declare instruction definition. */
760typedef struct aarch64_inst aarch64_inst;
761
a06ea964
NC
762/* This structure holds information for a particular opcode. */
763
764struct aarch64_opcode
765{
766 /* The name of the mnemonic. */
767 const char *name;
768
769 /* The opcode itself. Those bits which will be filled in with
770 operands are zeroes. */
771 aarch64_insn opcode;
772
773 /* The opcode mask. This is used by the disassembler. This is a
774 mask containing ones indicating those bits which must match the
775 opcode field, and zeroes indicating those bits which need not
776 match (and are presumably filled in by operands). */
777 aarch64_insn mask;
778
779 /* Instruction class. */
780 enum aarch64_insn_class iclass;
781
782 /* Enumerator identifier. */
783 enum aarch64_op op;
784
785 /* Which architecture variant provides this instruction. */
786 const aarch64_feature_set *avariant;
787
788 /* An array of operand codes. Each code is an index into the
789 operand table. They appear in the order which the operands must
790 appear in assembly code, and are terminated by a zero. */
791 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
792
793 /* A list of operand qualifier code sequence. Each operand qualifier
794 code qualifies the corresponding operand code. Each operand
795 qualifier sequence specifies a valid opcode variant and related
796 constraint on operands. */
797 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
798
799 /* Flags providing information about this instruction */
eae424ae
TC
800 uint64_t flags;
801
802 /* Extra constraints on the instruction that the verifier checks. */
803 uint32_t constraints;
4bd13cde 804
0c608d6b
RS
805 /* If nonzero, this operand and operand 0 are both registers and
806 are required to have the same register number. */
807 unsigned char tied_operand;
808
4bd13cde 809 /* If non-NULL, a function to verify that a given instruction is valid. */
755b748f
TC
810 enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
811 bfd_vma, bfd_boolean, aarch64_operand_error *,
812 struct aarch64_instr_sequence *);
a06ea964
NC
813};
814
815typedef struct aarch64_opcode aarch64_opcode;
816
817/* Table describing all the AArch64 opcodes. */
818extern aarch64_opcode aarch64_opcode_table[];
819
820/* Opcode flags. */
821#define F_ALIAS (1 << 0)
822#define F_HAS_ALIAS (1 << 1)
823/* Disassembly preference priority 1-3 (the larger the higher). If nothing
824 is specified, it is the priority 0 by default, i.e. the lowest priority. */
825#define F_P1 (1 << 2)
826#define F_P2 (2 << 2)
827#define F_P3 (3 << 2)
828/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
829#define F_COND (1 << 4)
830/* Instruction has the field of 'sf'. */
831#define F_SF (1 << 5)
832/* Instruction has the field of 'size:Q'. */
833#define F_SIZEQ (1 << 6)
834/* Floating-point instruction has the field of 'type'. */
835#define F_FPTYPE (1 << 7)
836/* AdvSIMD scalar instruction has the field of 'size'. */
837#define F_SSIZE (1 << 8)
838/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
839#define F_T (1 << 9)
840/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
841#define F_GPRSIZE_IN_Q (1 << 10)
842/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
843#define F_LDS_SIZE (1 << 11)
844/* Optional operand; assume maximum of 1 operand can be optional. */
845#define F_OPD0_OPT (1 << 12)
846#define F_OPD1_OPT (2 << 12)
847#define F_OPD2_OPT (3 << 12)
848#define F_OPD3_OPT (4 << 12)
849#define F_OPD4_OPT (5 << 12)
850/* Default value for the optional operand when omitted from the assembly. */
851#define F_DEFAULT(X) (((X) & 0x1f) << 15)
852/* Instruction that is an alias of another instruction needs to be
853 encoded/decoded by converting it to/from the real form, followed by
854 the encoding/decoding according to the rules of the real opcode.
855 This compares to the direct coding using the alias's information.
856 N.B. this flag requires F_ALIAS to be used together. */
857#define F_CONV (1 << 20)
858/* Use together with F_ALIAS to indicate an alias opcode is a programmer
859 friendly pseudo instruction available only in the assembly code (thus will
860 not show up in the disassembly). */
861#define F_PSEUDO (1 << 21)
862/* Instruction has miscellaneous encoding/decoding rules. */
863#define F_MISC (1 << 22)
864/* Instruction has the field of 'N'; used in conjunction with F_SF. */
865#define F_N (1 << 23)
866/* Opcode dependent field. */
867#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW
868/* Instruction has the field of 'sz'. */
869#define F_LSE_SZ (1 << 27)
4989adac
RS
870/* Require an exact qualifier match, even for NIL qualifiers. */
871#define F_STRICT (1ULL << 28)
f9830ec1
TC
872/* This system instruction is used to read system registers. */
873#define F_SYS_READ (1ULL << 29)
874/* This system instruction is used to write system registers. */
875#define F_SYS_WRITE (1ULL << 30)
eae424ae
TC
876/* This instruction has an extra constraint on it that imposes a requirement on
877 subsequent instructions. */
878#define F_SCAN (1ULL << 31)
879/* Next bit is 32. */
880
881/* Instruction constraints. */
882/* This instruction has a predication constraint on the instruction at PC+4. */
883#define C_SCAN_MOVPRFX (1U << 0)
884/* This instruction's operation width is determined by the operand with the
885 largest element size. */
886#define C_MAX_ELEM (1U << 1)
887/* Next bit is 2. */
a06ea964
NC
888
889static inline bfd_boolean
890alias_opcode_p (const aarch64_opcode *opcode)
891{
892 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
893}
894
895static inline bfd_boolean
896opcode_has_alias (const aarch64_opcode *opcode)
897{
898 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
899}
900
901/* Priority for disassembling preference. */
902static inline int
903opcode_priority (const aarch64_opcode *opcode)
904{
905 return (opcode->flags >> 2) & 0x3;
906}
907
908static inline bfd_boolean
909pseudo_opcode_p (const aarch64_opcode *opcode)
910{
911 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
912}
913
914static inline bfd_boolean
915optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
916{
917 return (((opcode->flags >> 12) & 0x7) == idx + 1)
918 ? TRUE : FALSE;
919}
920
921static inline aarch64_insn
922get_optional_operand_default_value (const aarch64_opcode *opcode)
923{
924 return (opcode->flags >> 15) & 0x1f;
925}
926
927static inline unsigned int
928get_opcode_dependent_value (const aarch64_opcode *opcode)
929{
930 return (opcode->flags >> 24) & 0x7;
931}
932
933static inline bfd_boolean
934opcode_has_special_coder (const aarch64_opcode *opcode)
935{
ee804238 936 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC
937 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
938 : FALSE;
939}
940\f
941struct aarch64_name_value_pair
942{
943 const char * name;
944 aarch64_insn value;
945};
946
947extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC
948extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
949extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 950extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 951
fa63795f
AC
952#define AARCH64_MAX_SYSREG_NAME_LEN 32
953
49eec193
YZ
954typedef struct
955{
956 const char * name;
957 aarch64_insn value;
958 uint32_t flags;
14962256
AC
959
960 /* A set of features, all of which are required for this system register to be
961 available. */
962 aarch64_feature_set features;
49eec193
YZ
963} aarch64_sys_reg;
964
965extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 966extern const aarch64_sys_reg aarch64_pstatefields [];
f7cb161e 967extern bfd_boolean aarch64_sys_reg_deprecated_p (const uint32_t);
f21cce2c
MW
968extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
969 const aarch64_sys_reg *);
49eec193 970
a06ea964
NC
971typedef struct
972{
875880c6 973 const char *name;
a06ea964 974 uint32_t value;
ea2deeec 975 uint32_t flags ;
a06ea964
NC
976} aarch64_sys_ins_reg;
977
ea2deeec 978extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6 979extern bfd_boolean
38cf07a6
AC
980aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
981 const char *reg_name, aarch64_insn,
f7cb161e 982 uint32_t, aarch64_feature_set);
ea2deeec 983
a06ea964
NC
984extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
985extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
986extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
987extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
2ac435d4 988extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
a06ea964
NC
989
990/* Shift/extending operator kinds.
991 N.B. order is important; keep aarch64_operand_modifiers synced. */
992enum aarch64_modifier_kind
993{
994 AARCH64_MOD_NONE,
995 AARCH64_MOD_MSL,
996 AARCH64_MOD_ROR,
997 AARCH64_MOD_ASR,
998 AARCH64_MOD_LSR,
999 AARCH64_MOD_LSL,
1000 AARCH64_MOD_UXTB,
1001 AARCH64_MOD_UXTH,
1002 AARCH64_MOD_UXTW,
1003 AARCH64_MOD_UXTX,
1004 AARCH64_MOD_SXTB,
1005 AARCH64_MOD_SXTH,
1006 AARCH64_MOD_SXTW,
1007 AARCH64_MOD_SXTX,
2442d846 1008 AARCH64_MOD_MUL,
98907a70 1009 AARCH64_MOD_MUL_VL,
a06ea964
NC
1010};
1011
1012bfd_boolean
1013aarch64_extend_operator_p (enum aarch64_modifier_kind);
1014
1015enum aarch64_modifier_kind
1016aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
1017/* Condition. */
1018
1019typedef struct
1020{
1021 /* A list of names with the first one as the disassembly preference;
1022 terminated by NULL if fewer than 3. */
bb7eff52 1023 const char *names[4];
a06ea964
NC
1024 aarch64_insn value;
1025} aarch64_cond;
1026
1027extern const aarch64_cond aarch64_conds[16];
1028
1029const aarch64_cond* get_cond_from_value (aarch64_insn value);
1030const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
1031\f
1032/* Structure representing an operand. */
1033
1034struct aarch64_opnd_info
1035{
1036 enum aarch64_opnd type;
1037 aarch64_opnd_qualifier_t qualifier;
1038 int idx;
1039
1040 union
1041 {
1042 struct
1043 {
1044 unsigned regno;
1045 } reg;
1046 struct
1047 {
dab26bf4
RS
1048 unsigned int regno;
1049 int64_t index;
a06ea964
NC
1050 } reglane;
1051 /* e.g. LVn. */
1052 struct
1053 {
1054 unsigned first_regno : 5;
1055 unsigned num_regs : 3;
1056 /* 1 if it is a list of reg element. */
1057 unsigned has_index : 1;
1058 /* Lane index; valid only when has_index is 1. */
dab26bf4 1059 int64_t index;
a06ea964
NC
1060 } reglist;
1061 /* e.g. immediate or pc relative address offset. */
1062 struct
1063 {
1064 int64_t value;
1065 unsigned is_fp : 1;
1066 } imm;
1067 /* e.g. address in STR (register offset). */
1068 struct
1069 {
1070 unsigned base_regno;
1071 struct
1072 {
1073 union
1074 {
1075 int imm;
1076 unsigned regno;
1077 };
1078 unsigned is_reg;
1079 } offset;
1080 unsigned pcrel : 1; /* PC-relative. */
1081 unsigned writeback : 1;
1082 unsigned preind : 1; /* Pre-indexed. */
1083 unsigned postind : 1; /* Post-indexed. */
1084 } addr;
561a72d4
TC
1085
1086 struct
1087 {
1088 /* The encoding of the system register. */
1089 aarch64_insn value;
1090
1091 /* The system register flags. */
1092 uint32_t flags;
1093 } sysreg;
1094
a06ea964 1095 const aarch64_cond *cond;
a06ea964
NC
1096 /* The encoding of the PSTATE field. */
1097 aarch64_insn pstatefield;
1098 const aarch64_sys_ins_reg *sysins_op;
1099 const struct aarch64_name_value_pair *barrier;
9ed608f9 1100 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC
1101 const struct aarch64_name_value_pair *prfop;
1102 };
1103
1104 /* Operand shifter; in use when the operand is a register offset address,
1105 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
1106 struct
1107 {
1108 enum aarch64_modifier_kind kind;
a06ea964
NC
1109 unsigned operator_present: 1; /* Only valid during encoding. */
1110 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1111 unsigned amount_present: 1;
2442d846 1112 int64_t amount;
a06ea964
NC
1113 } shifter;
1114
1115 unsigned skip:1; /* Operand is not completed if there is a fixup needed
1116 to be done on it. In some (but not all) of these
1117 cases, we need to tell libopcodes to skip the
1118 constraint checking and the encoding for this
1119 operand, so that the libopcodes can pick up the
1120 right opcode before the operand is fixed-up. This
1121 flag should only be used during the
1122 assembling/encoding. */
1123 unsigned present:1; /* Whether this operand is present in the assembly
1124 line; not used during the disassembly. */
1125};
1126
1127typedef struct aarch64_opnd_info aarch64_opnd_info;
1128
1129/* Structure representing an instruction.
1130
1131 It is used during both the assembling and disassembling. The assembler
1132 fills an aarch64_inst after a successful parsing and then passes it to the
1133 encoding routine to do the encoding. During the disassembling, the
1134 disassembler calls the decoding routine to decode a binary instruction; on a
1135 successful return, such a structure will be filled with information of the
1136 instruction; then the disassembler uses the information to print out the
1137 instruction. */
1138
1139struct aarch64_inst
1140{
1141 /* The value of the binary instruction. */
1142 aarch64_insn value;
1143
1144 /* Corresponding opcode entry. */
1145 const aarch64_opcode *opcode;
1146
1147 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1148 const aarch64_cond *cond;
1149
1150 /* Operands information. */
1151 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1152};
1153
ff605452
SD
1154/* Defining the HINT #imm values for the aarch64_hint_options. */
1155#define HINT_OPD_CSYNC 0x11
1156#define HINT_OPD_C 0x22
1157#define HINT_OPD_J 0x24
1158#define HINT_OPD_JC 0x26
1159#define HINT_OPD_NULL 0x00
1160
a06ea964
NC
1161\f
1162/* Diagnosis related declaration and interface. */
1163
1164/* Operand error kind enumerators.
1165
1166 AARCH64_OPDE_RECOVERABLE
1167 Less severe error found during the parsing, very possibly because that
1168 GAS has picked up a wrong instruction template for the parsing.
1169
1170 AARCH64_OPDE_SYNTAX_ERROR
1171 General syntax error; it can be either a user error, or simply because
1172 that GAS is trying a wrong instruction template.
1173
1174 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1175 Definitely a user syntax error.
1176
1177 AARCH64_OPDE_INVALID_VARIANT
1178 No syntax error, but the operands are not a valid combination, e.g.
1179 FMOV D0,S0
1180
0c608d6b
RS
1181 AARCH64_OPDE_UNTIED_OPERAND
1182 The asm failed to use the same register for a destination operand
1183 and a tied source operand.
1184
a06ea964
NC
1185 AARCH64_OPDE_OUT_OF_RANGE
1186 Error about some immediate value out of a valid range.
1187
1188 AARCH64_OPDE_UNALIGNED
1189 Error about some immediate value not properly aligned (i.e. not being a
1190 multiple times of a certain value).
1191
1192 AARCH64_OPDE_REG_LIST
1193 Error about the register list operand having unexpected number of
1194 registers.
1195
1196 AARCH64_OPDE_OTHER_ERROR
1197 Error of the highest severity and used for any severe issue that does not
1198 fall into any of the above categories.
1199
1200 The enumerators are only interesting to GAS. They are declared here (in
1201 libopcodes) because that some errors are detected (and then notified to GAS)
1202 by libopcodes (rather than by GAS solely).
1203
1204 The first three errors are only deteced by GAS while the
1205 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1206 only libopcodes has the information about the valid variants of each
1207 instruction.
1208
1209 The enumerators have an increasing severity. This is helpful when there are
1210 multiple instruction templates available for a given mnemonic name (e.g.
1211 FMOV); this mechanism will help choose the most suitable template from which
1212 the generated diagnostics can most closely describe the issues, if any. */
1213
1214enum aarch64_operand_error_kind
1215{
1216 AARCH64_OPDE_NIL,
1217 AARCH64_OPDE_RECOVERABLE,
1218 AARCH64_OPDE_SYNTAX_ERROR,
1219 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1220 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1221 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC
1222 AARCH64_OPDE_OUT_OF_RANGE,
1223 AARCH64_OPDE_UNALIGNED,
1224 AARCH64_OPDE_REG_LIST,
1225 AARCH64_OPDE_OTHER_ERROR
1226};
1227
1228/* N.B. GAS assumes that this structure work well with shallow copy. */
1229struct aarch64_operand_error
1230{
1231 enum aarch64_operand_error_kind kind;
1232 int index;
1233 const char *error;
1234 int data[3]; /* Some data for extra information. */
7d02540a 1235 bfd_boolean non_fatal;
a06ea964
NC
1236};
1237
7e84b55d
TC
1238/* AArch64 sequence structure used to track instructions with F_SCAN
1239 dependencies for both assembler and disassembler. */
1240struct aarch64_instr_sequence
1241{
1242 /* The instruction that caused this sequence to be opened. */
1243 aarch64_inst *instr;
1244 /* The number of instructions the above instruction allows to be kept in the
1245 sequence before an automatic close is done. */
1246 int num_insns;
1247 /* The instructions currently added to the sequence. */
1248 aarch64_inst **current_insns;
1249 /* The number of instructions already in the sequence. */
1250 int next_insn;
1251};
a06ea964
NC
1252
1253/* Encoding entrypoint. */
1254
1255extern int
1256aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1257 aarch64_insn *, aarch64_opnd_qualifier_t *,
7e84b55d 1258 aarch64_operand_error *, aarch64_instr_sequence *);
a06ea964
NC
1259
1260extern const aarch64_opcode *
1261aarch64_replace_opcode (struct aarch64_inst *,
1262 const aarch64_opcode *);
1263
1264/* Given the opcode enumerator OP, return the pointer to the corresponding
1265 opcode entry. */
1266
1267extern const aarch64_opcode *
1268aarch64_get_opcode (enum aarch64_op);
1269
1270/* Generate the string representation of an operand. */
1271extern void
1272aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
7d02540a 1273 const aarch64_opnd_info *, int, int *, bfd_vma *,
38cf07a6
AC
1274 char **,
1275 aarch64_feature_set features);
a06ea964
NC
1276
1277/* Miscellaneous interface. */
1278
1279extern int
1280aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1281
1282extern aarch64_opnd_qualifier_t
1283aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1284 const aarch64_opnd_qualifier_t, int);
1285
a68f4cd2
TC
1286extern bfd_boolean
1287aarch64_is_destructive_by_operands (const aarch64_opcode *);
1288
a06ea964
NC
1289extern int
1290aarch64_num_of_operands (const aarch64_opcode *);
1291
1292extern int
1293aarch64_stack_pointer_p (const aarch64_opnd_info *);
1294
e141d84e
YQ
1295extern int
1296aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1297
1d482394 1298extern enum err_type
561a72d4 1299aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
a68f4cd2
TC
1300 aarch64_operand_error *);
1301
1302extern void
1303init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
36f4aab1 1304
a06ea964
NC
1305/* Given an operand qualifier, return the expected data element size
1306 of a qualified operand. */
1307extern unsigned char
1308aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1309
1310extern enum aarch64_operand_class
1311aarch64_get_operand_class (enum aarch64_opnd);
1312
1313extern const char *
1314aarch64_get_operand_name (enum aarch64_opnd);
1315
1316extern const char *
1317aarch64_get_operand_desc (enum aarch64_opnd);
1318
e950b345
RS
1319extern bfd_boolean
1320aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1321
a06ea964
NC
1322#ifdef DEBUG_AARCH64
1323extern int debug_dump;
1324
1325extern void
1326aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1327
1328#define DEBUG_TRACE(M, ...) \
1329 { \
1330 if (debug_dump) \
1331 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1332 }
1333
1334#define DEBUG_TRACE_IF(C, M, ...) \
1335 { \
1336 if (debug_dump && (C)) \
1337 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1338 }
1339#else /* !DEBUG_AARCH64 */
1340#define DEBUG_TRACE(M, ...) ;
1341#define DEBUG_TRACE_IF(C, M, ...) ;
1342#endif /* DEBUG_AARCH64 */
1343
245d2e3f
RS
1344extern const char *const aarch64_sve_pattern_array[32];
1345extern const char *const aarch64_sve_prfop_array[16];
1346
d3e12b29
YQ
1347#ifdef __cplusplus
1348}
1349#endif
1350
a06ea964 1351#endif /* OPCODE_AARCH64_H */