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Fix snafu with booleans in readelf patch - lack of a program header is not a reason...
[thirdparty/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
2571583a 3 Copyright (C) 2009-2017 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
40#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 41#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 42#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 43#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
44#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
45#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 46#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 47#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 48#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 49#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 50#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 51#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 52#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 53#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 54#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 55#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
d74d4880 56#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
a06ea964
NC		 57
58/* Architectures are the sum of the base and extensions. */
59#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
60 AARCH64_FEATURE_FP \
61 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 62#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
63 AARCH64_FEATURE_CRC \
250aafa4 64 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 65 | AARCH64_FEATURE_LSE \
66 | AARCH64_FEATURE_PAN \
67 | AARCH64_FEATURE_LOR \
68 | AARCH64_FEATURE_RDMA)
1924ff75 69#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 70 AARCH64_FEATURE_V8_2 \
87018195 71 | AARCH64_FEATURE_F16 \
1924ff75
SN		 72 | AARCH64_FEATURE_RAS)
73#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880
SN		 74 AARCH64_FEATURE_V8_3 \
75 | AARCH64_FEATURE_RCPC)
88f0ea34 76
a06ea964
NC		 77#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
78#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
79
80/* CPU-specific features. */
81typedef unsigned long aarch64_feature_set;
82
93d8990c
SN		 83#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
84 ((~(CPU) & (FEAT)) == 0)
85
86#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 87 (((CPU) & (FEAT)) != 0)
88
93d8990c
SN		 89#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
90 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
91
a06ea964
NC		 92#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
93 do \
94 { \
95 (TARG) = (F1) | (F2); \
96 } \
97 while (0)
98
99#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
100 do \
101 { \
102 (TARG) = (F1) &~ (F2); \
103 } \
104 while (0)
105
106#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
107
a06ea964
NC		 108enum aarch64_operand_class
109{
110 AARCH64_OPND_CLASS_NIL,
111 AARCH64_OPND_CLASS_INT_REG,
112 AARCH64_OPND_CLASS_MODIFIED_REG,
113 AARCH64_OPND_CLASS_FP_REG,
114 AARCH64_OPND_CLASS_SIMD_REG,
115 AARCH64_OPND_CLASS_SIMD_ELEMENT,
116 AARCH64_OPND_CLASS_SISD_REG,
117 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 118 AARCH64_OPND_CLASS_SVE_REG,
119 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 120 AARCH64_OPND_CLASS_ADDRESS,
121 AARCH64_OPND_CLASS_IMMEDIATE,
122 AARCH64_OPND_CLASS_SYSTEM,
68a64283 123 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 124};
125
126/* Operand code that helps both parsing and coding.
127 Keep AARCH64_OPERANDS synced. */
128
129enum aarch64_opnd
130{
131 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
132
133 AARCH64_OPND_Rd, /* Integer register as destination. */
134 AARCH64_OPND_Rn, /* Integer register as source. */
135 AARCH64_OPND_Rm, /* Integer register as source. */
136 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
137 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
138 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
139 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
140 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
141
142 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
143 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 144 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 145 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 146 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
147 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
148
149 AARCH64_OPND_Fd, /* Floating-point Fd. */
150 AARCH64_OPND_Fn, /* Floating-point Fn. */
151 AARCH64_OPND_Fm, /* Floating-point Fm. */
152 AARCH64_OPND_Fa, /* Floating-point Fa. */
153 AARCH64_OPND_Ft, /* Floating-point Ft. */
154 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
155
156 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
157 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
158 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
159
160 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
161 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
162 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
163 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
164 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
165 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
166 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
167 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
168 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
169 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
170 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
171 structure to all lanes. */
172 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
173
a6a51754
RL		 174 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
175 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 176
177 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
178 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
179 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
180 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
181 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
182 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
183 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
184 (no encoding). */
185 AARCH64_OPND_IMM0, /* Immediate for #0. */
186 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
187 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
188 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
189 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
190 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
191 AARCH64_OPND_IMM, /* Immediate. */
192 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
193 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
194 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
195 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
196 AARCH64_OPND_BIT_NUM, /* Immediate. */
197 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
198 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 199 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 200 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
201 each condition flag. */
202
203 AARCH64_OPND_LIMM, /* Logical Immediate. */
204 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
205 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
206 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
207 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 208 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
209 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
210 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 211
212 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 213 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 214
215 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
216 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
217 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
218 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
219 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
220
221 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
222 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
223 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
224 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
225 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
226 negative or unaligned and there is
227 no writeback allowed. This operand code
228 is only used to support the programmer-
229 friendly feature of using LDR/STR as the
230 the mnemonic name for LDUR/STUR instructions
231 wherever there is no ambiguity. */
3f06e550 232 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
a06ea964
NC		 233 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
234 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
235 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
236
237 AARCH64_OPND_SYSREG, /* System register operand. */
238 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
239 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
240 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
241 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
242 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
243 AARCH64_OPND_BARRIER, /* Barrier operand. */
244 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
245 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 246 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
f11ad6bc 247
98907a70
RS		 248 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
249 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
250 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
251 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
252 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
253 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 254 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
255 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
256 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
257 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
258 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
259 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
260 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
261 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
262 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
263 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
264 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
265 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
266 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
267 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
268 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
269 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
270 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
271 Bit 14 controls S/U choice. */
272 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
273 Bit 22 controls S/U choice. */
274 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
275 Bit 14 controls S/U choice. */
276 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
277 Bit 22 controls S/U choice. */
278 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
279 Bit 14 controls S/U choice. */
280 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
281 Bit 22 controls S/U choice. */
282 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
283 Bit 14 controls S/U choice. */
284 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
285 Bit 22 controls S/U choice. */
286 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
287 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
288 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
289 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
290 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
291 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
292 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 293 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
294 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 295 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
296 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
297 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
298 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
e950b345
RS		 299 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
300 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
301 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 302 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 303 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 304 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 305 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
306 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
307 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
308 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
309 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
310 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
311 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
312 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 313 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
314 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 315 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
316 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
317 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
318 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
319 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
320 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
321 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
322 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
323 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
324 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
325 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
326 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 327 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
328 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
329 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
330 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 331 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
332 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
333 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
334 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
335 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
336 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
337 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
338 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
339 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
340 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
a06ea964
NC		 341};
342
343/* Qualifier constrains an operand. It either specifies a variant of an
344 operand type or limits values available to an operand type.
345
346 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
347
348enum aarch64_opnd_qualifier
349{
350 /* Indicating no further qualification on an operand. */
351 AARCH64_OPND_QLF_NIL,
352
353 /* Qualifying an operand which is a general purpose (integer) register;
354 indicating the operand data size or a specific register. */
355 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
356 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
357 AARCH64_OPND_QLF_WSP, /* WSP. */
358 AARCH64_OPND_QLF_SP, /* SP. */
359
360 /* Qualifying an operand which is a floating-point register, a SIMD
361 vector element or a SIMD vector element list; indicating operand data
362 size or the size of each SIMD vector element in the case of a SIMD
363 vector element list.
364 These qualifiers are also used to qualify an address operand to
365 indicate the size of data element a load/store instruction is
366 accessing.
367 They are also used for the immediate shift operand in e.g. SSHR. Such
368 a use is only for the ease of operand encoding/decoding and qualifier
369 sequence matching; such a use should not be applied widely; use the value
370 constraint qualifiers for immediate operands wherever possible. */
371 AARCH64_OPND_QLF_S_B,
372 AARCH64_OPND_QLF_S_H,
373 AARCH64_OPND_QLF_S_S,
374 AARCH64_OPND_QLF_S_D,
375 AARCH64_OPND_QLF_S_Q,
376
377 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
378 register list; indicating register shape.
379 They are also used for the immediate shift operand in e.g. SSHR. Such
380 a use is only for the ease of operand encoding/decoding and qualifier
381 sequence matching; such a use should not be applied widely; use the value
382 constraint qualifiers for immediate operands wherever possible. */
383 AARCH64_OPND_QLF_V_8B,
384 AARCH64_OPND_QLF_V_16B,
3067d3b9 385 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 386 AARCH64_OPND_QLF_V_4H,
387 AARCH64_OPND_QLF_V_8H,
388 AARCH64_OPND_QLF_V_2S,
389 AARCH64_OPND_QLF_V_4S,
390 AARCH64_OPND_QLF_V_1D,
391 AARCH64_OPND_QLF_V_2D,
392 AARCH64_OPND_QLF_V_1Q,
393
d50c751e
RS		 394 AARCH64_OPND_QLF_P_Z,
395 AARCH64_OPND_QLF_P_M,
396
a06ea964 397 /* Constraint on value. */
a6a51754 398 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 399 AARCH64_OPND_QLF_imm_0_7,
400 AARCH64_OPND_QLF_imm_0_15,
401 AARCH64_OPND_QLF_imm_0_31,
402 AARCH64_OPND_QLF_imm_0_63,
403 AARCH64_OPND_QLF_imm_1_32,
404 AARCH64_OPND_QLF_imm_1_64,
405
406 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
407 or shift-ones. */
408 AARCH64_OPND_QLF_LSL,
409 AARCH64_OPND_QLF_MSL,
410
411 /* Special qualifier helping retrieve qualifier information during the
412 decoding time (currently not in use). */
413 AARCH64_OPND_QLF_RETRIEVE,
414};
415\f
416/* Instruction class. */
417
418enum aarch64_insn_class
419{
420 addsub_carry,
421 addsub_ext,
422 addsub_imm,
423 addsub_shift,
424 asimdall,
425 asimddiff,
426 asimdelem,
427 asimdext,
428 asimdimm,
429 asimdins,
430 asimdmisc,
431 asimdperm,
432 asimdsame,
433 asimdshf,
434 asimdtbl,
435 asisddiff,
436 asisdelem,
437 asisdlse,
438 asisdlsep,
439 asisdlso,
440 asisdlsop,
441 asisdmisc,
442 asisdone,
443 asisdpair,
444 asisdsame,
445 asisdshf,
446 bitfield,
447 branch_imm,
448 branch_reg,
449 compbranch,
450 condbranch,
451 condcmp_imm,
452 condcmp_reg,
453 condsel,
454 cryptoaes,
455 cryptosha2,
456 cryptosha3,
457 dp_1src,
458 dp_2src,
459 dp_3src,
460 exception,
461 extract,
462 float2fix,
463 float2int,
464 floatccmp,
465 floatcmp,
466 floatdp1,
467 floatdp2,
468 floatdp3,
469 floatimm,
470 floatsel,
471 ldst_immpost,
472 ldst_immpre,
473 ldst_imm9, /* immpost or immpre */
3f06e550 474 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 475 ldst_pos,
476 ldst_regoff,
477 ldst_unpriv,
478 ldst_unscaled,
479 ldstexcl,
480 ldstnapair_offs,
481 ldstpair_off,
482 ldstpair_indexed,
483 loadlit,
484 log_imm,
485 log_shift,
ee804238 486 lse_atomic,
a06ea964
NC		 487 movewide,
488 pcreladdr,
489 ic_system,
116b6019
RS		 490 sve_cpy,
491 sve_index,
492 sve_limm,
493 sve_misc,
494 sve_movprfx,
495 sve_pred_zm,
496 sve_shift_pred,
497 sve_shift_unpred,
498 sve_size_bhs,
499 sve_size_bhsd,
500 sve_size_hsd,
501 sve_size_sd,
a06ea964
NC		 502 testbranch,
503};
504
505/* Opcode enumerators. */
506
507enum aarch64_op
508{
509 OP_NIL,
510 OP_STRB_POS,
511 OP_LDRB_POS,
512 OP_LDRSB_POS,
513 OP_STRH_POS,
514 OP_LDRH_POS,
515 OP_LDRSH_POS,
516 OP_STR_POS,
517 OP_LDR_POS,
518 OP_STRF_POS,
519 OP_LDRF_POS,
520 OP_LDRSW_POS,
521 OP_PRFM_POS,
522
523 OP_STURB,
524 OP_LDURB,
525 OP_LDURSB,
526 OP_STURH,
527 OP_LDURH,
528 OP_LDURSH,
529 OP_STUR,
530 OP_LDUR,
531 OP_STURV,
532 OP_LDURV,
533 OP_LDURSW,
534 OP_PRFUM,
535
536 OP_LDR_LIT,
537 OP_LDRV_LIT,
538 OP_LDRSW_LIT,
539 OP_PRFM_LIT,
540
541 OP_ADD,
542 OP_B,
543 OP_BL,
544
545 OP_MOVN,
546 OP_MOVZ,
547 OP_MOVK,
548
549 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
550 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
551 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
552
553 OP_MOV_V, /* MOV alias for moving vector register. */
554
555 OP_ASR_IMM,
556 OP_LSR_IMM,
557 OP_LSL_IMM,
558
559 OP_BIC,
560
561 OP_UBFX,
562 OP_BFXIL,
563 OP_SBFX,
564 OP_SBFIZ,
565 OP_BFI,
d685192a 566 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 567 OP_UBFIZ,
568 OP_UXTB,
569 OP_UXTH,
570 OP_UXTW,
571
a06ea964
NC		 572 OP_CINC,
573 OP_CINV,
574 OP_CNEG,
575 OP_CSET,
576 OP_CSETM,
577
578 OP_FCVT,
579 OP_FCVTN,
580 OP_FCVTN2,
581 OP_FCVTL,
582 OP_FCVTL2,
583 OP_FCVTXN_S, /* Scalar version. */
584
585 OP_ROR_IMM,
586
e30181a5
YZ		 587 OP_SXTL,
588 OP_SXTL2,
589 OP_UXTL,
590 OP_UXTL2,
591
c0890d26
RS		 592 OP_MOV_P_P,
593 OP_MOV_Z_P_Z,
594 OP_MOV_Z_V,
595 OP_MOV_Z_Z,
596 OP_MOV_Z_Zi,
597 OP_MOVM_P_P_P,
598 OP_MOVS_P_P,
599 OP_MOVZS_P_P_P,
600 OP_MOVZ_P_P_P,
601 OP_NOTS_P_P_P_Z,
602 OP_NOT_P_P_P_Z,
603
c2c4ff8d
SN		 604 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
605
a06ea964
NC		 606 OP_TOTAL_NUM, /* Pseudo. */
607};
608
609/* Maximum number of operands an instruction can have. */
610#define AARCH64_MAX_OPND_NUM 6
611/* Maximum number of qualifier sequences an instruction can have. */
612#define AARCH64_MAX_QLF_SEQ_NUM 10
613/* Operand qualifier typedef; optimized for the size. */
614typedef unsigned char aarch64_opnd_qualifier_t;
615/* Operand qualifier sequence typedef. */
616typedef aarch64_opnd_qualifier_t \
617 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
618
619/* FIXME: improve the efficiency. */
620static inline bfd_boolean
621empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
622{
623 int i;
624 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
625 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
626 return FALSE;
627 return TRUE;
628}
629
630/* This structure holds information for a particular opcode. */
631
632struct aarch64_opcode
633{
634 /* The name of the mnemonic. */
635 const char *name;
636
637 /* The opcode itself. Those bits which will be filled in with
638 operands are zeroes. */
639 aarch64_insn opcode;
640
641 /* The opcode mask. This is used by the disassembler. This is a
642 mask containing ones indicating those bits which must match the
643 opcode field, and zeroes indicating those bits which need not
644 match (and are presumably filled in by operands). */
645 aarch64_insn mask;
646
647 /* Instruction class. */
648 enum aarch64_insn_class iclass;
649
650 /* Enumerator identifier. */
651 enum aarch64_op op;
652
653 /* Which architecture variant provides this instruction. */
654 const aarch64_feature_set *avariant;
655
656 /* An array of operand codes. Each code is an index into the
657 operand table. They appear in the order which the operands must
658 appear in assembly code, and are terminated by a zero. */
659 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
660
661 /* A list of operand qualifier code sequence. Each operand qualifier
662 code qualifies the corresponding operand code. Each operand
663 qualifier sequence specifies a valid opcode variant and related
664 constraint on operands. */
665 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
666
667 /* Flags providing information about this instruction */
668 uint32_t flags;
4bd13cde 669
0c608d6b
RS		 670 /* If nonzero, this operand and operand 0 are both registers and
671 are required to have the same register number. */
672 unsigned char tied_operand;
673
4bd13cde
NC		 674 /* If non-NULL, a function to verify that a given instruction is valid. */
675 bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
a06ea964
NC		 676};
677
678typedef struct aarch64_opcode aarch64_opcode;
679
680/* Table describing all the AArch64 opcodes. */
681extern aarch64_opcode aarch64_opcode_table[];
682
683/* Opcode flags. */
684#define F_ALIAS (1 << 0)
685#define F_HAS_ALIAS (1 << 1)
686/* Disassembly preference priority 1-3 (the larger the higher). If nothing
687 is specified, it is the priority 0 by default, i.e. the lowest priority. */
688#define F_P1 (1 << 2)
689#define F_P2 (2 << 2)
690#define F_P3 (3 << 2)
691/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
692#define F_COND (1 << 4)
693/* Instruction has the field of 'sf'. */
694#define F_SF (1 << 5)
695/* Instruction has the field of 'size:Q'. */
696#define F_SIZEQ (1 << 6)
697/* Floating-point instruction has the field of 'type'. */
698#define F_FPTYPE (1 << 7)
699/* AdvSIMD scalar instruction has the field of 'size'. */
700#define F_SSIZE (1 << 8)
701/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
702#define F_T (1 << 9)
703/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
704#define F_GPRSIZE_IN_Q (1 << 10)
705/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
706#define F_LDS_SIZE (1 << 11)
707/* Optional operand; assume maximum of 1 operand can be optional. */
708#define F_OPD0_OPT (1 << 12)
709#define F_OPD1_OPT (2 << 12)
710#define F_OPD2_OPT (3 << 12)
711#define F_OPD3_OPT (4 << 12)
712#define F_OPD4_OPT (5 << 12)
713/* Default value for the optional operand when omitted from the assembly. */
714#define F_DEFAULT(X) (((X) & 0x1f) << 15)
715/* Instruction that is an alias of another instruction needs to be
716 encoded/decoded by converting it to/from the real form, followed by
717 the encoding/decoding according to the rules of the real opcode.
718 This compares to the direct coding using the alias's information.
719 N.B. this flag requires F_ALIAS to be used together. */
720#define F_CONV (1 << 20)
721/* Use together with F_ALIAS to indicate an alias opcode is a programmer
722 friendly pseudo instruction available only in the assembly code (thus will
723 not show up in the disassembly). */
724#define F_PSEUDO (1 << 21)
725/* Instruction has miscellaneous encoding/decoding rules. */
726#define F_MISC (1 << 22)
727/* Instruction has the field of 'N'; used in conjunction with F_SF. */
728#define F_N (1 << 23)
729/* Opcode dependent field. */
730#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 731/* Instruction has the field of 'sz'. */
732#define F_LSE_SZ (1 << 27)
4989adac
RS		 733/* Require an exact qualifier match, even for NIL qualifiers. */
734#define F_STRICT (1ULL << 28)
735/* Next bit is 29. */
a06ea964
NC		 736
737static inline bfd_boolean
738alias_opcode_p (const aarch64_opcode *opcode)
739{
740 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
741}
742
743static inline bfd_boolean
744opcode_has_alias (const aarch64_opcode *opcode)
745{
746 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
747}
748
749/* Priority for disassembling preference. */
750static inline int
751opcode_priority (const aarch64_opcode *opcode)
752{
753 return (opcode->flags >> 2) & 0x3;
754}
755
756static inline bfd_boolean
757pseudo_opcode_p (const aarch64_opcode *opcode)
758{
759 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
760}
761
762static inline bfd_boolean
763optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
764{
765 return (((opcode->flags >> 12) & 0x7) == idx + 1)
766 ? TRUE : FALSE;
767}
768
769static inline aarch64_insn
770get_optional_operand_default_value (const aarch64_opcode *opcode)
771{
772 return (opcode->flags >> 15) & 0x1f;
773}
774
775static inline unsigned int
776get_opcode_dependent_value (const aarch64_opcode *opcode)
777{
778 return (opcode->flags >> 24) & 0x7;
779}
780
781static inline bfd_boolean
782opcode_has_special_coder (const aarch64_opcode *opcode)
783{
ee804238 784 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 785 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
786 : FALSE;
787}
788\f
789struct aarch64_name_value_pair
790{
791 const char * name;
792 aarch64_insn value;
793};
794
795extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 796extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
797extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 798extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 799
49eec193
YZ		 800typedef struct
801{
802 const char * name;
803 aarch64_insn value;
804 uint32_t flags;
805} aarch64_sys_reg;
806
807extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 808extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 809extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 810extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
811 const aarch64_sys_reg *);
812extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
813 const aarch64_sys_reg *);
49eec193 814
a06ea964
NC		 815typedef struct
816{
875880c6 817 const char *name;
a06ea964 818 uint32_t value;
ea2deeec 819 uint32_t flags ;
a06ea964
NC		 820} aarch64_sys_ins_reg;
821
ea2deeec 822extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 823extern bfd_boolean
824aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
825 const aarch64_sys_ins_reg *);
ea2deeec 826
a06ea964
NC		 827extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
828extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
829extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
830extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
831
832/* Shift/extending operator kinds.
833 N.B. order is important; keep aarch64_operand_modifiers synced. */
834enum aarch64_modifier_kind
835{
836 AARCH64_MOD_NONE,
837 AARCH64_MOD_MSL,
838 AARCH64_MOD_ROR,
839 AARCH64_MOD_ASR,
840 AARCH64_MOD_LSR,
841 AARCH64_MOD_LSL,
842 AARCH64_MOD_UXTB,
843 AARCH64_MOD_UXTH,
844 AARCH64_MOD_UXTW,
845 AARCH64_MOD_UXTX,
846 AARCH64_MOD_SXTB,
847 AARCH64_MOD_SXTH,
848 AARCH64_MOD_SXTW,
849 AARCH64_MOD_SXTX,
2442d846 850 AARCH64_MOD_MUL,
98907a70 851 AARCH64_MOD_MUL_VL,
a06ea964
NC		 852};
853
854bfd_boolean
855aarch64_extend_operator_p (enum aarch64_modifier_kind);
856
857enum aarch64_modifier_kind
858aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
859/* Condition. */
860
861typedef struct
862{
863 /* A list of names with the first one as the disassembly preference;
864 terminated by NULL if fewer than 3. */
bb7eff52 865 const char *names[4];
a06ea964
NC		 866 aarch64_insn value;
867} aarch64_cond;
868
869extern const aarch64_cond aarch64_conds[16];
870
871const aarch64_cond* get_cond_from_value (aarch64_insn value);
872const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
873\f
874/* Structure representing an operand. */
875
876struct aarch64_opnd_info
877{
878 enum aarch64_opnd type;
879 aarch64_opnd_qualifier_t qualifier;
880 int idx;
881
882 union
883 {
884 struct
885 {
886 unsigned regno;
887 } reg;
888 struct
889 {
dab26bf4
RS		 890 unsigned int regno;
891 int64_t index;
a06ea964
NC		 892 } reglane;
893 /* e.g. LVn. */
894 struct
895 {
896 unsigned first_regno : 5;
897 unsigned num_regs : 3;
898 /* 1 if it is a list of reg element. */
899 unsigned has_index : 1;
900 /* Lane index; valid only when has_index is 1. */
dab26bf4 901 int64_t index;
a06ea964
NC		 902 } reglist;
903 /* e.g. immediate or pc relative address offset. */
904 struct
905 {
906 int64_t value;
907 unsigned is_fp : 1;
908 } imm;
909 /* e.g. address in STR (register offset). */
910 struct
911 {
912 unsigned base_regno;
913 struct
914 {
915 union
916 {
917 int imm;
918 unsigned regno;
919 };
920 unsigned is_reg;
921 } offset;
922 unsigned pcrel : 1; /* PC-relative. */
923 unsigned writeback : 1;
924 unsigned preind : 1; /* Pre-indexed. */
925 unsigned postind : 1; /* Post-indexed. */
926 } addr;
927 const aarch64_cond *cond;
928 /* The encoding of the system register. */
929 aarch64_insn sysreg;
930 /* The encoding of the PSTATE field. */
931 aarch64_insn pstatefield;
932 const aarch64_sys_ins_reg *sysins_op;
933 const struct aarch64_name_value_pair *barrier;
9ed608f9 934 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 935 const struct aarch64_name_value_pair *prfop;
936 };
937
938 /* Operand shifter; in use when the operand is a register offset address,
939 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
940 struct
941 {
942 enum aarch64_modifier_kind kind;
a06ea964
NC		 943 unsigned operator_present: 1; /* Only valid during encoding. */
944 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
945 unsigned amount_present: 1;
2442d846 946 int64_t amount;
a06ea964
NC		 947 } shifter;
948
949 unsigned skip:1; /* Operand is not completed if there is a fixup needed
950 to be done on it. In some (but not all) of these
951 cases, we need to tell libopcodes to skip the
952 constraint checking and the encoding for this
953 operand, so that the libopcodes can pick up the
954 right opcode before the operand is fixed-up. This
955 flag should only be used during the
956 assembling/encoding. */
957 unsigned present:1; /* Whether this operand is present in the assembly
958 line; not used during the disassembly. */
959};
960
961typedef struct aarch64_opnd_info aarch64_opnd_info;
962
963/* Structure representing an instruction.
964
965 It is used during both the assembling and disassembling. The assembler
966 fills an aarch64_inst after a successful parsing and then passes it to the
967 encoding routine to do the encoding. During the disassembling, the
968 disassembler calls the decoding routine to decode a binary instruction; on a
969 successful return, such a structure will be filled with information of the
970 instruction; then the disassembler uses the information to print out the
971 instruction. */
972
973struct aarch64_inst
974{
975 /* The value of the binary instruction. */
976 aarch64_insn value;
977
978 /* Corresponding opcode entry. */
979 const aarch64_opcode *opcode;
980
981 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
982 const aarch64_cond *cond;
983
984 /* Operands information. */
985 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
986};
987
988typedef struct aarch64_inst aarch64_inst;
989\f
990/* Diagnosis related declaration and interface. */
991
992/* Operand error kind enumerators.
993
994 AARCH64_OPDE_RECOVERABLE
995 Less severe error found during the parsing, very possibly because that
996 GAS has picked up a wrong instruction template for the parsing.
997
998 AARCH64_OPDE_SYNTAX_ERROR
999 General syntax error; it can be either a user error, or simply because
1000 that GAS is trying a wrong instruction template.
1001
1002 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1003 Definitely a user syntax error.
1004
1005 AARCH64_OPDE_INVALID_VARIANT
1006 No syntax error, but the operands are not a valid combination, e.g.
1007 FMOV D0,S0
1008
0c608d6b
RS		 1009 AARCH64_OPDE_UNTIED_OPERAND
1010 The asm failed to use the same register for a destination operand
1011 and a tied source operand.
1012
a06ea964
NC		 1013 AARCH64_OPDE_OUT_OF_RANGE
1014 Error about some immediate value out of a valid range.
1015
1016 AARCH64_OPDE_UNALIGNED
1017 Error about some immediate value not properly aligned (i.e. not being a
1018 multiple times of a certain value).
1019
1020 AARCH64_OPDE_REG_LIST
1021 Error about the register list operand having unexpected number of
1022 registers.
1023
1024 AARCH64_OPDE_OTHER_ERROR
1025 Error of the highest severity and used for any severe issue that does not
1026 fall into any of the above categories.
1027
1028 The enumerators are only interesting to GAS. They are declared here (in
1029 libopcodes) because that some errors are detected (and then notified to GAS)
1030 by libopcodes (rather than by GAS solely).
1031
1032 The first three errors are only deteced by GAS while the
1033 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1034 only libopcodes has the information about the valid variants of each
1035 instruction.
1036
1037 The enumerators have an increasing severity. This is helpful when there are
1038 multiple instruction templates available for a given mnemonic name (e.g.
1039 FMOV); this mechanism will help choose the most suitable template from which
1040 the generated diagnostics can most closely describe the issues, if any. */
1041
1042enum aarch64_operand_error_kind
1043{
1044 AARCH64_OPDE_NIL,
1045 AARCH64_OPDE_RECOVERABLE,
1046 AARCH64_OPDE_SYNTAX_ERROR,
1047 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1048 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1049 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1050 AARCH64_OPDE_OUT_OF_RANGE,
1051 AARCH64_OPDE_UNALIGNED,
1052 AARCH64_OPDE_REG_LIST,
1053 AARCH64_OPDE_OTHER_ERROR
1054};
1055
1056/* N.B. GAS assumes that this structure work well with shallow copy. */
1057struct aarch64_operand_error
1058{
1059 enum aarch64_operand_error_kind kind;
1060 int index;
1061 const char *error;
1062 int data[3]; /* Some data for extra information. */
1063};
1064
1065typedef struct aarch64_operand_error aarch64_operand_error;
1066
1067/* Encoding entrypoint. */
1068
1069extern int
1070aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1071 aarch64_insn *, aarch64_opnd_qualifier_t *,
1072 aarch64_operand_error *);
1073
1074extern const aarch64_opcode *
1075aarch64_replace_opcode (struct aarch64_inst *,
1076 const aarch64_opcode *);
1077
1078/* Given the opcode enumerator OP, return the pointer to the corresponding
1079 opcode entry. */
1080
1081extern const aarch64_opcode *
1082aarch64_get_opcode (enum aarch64_op);
1083
1084/* Generate the string representation of an operand. */
1085extern void
1086aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1087 const aarch64_opnd_info *, int, int *, bfd_vma *);
1088
1089/* Miscellaneous interface. */
1090
1091extern int
1092aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1093
1094extern aarch64_opnd_qualifier_t
1095aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1096 const aarch64_opnd_qualifier_t, int);
1097
1098extern int
1099aarch64_num_of_operands (const aarch64_opcode *);
1100
1101extern int
1102aarch64_stack_pointer_p (const aarch64_opnd_info *);
1103
e141d84e
YQ		 1104extern int
1105aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1106
36f4aab1 1107extern int
43cdf5ae 1108aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
36f4aab1 1109
a06ea964
NC		 1110/* Given an operand qualifier, return the expected data element size
1111 of a qualified operand. */
1112extern unsigned char
1113aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1114
1115extern enum aarch64_operand_class
1116aarch64_get_operand_class (enum aarch64_opnd);
1117
1118extern const char *
1119aarch64_get_operand_name (enum aarch64_opnd);
1120
1121extern const char *
1122aarch64_get_operand_desc (enum aarch64_opnd);
1123
e950b345
RS		 1124extern bfd_boolean
1125aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1126
a06ea964
NC		 1127#ifdef DEBUG_AARCH64
1128extern int debug_dump;
1129
1130extern void
1131aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1132
1133#define DEBUG_TRACE(M, ...) \
1134 { \
1135 if (debug_dump) \
1136 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1137 }
1138
1139#define DEBUG_TRACE_IF(C, M, ...) \
1140 { \
1141 if (debug_dump && (C)) \
1142 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1143 }
1144#else /* !DEBUG_AARCH64 */
1145#define DEBUG_TRACE(M, ...) ;
1146#define DEBUG_TRACE_IF(C, M, ...) ;
1147#endif /* DEBUG_AARCH64 */
1148
245d2e3f
RS		 1149extern const char *const aarch64_sve_pattern_array[32];
1150extern const char *const aarch64_sve_prfop_array[16];
1151
d3e12b29
YQ		 1152#ifdef __cplusplus
1153}
1154#endif
1155
a06ea964 1156#endif /* OPCODE_AARCH64_H */
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