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[thirdparty/binutils-gdb.git] / include / opcode / aarch64.h
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a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
b3adc24a 3 Copyright (C) 2009-2020 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
359157df
AC		 40#define AARCH64_FEATURE_V8 (1ULL << 0) /* All processors. */
41#define AARCH64_FEATURE_V8_6 (1ULL << 1) /* ARMv8.6 processors. */
42#define AARCH64_FEATURE_BFLOAT16 (1ULL << 2) /* Bfloat16 insns. */
43#define AARCH64_FEATURE_SVE2 (1ULL << 4) /* SVE2 instructions. */
44#define AARCH64_FEATURE_V8_2 (1ULL << 5) /* ARMv8.2 processors. */
45#define AARCH64_FEATURE_V8_3 (1ULL << 6) /* ARMv8.3 processors. */
46#define AARCH64_FEATURE_SVE2_AES (1ULL << 7)
47#define AARCH64_FEATURE_SVE2_BITPERM (1ULL << 8)
48#define AARCH64_FEATURE_SVE2_SM4 (1ULL << 9)
49#define AARCH64_FEATURE_SVE2_SHA3 (1ULL << 10)
50#define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */
51#define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */
52#define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */
53#define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */
54#define AARCH64_FEATURE_LSE (1ULL << 20) /* LSE instructions. */
55#define AARCH64_FEATURE_PAN (1ULL << 21) /* PAN instructions. */
56#define AARCH64_FEATURE_LOR (1ULL << 22) /* LOR instructions. */
57#define AARCH64_FEATURE_RDMA (1ULL << 23) /* v8.1 SIMD instructions. */
58#define AARCH64_FEATURE_V8_1 (1ULL << 24) /* v8.1 features. */
59#define AARCH64_FEATURE_F16 (1ULL << 25) /* v8.2 FP16 instructions. */
60#define AARCH64_FEATURE_RAS (1ULL << 26) /* RAS Extensions. */
61#define AARCH64_FEATURE_PROFILE (1ULL << 27) /* Statistical Profiling. */
62#define AARCH64_FEATURE_SVE (1ULL << 28) /* SVE instructions. */
63#define AARCH64_FEATURE_RCPC (1ULL << 29) /* RCPC instructions. */
64#define AARCH64_FEATURE_COMPNUM (1ULL << 30) /* Complex # instructions. */
65#define AARCH64_FEATURE_DOTPROD (1ULL << 31) /* Dot Product instructions. */
66#define AARCH64_FEATURE_SM4 (1ULL << 32) /* SM3 & SM4 instructions. */
67#define AARCH64_FEATURE_SHA2 (1ULL << 33) /* SHA2 instructions. */
68#define AARCH64_FEATURE_SHA3 (1ULL << 34) /* SHA3 instructions. */
69#define AARCH64_FEATURE_AES (1ULL << 35) /* AES instructions. */
70#define AARCH64_FEATURE_F16_FML (1ULL << 36) /* v8.2 FP16FML ins. */
71#define AARCH64_FEATURE_V8_5 (1ULL << 37) /* ARMv8.5 processors. */
72#define AARCH64_FEATURE_FLAGMANIP (1ULL << 38) /* Flag Manipulation insns. */
73#define AARCH64_FEATURE_FRINTTS (1ULL << 39) /* FRINT[32,64][Z,X] insns. */
74#define AARCH64_FEATURE_SB (1ULL << 40) /* SB instruction. */
75#define AARCH64_FEATURE_PREDRES (1ULL << 41) /* Execution and Data Prediction Restriction instructions. */
76#define AARCH64_FEATURE_CVADP (1ULL << 42) /* DC CVADP. */
77#define AARCH64_FEATURE_RNG (1ULL << 43) /* Random Number instructions. */
78#define AARCH64_FEATURE_BTI (1ULL << 44) /* BTI instructions. */
79#define AARCH64_FEATURE_SCXTNUM (1ULL << 45) /* SCXTNUM_ELx. */
80#define AARCH64_FEATURE_ID_PFR2 (1ULL << 46) /* ID_PFR2 instructions. */
81#define AARCH64_FEATURE_SSBS (1ULL << 47) /* SSBS mechanism enabled. */
82#define AARCH64_FEATURE_MEMTAG (1ULL << 48) /* Memory Tagging Extension. */
83#define AARCH64_FEATURE_TME (1ULL << 49) /* Transactional Memory Extension. */
84#define AARCH64_FEATURE_I8MM (1ULL << 52) /* Matrix Multiply instructions. */
85#define AARCH64_FEATURE_F32MM (1ULL << 53)
86#define AARCH64_FEATURE_F64MM (1ULL << 54)
7ce2460a 87
2dc4b12f
JB		 88/* Crypto instructions are the combination of AES and SHA2. */
89#define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
90
a06ea964
NC		 91/* Architectures are the sum of the base and extensions. */
92#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
93 AARCH64_FEATURE_FP \
94 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 95#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
96 AARCH64_FEATURE_CRC \
250aafa4 97 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 98 | AARCH64_FEATURE_LSE \
99 | AARCH64_FEATURE_PAN \
100 | AARCH64_FEATURE_LOR \
101 | AARCH64_FEATURE_RDMA)
1924ff75 102#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 103 AARCH64_FEATURE_V8_2 \
1924ff75
SN		 104 | AARCH64_FEATURE_RAS)
105#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 106 AARCH64_FEATURE_V8_3 \
f482d304
RS		 107 | AARCH64_FEATURE_RCPC \
108 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c 109#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
981b557a 110 AARCH64_FEATURE_V8_4 \
d0f7791c
TC		 111 | AARCH64_FEATURE_DOTPROD \
112 | AARCH64_FEATURE_F16_FML)
70d56181 113#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
13c60ad7
SD		 114 AARCH64_FEATURE_V8_5 \
115 | AARCH64_FEATURE_FLAGMANIP \
68dfbb92 116 | AARCH64_FEATURE_FRINTTS \
2ac435d4 117 | AARCH64_FEATURE_SB \
3fd229a4 118 | AARCH64_FEATURE_PREDRES \
ff605452 119 | AARCH64_FEATURE_CVADP \
a97330e7
SD		 120 | AARCH64_FEATURE_BTI \
121 | AARCH64_FEATURE_SCXTNUM \
104fefee
SD		 122 | AARCH64_FEATURE_ID_PFR2 \
123 | AARCH64_FEATURE_SSBS)
8ae2d3d9 124#define AARCH64_ARCH_V8_6 AARCH64_FEATURE (AARCH64_ARCH_V8_5, \
df678013 125 AARCH64_FEATURE_V8_6 \
8382113f
MM		 126 | AARCH64_FEATURE_BFLOAT16 \
127 | AARCH64_FEATURE_I8MM)
88f0ea34 128
a06ea964
NC		 129#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
130#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
131
132/* CPU-specific features. */
21b81e67 133typedef unsigned long long aarch64_feature_set;
a06ea964 134
93d8990c
SN		 135#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
136 ((~(CPU) & (FEAT)) == 0)
137
138#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 139 (((CPU) & (FEAT)) != 0)
140
93d8990c
SN		 141#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
142 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
143
a06ea964
NC		 144#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
145 do \
146 { \
147 (TARG) = (F1) | (F2); \
148 } \
149 while (0)
150
151#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
152 do \
153 { \
154 (TARG) = (F1) &~ (F2); \
155 } \
156 while (0)
157
158#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
159
a06ea964
NC		 160enum aarch64_operand_class
161{
162 AARCH64_OPND_CLASS_NIL,
163 AARCH64_OPND_CLASS_INT_REG,
164 AARCH64_OPND_CLASS_MODIFIED_REG,
165 AARCH64_OPND_CLASS_FP_REG,
166 AARCH64_OPND_CLASS_SIMD_REG,
167 AARCH64_OPND_CLASS_SIMD_ELEMENT,
168 AARCH64_OPND_CLASS_SISD_REG,
169 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 170 AARCH64_OPND_CLASS_SVE_REG,
171 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 172 AARCH64_OPND_CLASS_ADDRESS,
173 AARCH64_OPND_CLASS_IMMEDIATE,
174 AARCH64_OPND_CLASS_SYSTEM,
68a64283 175 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 176};
177
178/* Operand code that helps both parsing and coding.
179 Keep AARCH64_OPERANDS synced. */
180
181enum aarch64_opnd
182{
183 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
184
185 AARCH64_OPND_Rd, /* Integer register as destination. */
186 AARCH64_OPND_Rn, /* Integer register as source. */
187 AARCH64_OPND_Rm, /* Integer register as source. */
188 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
189 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
bd7ceb8d 190 AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */
a06ea964
NC		 191 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
192 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
193 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
194
195 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
196 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 197 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 198 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 199 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
200 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
201
202 AARCH64_OPND_Fd, /* Floating-point Fd. */
203 AARCH64_OPND_Fn, /* Floating-point Fn. */
204 AARCH64_OPND_Fm, /* Floating-point Fm. */
205 AARCH64_OPND_Fa, /* Floating-point Fa. */
206 AARCH64_OPND_Ft, /* Floating-point Ft. */
207 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
208
209 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
210 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
211 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
212
f42f1a1d 213 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
a06ea964
NC		 214 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
215 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
216 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
217 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
218 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
219 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
220 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
221 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
369c9167
TC		 222 AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
223 qualifier is S_H. */
a06ea964
NC		 224 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
225 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
226 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
227 structure to all lanes. */
228 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
229
a6a51754
RL		 230 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
231 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 232
233 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
f42f1a1d 234 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
a06ea964
NC		 235 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
236 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
237 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
238 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
239 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
240 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
241 (no encoding). */
242 AARCH64_OPND_IMM0, /* Immediate for #0. */
243 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
244 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
245 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
246 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
247 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
248 AARCH64_OPND_IMM, /* Immediate. */
f42f1a1d 249 AARCH64_OPND_IMM_2, /* Immediate. */
a06ea964
NC		 250 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
251 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
252 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
193614f2 253 AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */
a06ea964 254 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
193614f2 255 AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */
a06ea964
NC		 256 AARCH64_OPND_BIT_NUM, /* Immediate. */
257 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
09c1e68a 258 AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */
a06ea964 259 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 260 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 261 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
262 each condition flag. */
263
264 AARCH64_OPND_LIMM, /* Logical Immediate. */
265 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
266 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
267 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
268 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 269 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
270 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
271 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 272
273 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 274 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 275
276 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
277 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
278 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
279 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
280 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
281
282 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
283 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
284 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
285 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
286 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
287 negative or unaligned and there is
288 no writeback allowed. This operand code
289 is only used to support the programmer-
290 friendly feature of using LDR/STR as the
291 the mnemonic name for LDUR/STUR instructions
292 wherever there is no ambiguity. */
3f06e550 293 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
fb3265b3
SD		 294 AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of
295 16) immediate. */
a06ea964 296 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
fb3265b3
SD		 297 AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of
298 16) immediate. */
a06ea964 299 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
f42f1a1d 300 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
a06ea964
NC		 301 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
302
303 AARCH64_OPND_SYSREG, /* System register operand. */
304 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
305 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
306 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
307 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
308 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
2ac435d4 309 AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
a06ea964
NC		 310 AARCH64_OPND_BARRIER, /* Barrier operand. */
311 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
312 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 313 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
ff605452 314 AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
f11ad6bc 315
582e12bf 316 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
8382113f 317 AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn|SP>, #<simm4>*32]. */
98907a70
RS		 318 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
319 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
320 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
321 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
322 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
323 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 324 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
325 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
326 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
327 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
c8d59609 328 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
4df068de
RS		 329 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
330 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
331 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
332 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
333 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
334 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
335 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
336 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
c469c864 337 AARCH64_OPND_SVE_ADDR_ZX, /* SVE [Zn.<T>{, <Xm>}]. */
4df068de
RS		 338 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
339 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
340 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
341 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
342 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
343 Bit 14 controls S/U choice. */
344 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
345 Bit 22 controls S/U choice. */
346 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
347 Bit 14 controls S/U choice. */
348 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
349 Bit 22 controls S/U choice. */
350 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
351 Bit 14 controls S/U choice. */
352 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
353 Bit 22 controls S/U choice. */
354 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
355 Bit 14 controls S/U choice. */
356 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
357 Bit 22 controls S/U choice. */
358 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
359 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
360 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
361 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
362 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
363 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
364 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 365 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
366 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 367 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
368 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
369 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
370 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS		 371 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
372 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
adccc507 373 AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */
e950b345
RS		 374 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
375 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
376 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 377 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 378 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 379 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 380 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
381 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
382 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
383 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
384 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
385 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
386 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
387 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 388 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
389 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 390 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
391 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
28ed815a 392 AARCH64_OPND_SVE_SHLIMM_UNPRED_22, /* SVE 3 bit shift left unpred. */
e950b345
RS		 393 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
394 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
3c17238b 395 AARCH64_OPND_SVE_SHRIMM_UNPRED_22, /* SVE 3 bit shift right unpred. */
e950b345
RS		 396 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
397 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
398 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
399 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
400 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
401 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
402 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
403 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 404 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
405 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
406 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
407 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 408 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
409 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
410 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
411 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
412 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS		 413 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
414 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
116adc27 415 AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */
31e36ab3 416 AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */
582e12bf 417 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS		 418 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
419 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
420 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
421 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
422 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
b83b4b13 423 AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
f42f1a1d 424 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
a06ea964
NC		 425};
426
427/* Qualifier constrains an operand. It either specifies a variant of an
428 operand type or limits values available to an operand type.
429
430 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
431
432enum aarch64_opnd_qualifier
433{
434 /* Indicating no further qualification on an operand. */
435 AARCH64_OPND_QLF_NIL,
436
437 /* Qualifying an operand which is a general purpose (integer) register;
438 indicating the operand data size or a specific register. */
439 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
440 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
441 AARCH64_OPND_QLF_WSP, /* WSP. */
442 AARCH64_OPND_QLF_SP, /* SP. */
443
444 /* Qualifying an operand which is a floating-point register, a SIMD
445 vector element or a SIMD vector element list; indicating operand data
446 size or the size of each SIMD vector element in the case of a SIMD
447 vector element list.
448 These qualifiers are also used to qualify an address operand to
449 indicate the size of data element a load/store instruction is
450 accessing.
451 They are also used for the immediate shift operand in e.g. SSHR. Such
452 a use is only for the ease of operand encoding/decoding and qualifier
453 sequence matching; such a use should not be applied widely; use the value
454 constraint qualifiers for immediate operands wherever possible. */
455 AARCH64_OPND_QLF_S_B,
456 AARCH64_OPND_QLF_S_H,
457 AARCH64_OPND_QLF_S_S,
458 AARCH64_OPND_QLF_S_D,
459 AARCH64_OPND_QLF_S_Q,
df678013
MM		 460 /* These type qualifiers have a special meaning in that they mean 4 x 1 byte
461 or 2 x 2 byte are selected by the instruction. Other than that they have
462 no difference with AARCH64_OPND_QLF_S_B in encoding. They are here purely
463 for syntactical reasons and is an exception from normal AArch64
464 disassembly scheme. */
00c2093f 465 AARCH64_OPND_QLF_S_4B,
df678013 466 AARCH64_OPND_QLF_S_2H,
a06ea964
NC		 467
468 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
469 register list; indicating register shape.
470 They are also used for the immediate shift operand in e.g. SSHR. Such
471 a use is only for the ease of operand encoding/decoding and qualifier
472 sequence matching; such a use should not be applied widely; use the value
473 constraint qualifiers for immediate operands wherever possible. */
a3b3345a 474 AARCH64_OPND_QLF_V_4B,
a06ea964
NC		 475 AARCH64_OPND_QLF_V_8B,
476 AARCH64_OPND_QLF_V_16B,
3067d3b9 477 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 478 AARCH64_OPND_QLF_V_4H,
479 AARCH64_OPND_QLF_V_8H,
480 AARCH64_OPND_QLF_V_2S,
481 AARCH64_OPND_QLF_V_4S,
482 AARCH64_OPND_QLF_V_1D,
483 AARCH64_OPND_QLF_V_2D,
484 AARCH64_OPND_QLF_V_1Q,
485
d50c751e
RS		 486 AARCH64_OPND_QLF_P_Z,
487 AARCH64_OPND_QLF_P_M,
fb3265b3
SD		 488
489 /* Used in scaled signed immediate that are scaled by a Tag granule
490 like in stg, st2g, etc. */
491 AARCH64_OPND_QLF_imm_tag,
d50c751e 492
a06ea964 493 /* Constraint on value. */
a6a51754 494 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 495 AARCH64_OPND_QLF_imm_0_7,
496 AARCH64_OPND_QLF_imm_0_15,
497 AARCH64_OPND_QLF_imm_0_31,
498 AARCH64_OPND_QLF_imm_0_63,
499 AARCH64_OPND_QLF_imm_1_32,
500 AARCH64_OPND_QLF_imm_1_64,
501
502 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
503 or shift-ones. */
504 AARCH64_OPND_QLF_LSL,
505 AARCH64_OPND_QLF_MSL,
506
507 /* Special qualifier helping retrieve qualifier information during the
508 decoding time (currently not in use). */
509 AARCH64_OPND_QLF_RETRIEVE,
510};
511\f
512/* Instruction class. */
513
514enum aarch64_insn_class
515{
8382113f 516 aarch64_misc,
a06ea964
NC		 517 addsub_carry,
518 addsub_ext,
519 addsub_imm,
520 addsub_shift,
521 asimdall,
522 asimddiff,
523 asimdelem,
524 asimdext,
525 asimdimm,
526 asimdins,
527 asimdmisc,
528 asimdperm,
529 asimdsame,
530 asimdshf,
531 asimdtbl,
532 asisddiff,
533 asisdelem,
534 asisdlse,
535 asisdlsep,
536 asisdlso,
537 asisdlsop,
538 asisdmisc,
539 asisdone,
540 asisdpair,
541 asisdsame,
542 asisdshf,
543 bitfield,
544 branch_imm,
545 branch_reg,
546 compbranch,
547 condbranch,
548 condcmp_imm,
549 condcmp_reg,
550 condsel,
551 cryptoaes,
552 cryptosha2,
553 cryptosha3,
554 dp_1src,
555 dp_2src,
556 dp_3src,
557 exception,
558 extract,
559 float2fix,
560 float2int,
561 floatccmp,
562 floatcmp,
563 floatdp1,
564 floatdp2,
565 floatdp3,
566 floatimm,
567 floatsel,
568 ldst_immpost,
569 ldst_immpre,
570 ldst_imm9, /* immpost or immpre */
3f06e550 571 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 572 ldst_pos,
573 ldst_regoff,
574 ldst_unpriv,
575 ldst_unscaled,
576 ldstexcl,
577 ldstnapair_offs,
578 ldstpair_off,
579 ldstpair_indexed,
580 loadlit,
581 log_imm,
582 log_shift,
ee804238 583 lse_atomic,
a06ea964
NC		 584 movewide,
585 pcreladdr,
586 ic_system,
116b6019
RS		 587 sve_cpy,
588 sve_index,
589 sve_limm,
590 sve_misc,
591 sve_movprfx,
592 sve_pred_zm,
593 sve_shift_pred,
594 sve_shift_unpred,
595 sve_size_bhs,
596 sve_size_bhsd,
597 sve_size_hsd,
3bd82c86 598 sve_size_hsd2,
116b6019 599 sve_size_sd,
3c705960 600 sve_size_bh,
0a57e14f 601 sve_size_sd2,
41be57ca 602 sve_size_13,
3c17238b 603 sve_shift_tsz_hsd,
1be5f94f 604 sve_shift_tsz_bhsd,
fd1dc4a0 605 sve_size_tsz_bhs,
a06ea964 606 testbranch,
f42f1a1d
TC		 607 cryptosm3,
608 cryptosm4,
65a55fbb 609 dotproduct,
df678013 610 bfloat16,
a06ea964
NC		 611};
612
613/* Opcode enumerators. */
614
615enum aarch64_op
616{
617 OP_NIL,
618 OP_STRB_POS,
619 OP_LDRB_POS,
620 OP_LDRSB_POS,
621 OP_STRH_POS,
622 OP_LDRH_POS,
623 OP_LDRSH_POS,
624 OP_STR_POS,
625 OP_LDR_POS,
626 OP_STRF_POS,
627 OP_LDRF_POS,
628 OP_LDRSW_POS,
629 OP_PRFM_POS,
630
631 OP_STURB,
632 OP_LDURB,
633 OP_LDURSB,
634 OP_STURH,
635 OP_LDURH,
636 OP_LDURSH,
637 OP_STUR,
638 OP_LDUR,
639 OP_STURV,
640 OP_LDURV,
641 OP_LDURSW,
642 OP_PRFUM,
643
644 OP_LDR_LIT,
645 OP_LDRV_LIT,
646 OP_LDRSW_LIT,
647 OP_PRFM_LIT,
648
649 OP_ADD,
650 OP_B,
651 OP_BL,
652
653 OP_MOVN,
654 OP_MOVZ,
655 OP_MOVK,
656
657 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
658 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
659 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
660
661 OP_MOV_V, /* MOV alias for moving vector register. */
662
663 OP_ASR_IMM,
664 OP_LSR_IMM,
665 OP_LSL_IMM,
666
667 OP_BIC,
668
669 OP_UBFX,
670 OP_BFXIL,
671 OP_SBFX,
672 OP_SBFIZ,
673 OP_BFI,
d685192a 674 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 675 OP_UBFIZ,
676 OP_UXTB,
677 OP_UXTH,
678 OP_UXTW,
679
a06ea964
NC		 680 OP_CINC,
681 OP_CINV,
682 OP_CNEG,
683 OP_CSET,
684 OP_CSETM,
685
686 OP_FCVT,
687 OP_FCVTN,
688 OP_FCVTN2,
689 OP_FCVTL,
690 OP_FCVTL2,
691 OP_FCVTXN_S, /* Scalar version. */
692
693 OP_ROR_IMM,
694
e30181a5
YZ		 695 OP_SXTL,
696 OP_SXTL2,
697 OP_UXTL,
698 OP_UXTL2,
699
c0890d26
RS		 700 OP_MOV_P_P,
701 OP_MOV_Z_P_Z,
702 OP_MOV_Z_V,
703 OP_MOV_Z_Z,
704 OP_MOV_Z_Zi,
705 OP_MOVM_P_P_P,
706 OP_MOVS_P_P,
707 OP_MOVZS_P_P_P,
708 OP_MOVZ_P_P_P,
709 OP_NOTS_P_P_P_Z,
710 OP_NOT_P_P_P_Z,
711
c2c4ff8d
SN		 712 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
713
a06ea964
NC		 714 OP_TOTAL_NUM, /* Pseudo. */
715};
716
1d482394
TC		 717/* Error types. */
718enum err_type
719{
720 ERR_OK,
721 ERR_UND,
722 ERR_UNP,
723 ERR_NYI,
a68f4cd2 724 ERR_VFI,
1d482394
TC		 725 ERR_NR_ENTRIES
726};
727
a06ea964
NC		 728/* Maximum number of operands an instruction can have. */
729#define AARCH64_MAX_OPND_NUM 6
730/* Maximum number of qualifier sequences an instruction can have. */
731#define AARCH64_MAX_QLF_SEQ_NUM 10
732/* Operand qualifier typedef; optimized for the size. */
733typedef unsigned char aarch64_opnd_qualifier_t;
734/* Operand qualifier sequence typedef. */
735typedef aarch64_opnd_qualifier_t \
736 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
737
738/* FIXME: improve the efficiency. */
739static inline bfd_boolean
740empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
741{
742 int i;
743 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
744 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
745 return FALSE;
746 return TRUE;
747}
748
7e84b55d
TC		 749/* Forward declare error reporting type. */
750typedef struct aarch64_operand_error aarch64_operand_error;
751/* Forward declare instruction sequence type. */
752typedef struct aarch64_instr_sequence aarch64_instr_sequence;
753/* Forward declare instruction definition. */
754typedef struct aarch64_inst aarch64_inst;
755
a06ea964
NC		 756/* This structure holds information for a particular opcode. */
757
758struct aarch64_opcode
759{
760 /* The name of the mnemonic. */
761 const char *name;
762
763 /* The opcode itself. Those bits which will be filled in with
764 operands are zeroes. */
765 aarch64_insn opcode;
766
767 /* The opcode mask. This is used by the disassembler. This is a
768 mask containing ones indicating those bits which must match the
769 opcode field, and zeroes indicating those bits which need not
770 match (and are presumably filled in by operands). */
771 aarch64_insn mask;
772
773 /* Instruction class. */
774 enum aarch64_insn_class iclass;
775
776 /* Enumerator identifier. */
777 enum aarch64_op op;
778
779 /* Which architecture variant provides this instruction. */
780 const aarch64_feature_set *avariant;
781
782 /* An array of operand codes. Each code is an index into the
783 operand table. They appear in the order which the operands must
784 appear in assembly code, and are terminated by a zero. */
785 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
786
787 /* A list of operand qualifier code sequence. Each operand qualifier
788 code qualifies the corresponding operand code. Each operand
789 qualifier sequence specifies a valid opcode variant and related
790 constraint on operands. */
791 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
792
793 /* Flags providing information about this instruction */
eae424ae
TC		 794 uint64_t flags;
795
796 /* Extra constraints on the instruction that the verifier checks. */
797 uint32_t constraints;
4bd13cde 798
0c608d6b
RS		 799 /* If nonzero, this operand and operand 0 are both registers and
800 are required to have the same register number. */
801 unsigned char tied_operand;
802
4bd13cde 803 /* If non-NULL, a function to verify that a given instruction is valid. */
755b748f
TC		 804 enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
805 bfd_vma, bfd_boolean, aarch64_operand_error *,
806 struct aarch64_instr_sequence *);
a06ea964
NC		 807};
808
809typedef struct aarch64_opcode aarch64_opcode;
810
811/* Table describing all the AArch64 opcodes. */
812extern aarch64_opcode aarch64_opcode_table[];
813
814/* Opcode flags. */
815#define F_ALIAS (1 << 0)
816#define F_HAS_ALIAS (1 << 1)
817/* Disassembly preference priority 1-3 (the larger the higher). If nothing
818 is specified, it is the priority 0 by default, i.e. the lowest priority. */
819#define F_P1 (1 << 2)
820#define F_P2 (2 << 2)
821#define F_P3 (3 << 2)
822/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
823#define F_COND (1 << 4)
824/* Instruction has the field of 'sf'. */
825#define F_SF (1 << 5)
826/* Instruction has the field of 'size:Q'. */
827#define F_SIZEQ (1 << 6)
828/* Floating-point instruction has the field of 'type'. */
829#define F_FPTYPE (1 << 7)
830/* AdvSIMD scalar instruction has the field of 'size'. */
831#define F_SSIZE (1 << 8)
832/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
833#define F_T (1 << 9)
834/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
835#define F_GPRSIZE_IN_Q (1 << 10)
836/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
837#define F_LDS_SIZE (1 << 11)
838/* Optional operand; assume maximum of 1 operand can be optional. */
839#define F_OPD0_OPT (1 << 12)
840#define F_OPD1_OPT (2 << 12)
841#define F_OPD2_OPT (3 << 12)
842#define F_OPD3_OPT (4 << 12)
843#define F_OPD4_OPT (5 << 12)
844/* Default value for the optional operand when omitted from the assembly. */
845#define F_DEFAULT(X) (((X) & 0x1f) << 15)
846/* Instruction that is an alias of another instruction needs to be
847 encoded/decoded by converting it to/from the real form, followed by
848 the encoding/decoding according to the rules of the real opcode.
849 This compares to the direct coding using the alias's information.
850 N.B. this flag requires F_ALIAS to be used together. */
851#define F_CONV (1 << 20)
852/* Use together with F_ALIAS to indicate an alias opcode is a programmer
853 friendly pseudo instruction available only in the assembly code (thus will
854 not show up in the disassembly). */
855#define F_PSEUDO (1 << 21)
856/* Instruction has miscellaneous encoding/decoding rules. */
857#define F_MISC (1 << 22)
858/* Instruction has the field of 'N'; used in conjunction with F_SF. */
859#define F_N (1 << 23)
860/* Opcode dependent field. */
861#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 862/* Instruction has the field of 'sz'. */
863#define F_LSE_SZ (1 << 27)
4989adac
RS		 864/* Require an exact qualifier match, even for NIL qualifiers. */
865#define F_STRICT (1ULL << 28)
f9830ec1
TC		 866/* This system instruction is used to read system registers. */
867#define F_SYS_READ (1ULL << 29)
868/* This system instruction is used to write system registers. */
869#define F_SYS_WRITE (1ULL << 30)
eae424ae
TC		 870/* This instruction has an extra constraint on it that imposes a requirement on
871 subsequent instructions. */
872#define F_SCAN (1ULL << 31)
873/* Next bit is 32. */
874
875/* Instruction constraints. */
876/* This instruction has a predication constraint on the instruction at PC+4. */
877#define C_SCAN_MOVPRFX (1U << 0)
878/* This instruction's operation width is determined by the operand with the
879 largest element size. */
880#define C_MAX_ELEM (1U << 1)
881/* Next bit is 2. */
a06ea964
NC		 882
883static inline bfd_boolean
884alias_opcode_p (const aarch64_opcode *opcode)
885{
886 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
887}
888
889static inline bfd_boolean
890opcode_has_alias (const aarch64_opcode *opcode)
891{
892 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
893}
894
895/* Priority for disassembling preference. */
896static inline int
897opcode_priority (const aarch64_opcode *opcode)
898{
899 return (opcode->flags >> 2) & 0x3;
900}
901
902static inline bfd_boolean
903pseudo_opcode_p (const aarch64_opcode *opcode)
904{
905 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
906}
907
908static inline bfd_boolean
909optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
910{
911 return (((opcode->flags >> 12) & 0x7) == idx + 1)
912 ? TRUE : FALSE;
913}
914
915static inline aarch64_insn
916get_optional_operand_default_value (const aarch64_opcode *opcode)
917{
918 return (opcode->flags >> 15) & 0x1f;
919}
920
921static inline unsigned int
922get_opcode_dependent_value (const aarch64_opcode *opcode)
923{
924 return (opcode->flags >> 24) & 0x7;
925}
926
927static inline bfd_boolean
928opcode_has_special_coder (const aarch64_opcode *opcode)
929{
ee804238 930 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 931 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
932 : FALSE;
933}
934\f
935struct aarch64_name_value_pair
936{
937 const char * name;
938 aarch64_insn value;
939};
940
941extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 942extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
943extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 944extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 945
49eec193
YZ		 946typedef struct
947{
948 const char * name;
949 aarch64_insn value;
950 uint32_t flags;
14962256
AC		 951
952 /* A set of features, all of which are required for this system register to be
953 available. */
954 aarch64_feature_set features;
49eec193
YZ		 955} aarch64_sys_reg;
956
957extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 958extern const aarch64_sys_reg aarch64_pstatefields [];
f7cb161e 959extern bfd_boolean aarch64_sys_reg_deprecated_p (const uint32_t);
f21cce2c
MW		 960extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
961 const aarch64_sys_reg *);
49eec193 962
a06ea964
NC		 963typedef struct
964{
875880c6 965 const char *name;
a06ea964 966 uint32_t value;
ea2deeec 967 uint32_t flags ;
a06ea964
NC		 968} aarch64_sys_ins_reg;
969
ea2deeec 970extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6 971extern bfd_boolean
f7cb161e
PW		 972aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, aarch64_insn,
973 uint32_t, aarch64_feature_set);
ea2deeec 974
a06ea964
NC		 975extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
976extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
977extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
978extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
2ac435d4 979extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
a06ea964
NC		 980
981/* Shift/extending operator kinds.
982 N.B. order is important; keep aarch64_operand_modifiers synced. */
983enum aarch64_modifier_kind
984{
985 AARCH64_MOD_NONE,
986 AARCH64_MOD_MSL,
987 AARCH64_MOD_ROR,
988 AARCH64_MOD_ASR,
989 AARCH64_MOD_LSR,
990 AARCH64_MOD_LSL,
991 AARCH64_MOD_UXTB,
992 AARCH64_MOD_UXTH,
993 AARCH64_MOD_UXTW,
994 AARCH64_MOD_UXTX,
995 AARCH64_MOD_SXTB,
996 AARCH64_MOD_SXTH,
997 AARCH64_MOD_SXTW,
998 AARCH64_MOD_SXTX,
2442d846 999 AARCH64_MOD_MUL,
98907a70 1000 AARCH64_MOD_MUL_VL,
a06ea964
NC		 1001};
1002
1003bfd_boolean
1004aarch64_extend_operator_p (enum aarch64_modifier_kind);
1005
1006enum aarch64_modifier_kind
1007aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
1008/* Condition. */
1009
1010typedef struct
1011{
1012 /* A list of names with the first one as the disassembly preference;
1013 terminated by NULL if fewer than 3. */
bb7eff52 1014 const char *names[4];
a06ea964
NC		 1015 aarch64_insn value;
1016} aarch64_cond;
1017
1018extern const aarch64_cond aarch64_conds[16];
1019
1020const aarch64_cond* get_cond_from_value (aarch64_insn value);
1021const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
1022\f
1023/* Structure representing an operand. */
1024
1025struct aarch64_opnd_info
1026{
1027 enum aarch64_opnd type;
1028 aarch64_opnd_qualifier_t qualifier;
1029 int idx;
1030
1031 union
1032 {
1033 struct
1034 {
1035 unsigned regno;
1036 } reg;
1037 struct
1038 {
dab26bf4
RS		 1039 unsigned int regno;
1040 int64_t index;
a06ea964
NC		 1041 } reglane;
1042 /* e.g. LVn. */
1043 struct
1044 {
1045 unsigned first_regno : 5;
1046 unsigned num_regs : 3;
1047 /* 1 if it is a list of reg element. */
1048 unsigned has_index : 1;
1049 /* Lane index; valid only when has_index is 1. */
dab26bf4 1050 int64_t index;
a06ea964
NC		 1051 } reglist;
1052 /* e.g. immediate or pc relative address offset. */
1053 struct
1054 {
1055 int64_t value;
1056 unsigned is_fp : 1;
1057 } imm;
1058 /* e.g. address in STR (register offset). */
1059 struct
1060 {
1061 unsigned base_regno;
1062 struct
1063 {
1064 union
1065 {
1066 int imm;
1067 unsigned regno;
1068 };
1069 unsigned is_reg;
1070 } offset;
1071 unsigned pcrel : 1; /* PC-relative. */
1072 unsigned writeback : 1;
1073 unsigned preind : 1; /* Pre-indexed. */
1074 unsigned postind : 1; /* Post-indexed. */
1075 } addr;
561a72d4
TC		 1076
1077 struct
1078 {
1079 /* The encoding of the system register. */
1080 aarch64_insn value;
1081
1082 /* The system register flags. */
1083 uint32_t flags;
1084 } sysreg;
1085
a06ea964 1086 const aarch64_cond *cond;
a06ea964
NC		 1087 /* The encoding of the PSTATE field. */
1088 aarch64_insn pstatefield;
1089 const aarch64_sys_ins_reg *sysins_op;
1090 const struct aarch64_name_value_pair *barrier;
9ed608f9 1091 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 1092 const struct aarch64_name_value_pair *prfop;
1093 };
1094
1095 /* Operand shifter; in use when the operand is a register offset address,
1096 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
1097 struct
1098 {
1099 enum aarch64_modifier_kind kind;
a06ea964
NC		 1100 unsigned operator_present: 1; /* Only valid during encoding. */
1101 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1102 unsigned amount_present: 1;
2442d846 1103 int64_t amount;
a06ea964
NC		 1104 } shifter;
1105
1106 unsigned skip:1; /* Operand is not completed if there is a fixup needed
1107 to be done on it. In some (but not all) of these
1108 cases, we need to tell libopcodes to skip the
1109 constraint checking and the encoding for this
1110 operand, so that the libopcodes can pick up the
1111 right opcode before the operand is fixed-up. This
1112 flag should only be used during the
1113 assembling/encoding. */
1114 unsigned present:1; /* Whether this operand is present in the assembly
1115 line; not used during the disassembly. */
1116};
1117
1118typedef struct aarch64_opnd_info aarch64_opnd_info;
1119
1120/* Structure representing an instruction.
1121
1122 It is used during both the assembling and disassembling. The assembler
1123 fills an aarch64_inst after a successful parsing and then passes it to the
1124 encoding routine to do the encoding. During the disassembling, the
1125 disassembler calls the decoding routine to decode a binary instruction; on a
1126 successful return, such a structure will be filled with information of the
1127 instruction; then the disassembler uses the information to print out the
1128 instruction. */
1129
1130struct aarch64_inst
1131{
1132 /* The value of the binary instruction. */
1133 aarch64_insn value;
1134
1135 /* Corresponding opcode entry. */
1136 const aarch64_opcode *opcode;
1137
1138 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1139 const aarch64_cond *cond;
1140
1141 /* Operands information. */
1142 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1143};
1144
ff605452
SD		 1145/* Defining the HINT #imm values for the aarch64_hint_options. */
1146#define HINT_OPD_CSYNC 0x11
1147#define HINT_OPD_C 0x22
1148#define HINT_OPD_J 0x24
1149#define HINT_OPD_JC 0x26
1150#define HINT_OPD_NULL 0x00
1151
a06ea964
NC		 1152\f
1153/* Diagnosis related declaration and interface. */
1154
1155/* Operand error kind enumerators.
1156
1157 AARCH64_OPDE_RECOVERABLE
1158 Less severe error found during the parsing, very possibly because that
1159 GAS has picked up a wrong instruction template for the parsing.
1160
1161 AARCH64_OPDE_SYNTAX_ERROR
1162 General syntax error; it can be either a user error, or simply because
1163 that GAS is trying a wrong instruction template.
1164
1165 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1166 Definitely a user syntax error.
1167
1168 AARCH64_OPDE_INVALID_VARIANT
1169 No syntax error, but the operands are not a valid combination, e.g.
1170 FMOV D0,S0
1171
0c608d6b
RS		 1172 AARCH64_OPDE_UNTIED_OPERAND
1173 The asm failed to use the same register for a destination operand
1174 and a tied source operand.
1175
a06ea964
NC		 1176 AARCH64_OPDE_OUT_OF_RANGE
1177 Error about some immediate value out of a valid range.
1178
1179 AARCH64_OPDE_UNALIGNED
1180 Error about some immediate value not properly aligned (i.e. not being a
1181 multiple times of a certain value).
1182
1183 AARCH64_OPDE_REG_LIST
1184 Error about the register list operand having unexpected number of
1185 registers.
1186
1187 AARCH64_OPDE_OTHER_ERROR
1188 Error of the highest severity and used for any severe issue that does not
1189 fall into any of the above categories.
1190
1191 The enumerators are only interesting to GAS. They are declared here (in
1192 libopcodes) because that some errors are detected (and then notified to GAS)
1193 by libopcodes (rather than by GAS solely).
1194
1195 The first three errors are only deteced by GAS while the
1196 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1197 only libopcodes has the information about the valid variants of each
1198 instruction.
1199
1200 The enumerators have an increasing severity. This is helpful when there are
1201 multiple instruction templates available for a given mnemonic name (e.g.
1202 FMOV); this mechanism will help choose the most suitable template from which
1203 the generated diagnostics can most closely describe the issues, if any. */
1204
1205enum aarch64_operand_error_kind
1206{
1207 AARCH64_OPDE_NIL,
1208 AARCH64_OPDE_RECOVERABLE,
1209 AARCH64_OPDE_SYNTAX_ERROR,
1210 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1211 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1212 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1213 AARCH64_OPDE_OUT_OF_RANGE,
1214 AARCH64_OPDE_UNALIGNED,
1215 AARCH64_OPDE_REG_LIST,
1216 AARCH64_OPDE_OTHER_ERROR
1217};
1218
1219/* N.B. GAS assumes that this structure work well with shallow copy. */
1220struct aarch64_operand_error
1221{
1222 enum aarch64_operand_error_kind kind;
1223 int index;
1224 const char *error;
1225 int data[3]; /* Some data for extra information. */
7d02540a 1226 bfd_boolean non_fatal;
a06ea964
NC		 1227};
1228
7e84b55d
TC		 1229/* AArch64 sequence structure used to track instructions with F_SCAN
1230 dependencies for both assembler and disassembler. */
1231struct aarch64_instr_sequence
1232{
1233 /* The instruction that caused this sequence to be opened. */
1234 aarch64_inst *instr;
1235 /* The number of instructions the above instruction allows to be kept in the
1236 sequence before an automatic close is done. */
1237 int num_insns;
1238 /* The instructions currently added to the sequence. */
1239 aarch64_inst **current_insns;
1240 /* The number of instructions already in the sequence. */
1241 int next_insn;
1242};
a06ea964
NC		 1243
1244/* Encoding entrypoint. */
1245
1246extern int
1247aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1248 aarch64_insn *, aarch64_opnd_qualifier_t *,
7e84b55d 1249 aarch64_operand_error *, aarch64_instr_sequence *);
a06ea964
NC		 1250
1251extern const aarch64_opcode *
1252aarch64_replace_opcode (struct aarch64_inst *,
1253 const aarch64_opcode *);
1254
1255/* Given the opcode enumerator OP, return the pointer to the corresponding
1256 opcode entry. */
1257
1258extern const aarch64_opcode *
1259aarch64_get_opcode (enum aarch64_op);
1260
1261/* Generate the string representation of an operand. */
1262extern void
1263aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
7d02540a
TC		 1264 const aarch64_opnd_info *, int, int *, bfd_vma *,
1265 char **);
a06ea964
NC		 1266
1267/* Miscellaneous interface. */
1268
1269extern int
1270aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1271
1272extern aarch64_opnd_qualifier_t
1273aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1274 const aarch64_opnd_qualifier_t, int);
1275
a68f4cd2
TC		 1276extern bfd_boolean
1277aarch64_is_destructive_by_operands (const aarch64_opcode *);
1278
a06ea964
NC		 1279extern int
1280aarch64_num_of_operands (const aarch64_opcode *);
1281
1282extern int
1283aarch64_stack_pointer_p (const aarch64_opnd_info *);
1284
e141d84e
YQ		 1285extern int
1286aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1287
1d482394 1288extern enum err_type
561a72d4 1289aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
a68f4cd2
TC		 1290 aarch64_operand_error *);
1291
1292extern void
1293init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
36f4aab1 1294
a06ea964
NC		 1295/* Given an operand qualifier, return the expected data element size
1296 of a qualified operand. */
1297extern unsigned char
1298aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1299
1300extern enum aarch64_operand_class
1301aarch64_get_operand_class (enum aarch64_opnd);
1302
1303extern const char *
1304aarch64_get_operand_name (enum aarch64_opnd);
1305
1306extern const char *
1307aarch64_get_operand_desc (enum aarch64_opnd);
1308
e950b345
RS		 1309extern bfd_boolean
1310aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1311
a06ea964
NC		 1312#ifdef DEBUG_AARCH64
1313extern int debug_dump;
1314
1315extern void
1316aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1317
1318#define DEBUG_TRACE(M, ...) \
1319 { \
1320 if (debug_dump) \
1321 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1322 }
1323
1324#define DEBUG_TRACE_IF(C, M, ...) \
1325 { \
1326 if (debug_dump && (C)) \
1327 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1328 }
1329#else /* !DEBUG_AARCH64 */
1330#define DEBUG_TRACE(M, ...) ;
1331#define DEBUG_TRACE_IF(C, M, ...) ;
1332#endif /* DEBUG_AARCH64 */
1333
245d2e3f
RS		 1334extern const char *const aarch64_sve_pattern_array[32];
1335extern const char *const aarch64_sve_prfop_array[16];
1336
d3e12b29
YQ		 1337#ifdef __cplusplus
1338}
1339#endif
1340
a06ea964 1341#endif /* OPCODE_AARCH64_H */
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