]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - include/opcode/aarch64.h
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Handle __XVL fields in Ada type printing
[thirdparty/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
b3adc24a 3 Copyright (C) 2009-2020 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
359157df
AC		 40#define AARCH64_FEATURE_V8 (1ULL << 0) /* All processors. */
41#define AARCH64_FEATURE_V8_6 (1ULL << 1) /* ARMv8.6 processors. */
42#define AARCH64_FEATURE_BFLOAT16 (1ULL << 2) /* Bfloat16 insns. */
95830c98 43#define AARCH64_FEATURE_V8_A (1ULL << 3) /* Armv8-A processors. */
359157df
AC		 44#define AARCH64_FEATURE_SVE2 (1ULL << 4) /* SVE2 instructions. */
45#define AARCH64_FEATURE_V8_2 (1ULL << 5) /* ARMv8.2 processors. */
46#define AARCH64_FEATURE_V8_3 (1ULL << 6) /* ARMv8.3 processors. */
47#define AARCH64_FEATURE_SVE2_AES (1ULL << 7)
48#define AARCH64_FEATURE_SVE2_BITPERM (1ULL << 8)
49#define AARCH64_FEATURE_SVE2_SM4 (1ULL << 9)
50#define AARCH64_FEATURE_SVE2_SHA3 (1ULL << 10)
51#define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */
95830c98 52#define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */
8926e54e 53#define AARCH64_FEATURE_V8_7 (1ULL << 13) /* Armv8.7 processors. */
dd4a72c8 54#define AARCH64_FEATURE_CSRE (1ULL << 14) /* CSRE feature. */
fd65497d 55#define AARCH64_FEATURE_LS64 (1ULL << 15) /* Atomic 64-byte load/store. */
359157df
AC		 56#define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */
57#define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */
58#define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */
59#define AARCH64_FEATURE_LSE (1ULL << 20) /* LSE instructions. */
60#define AARCH64_FEATURE_PAN (1ULL << 21) /* PAN instructions. */
61#define AARCH64_FEATURE_LOR (1ULL << 22) /* LOR instructions. */
62#define AARCH64_FEATURE_RDMA (1ULL << 23) /* v8.1 SIMD instructions. */
63#define AARCH64_FEATURE_V8_1 (1ULL << 24) /* v8.1 features. */
64#define AARCH64_FEATURE_F16 (1ULL << 25) /* v8.2 FP16 instructions. */
65#define AARCH64_FEATURE_RAS (1ULL << 26) /* RAS Extensions. */
66#define AARCH64_FEATURE_PROFILE (1ULL << 27) /* Statistical Profiling. */
67#define AARCH64_FEATURE_SVE (1ULL << 28) /* SVE instructions. */
68#define AARCH64_FEATURE_RCPC (1ULL << 29) /* RCPC instructions. */
69#define AARCH64_FEATURE_COMPNUM (1ULL << 30) /* Complex # instructions. */
70#define AARCH64_FEATURE_DOTPROD (1ULL << 31) /* Dot Product instructions. */
71#define AARCH64_FEATURE_SM4 (1ULL << 32) /* SM3 & SM4 instructions. */
72#define AARCH64_FEATURE_SHA2 (1ULL << 33) /* SHA2 instructions. */
73#define AARCH64_FEATURE_SHA3 (1ULL << 34) /* SHA3 instructions. */
74#define AARCH64_FEATURE_AES (1ULL << 35) /* AES instructions. */
75#define AARCH64_FEATURE_F16_FML (1ULL << 36) /* v8.2 FP16FML ins. */
76#define AARCH64_FEATURE_V8_5 (1ULL << 37) /* ARMv8.5 processors. */
77#define AARCH64_FEATURE_FLAGMANIP (1ULL << 38) /* Flag Manipulation insns. */
78#define AARCH64_FEATURE_FRINTTS (1ULL << 39) /* FRINT[32,64][Z,X] insns. */
79#define AARCH64_FEATURE_SB (1ULL << 40) /* SB instruction. */
80#define AARCH64_FEATURE_PREDRES (1ULL << 41) /* Execution and Data Prediction Restriction instructions. */
81#define AARCH64_FEATURE_CVADP (1ULL << 42) /* DC CVADP. */
82#define AARCH64_FEATURE_RNG (1ULL << 43) /* Random Number instructions. */
83#define AARCH64_FEATURE_BTI (1ULL << 44) /* BTI instructions. */
84#define AARCH64_FEATURE_SCXTNUM (1ULL << 45) /* SCXTNUM_ELx. */
85#define AARCH64_FEATURE_ID_PFR2 (1ULL << 46) /* ID_PFR2 instructions. */
86#define AARCH64_FEATURE_SSBS (1ULL << 47) /* SSBS mechanism enabled. */
87#define AARCH64_FEATURE_MEMTAG (1ULL << 48) /* Memory Tagging Extension. */
88#define AARCH64_FEATURE_TME (1ULL << 49) /* Transactional Memory Extension. */
89#define AARCH64_FEATURE_I8MM (1ULL << 52) /* Matrix Multiply instructions. */
90#define AARCH64_FEATURE_F32MM (1ULL << 53)
91#define AARCH64_FEATURE_F64MM (1ULL << 54)
7ce2460a 92
2dc4b12f
JB		 93/* Crypto instructions are the combination of AES and SHA2. */
94#define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
95
a06ea964
NC		 96/* Architectures are the sum of the base and extensions. */
97#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
95830c98
AC		 98 AARCH64_FEATURE_V8_A \
99 | AARCH64_FEATURE_FP \
a06ea964 100 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 101#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
102 AARCH64_FEATURE_CRC \
250aafa4 103 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 104 | AARCH64_FEATURE_LSE \
105 | AARCH64_FEATURE_PAN \
106 | AARCH64_FEATURE_LOR \
107 | AARCH64_FEATURE_RDMA)
1924ff75 108#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 109 AARCH64_FEATURE_V8_2 \
1924ff75
SN		 110 | AARCH64_FEATURE_RAS)
111#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 112 AARCH64_FEATURE_V8_3 \
f482d304
RS		 113 | AARCH64_FEATURE_RCPC \
114 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c 115#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
981b557a 116 AARCH64_FEATURE_V8_4 \
d0f7791c
TC		 117 | AARCH64_FEATURE_DOTPROD \
118 | AARCH64_FEATURE_F16_FML)
70d56181 119#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
13c60ad7
SD		 120 AARCH64_FEATURE_V8_5 \
121 | AARCH64_FEATURE_FLAGMANIP \
68dfbb92 122 | AARCH64_FEATURE_FRINTTS \
2ac435d4 123 | AARCH64_FEATURE_SB \
3fd229a4 124 | AARCH64_FEATURE_PREDRES \
ff605452 125 | AARCH64_FEATURE_CVADP \
a97330e7
SD		 126 | AARCH64_FEATURE_BTI \
127 | AARCH64_FEATURE_SCXTNUM \
104fefee
SD		 128 | AARCH64_FEATURE_ID_PFR2 \
129 | AARCH64_FEATURE_SSBS)
8ae2d3d9 130#define AARCH64_ARCH_V8_6 AARCH64_FEATURE (AARCH64_ARCH_V8_5, \
df678013 131 AARCH64_FEATURE_V8_6 \
8382113f
MM		 132 | AARCH64_FEATURE_BFLOAT16 \
133 | AARCH64_FEATURE_I8MM)
8926e54e 134#define AARCH64_ARCH_V8_7 AARCH64_FEATURE (AARCH64_ARCH_V8_6, \
fd65497d
PW		 135 AARCH64_FEATURE_V8_7 \
136 | AARCH64_FEATURE_LS64)
95830c98
AC		 137#define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
138 AARCH64_FEATURE_V8_R) \
139 & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR))
88f0ea34 140
a06ea964
NC		 141#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
142#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
143
144/* CPU-specific features. */
21b81e67 145typedef unsigned long long aarch64_feature_set;
a06ea964 146
93d8990c
SN		 147#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
148 ((~(CPU) & (FEAT)) == 0)
149
150#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 151 (((CPU) & (FEAT)) != 0)
152
93d8990c
SN		 153#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
154 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
155
a06ea964
NC		 156#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
157 do \
158 { \
159 (TARG) = (F1) | (F2); \
160 } \
161 while (0)
162
163#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
164 do \
165 { \
166 (TARG) = (F1) &~ (F2); \
167 } \
168 while (0)
169
170#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
171
a06ea964
NC		 172enum aarch64_operand_class
173{
174 AARCH64_OPND_CLASS_NIL,
175 AARCH64_OPND_CLASS_INT_REG,
176 AARCH64_OPND_CLASS_MODIFIED_REG,
177 AARCH64_OPND_CLASS_FP_REG,
178 AARCH64_OPND_CLASS_SIMD_REG,
179 AARCH64_OPND_CLASS_SIMD_ELEMENT,
180 AARCH64_OPND_CLASS_SISD_REG,
181 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 182 AARCH64_OPND_CLASS_SVE_REG,
183 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 184 AARCH64_OPND_CLASS_ADDRESS,
185 AARCH64_OPND_CLASS_IMMEDIATE,
186 AARCH64_OPND_CLASS_SYSTEM,
68a64283 187 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 188};
189
190/* Operand code that helps both parsing and coding.
191 Keep AARCH64_OPERANDS synced. */
192
193enum aarch64_opnd
194{
195 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
196
197 AARCH64_OPND_Rd, /* Integer register as destination. */
198 AARCH64_OPND_Rn, /* Integer register as source. */
199 AARCH64_OPND_Rm, /* Integer register as source. */
200 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
201 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
bd7ceb8d 202 AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */
a06ea964
NC		 203 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
204 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
205 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
206
207 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
208 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 209 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 210 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 211 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
212 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
213
214 AARCH64_OPND_Fd, /* Floating-point Fd. */
215 AARCH64_OPND_Fn, /* Floating-point Fn. */
216 AARCH64_OPND_Fm, /* Floating-point Fm. */
217 AARCH64_OPND_Fa, /* Floating-point Fa. */
218 AARCH64_OPND_Ft, /* Floating-point Ft. */
219 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
220
221 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
222 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
223 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
224
f42f1a1d 225 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
a06ea964
NC		 226 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
227 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
228 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
229 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
230 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
231 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
232 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
233 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
369c9167
TC		 234 AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
235 qualifier is S_H. */
a06ea964
NC		 236 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
237 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
238 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
239 structure to all lanes. */
240 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
241
a6a51754
RL		 242 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
243 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 244
245 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
f42f1a1d 246 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
a06ea964
NC		 247 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
248 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
249 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
250 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
251 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
252 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
253 (no encoding). */
254 AARCH64_OPND_IMM0, /* Immediate for #0. */
255 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
256 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
257 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
258 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
259 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
260 AARCH64_OPND_IMM, /* Immediate. */
f42f1a1d 261 AARCH64_OPND_IMM_2, /* Immediate. */
a06ea964
NC		 262 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
263 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
264 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
193614f2 265 AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */
a06ea964 266 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
193614f2 267 AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */
a06ea964
NC		 268 AARCH64_OPND_BIT_NUM, /* Immediate. */
269 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
09c1e68a 270 AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */
a06ea964 271 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 272 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 273 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
274 each condition flag. */
275
276 AARCH64_OPND_LIMM, /* Logical Immediate. */
277 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
278 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
279 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
280 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 281 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
282 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
283 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 284
285 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 286 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 287
288 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
289 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
290 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
291 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
292 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
293
294 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
295 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
296 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
297 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
298 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
299 negative or unaligned and there is
300 no writeback allowed. This operand code
301 is only used to support the programmer-
302 friendly feature of using LDR/STR as the
303 the mnemonic name for LDUR/STUR instructions
304 wherever there is no ambiguity. */
3f06e550 305 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
fb3265b3
SD		 306 AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of
307 16) immediate. */
a06ea964 308 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
fb3265b3
SD		 309 AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of
310 16) immediate. */
a06ea964 311 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
f42f1a1d 312 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
a06ea964
NC		 313 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
314
315 AARCH64_OPND_SYSREG, /* System register operand. */
316 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
317 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
318 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
319 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
320 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
2ac435d4 321 AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
a06ea964 322 AARCH64_OPND_BARRIER, /* Barrier operand. */
fd195909 323 AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant. */
a06ea964
NC		 324 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
325 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 326 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
ff605452 327 AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
f11ad6bc 328
582e12bf 329 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
8382113f 330 AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn|SP>, #<simm4>*32]. */
98907a70
RS		 331 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
332 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
333 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
334 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
335 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
336 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 337 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
338 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
339 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
340 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
c8d59609 341 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
4df068de
RS		 342 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
343 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
344 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
345 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
346 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
347 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
348 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
349 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
c469c864 350 AARCH64_OPND_SVE_ADDR_ZX, /* SVE [Zn.<T>{, <Xm>}]. */
4df068de
RS		 351 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
352 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
353 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
354 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
355 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
356 Bit 14 controls S/U choice. */
357 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
358 Bit 22 controls S/U choice. */
359 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
360 Bit 14 controls S/U choice. */
361 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
362 Bit 22 controls S/U choice. */
363 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
364 Bit 14 controls S/U choice. */
365 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
366 Bit 22 controls S/U choice. */
367 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
368 Bit 14 controls S/U choice. */
369 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
370 Bit 22 controls S/U choice. */
371 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
372 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
373 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
374 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
375 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
376 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
377 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 378 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
379 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 380 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
381 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
382 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
383 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS		 384 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
385 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
adccc507 386 AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */
e950b345
RS		 387 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
388 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
389 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 390 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 391 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 392 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 393 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
394 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
395 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
396 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
397 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
398 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
399 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
400 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 401 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
402 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 403 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
404 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
28ed815a 405 AARCH64_OPND_SVE_SHLIMM_UNPRED_22, /* SVE 3 bit shift left unpred. */
e950b345
RS		 406 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
407 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
3c17238b 408 AARCH64_OPND_SVE_SHRIMM_UNPRED_22, /* SVE 3 bit shift right unpred. */
e950b345
RS		 409 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
410 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
411 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
412 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
413 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
414 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
415 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
416 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 417 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
418 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
419 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
420 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 421 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
422 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
423 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
424 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
425 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS		 426 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
427 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
116adc27 428 AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */
31e36ab3 429 AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */
582e12bf 430 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS		 431 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
432 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
433 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
434 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
435 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
b83b4b13 436 AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
f42f1a1d 437 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
dd4a72c8 438 AARCH64_OPND_CSRE_CSR, /* CSRE CSR instruction Rt field. */
a06ea964
NC		 439};
440
441/* Qualifier constrains an operand. It either specifies a variant of an
442 operand type or limits values available to an operand type.
443
444 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
445
446enum aarch64_opnd_qualifier
447{
448 /* Indicating no further qualification on an operand. */
449 AARCH64_OPND_QLF_NIL,
450
451 /* Qualifying an operand which is a general purpose (integer) register;
452 indicating the operand data size or a specific register. */
453 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
454 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
455 AARCH64_OPND_QLF_WSP, /* WSP. */
456 AARCH64_OPND_QLF_SP, /* SP. */
457
458 /* Qualifying an operand which is a floating-point register, a SIMD
459 vector element or a SIMD vector element list; indicating operand data
460 size or the size of each SIMD vector element in the case of a SIMD
461 vector element list.
462 These qualifiers are also used to qualify an address operand to
463 indicate the size of data element a load/store instruction is
464 accessing.
465 They are also used for the immediate shift operand in e.g. SSHR. Such
466 a use is only for the ease of operand encoding/decoding and qualifier
467 sequence matching; such a use should not be applied widely; use the value
468 constraint qualifiers for immediate operands wherever possible. */
469 AARCH64_OPND_QLF_S_B,
470 AARCH64_OPND_QLF_S_H,
471 AARCH64_OPND_QLF_S_S,
472 AARCH64_OPND_QLF_S_D,
473 AARCH64_OPND_QLF_S_Q,
df678013
MM		 474 /* These type qualifiers have a special meaning in that they mean 4 x 1 byte
475 or 2 x 2 byte are selected by the instruction. Other than that they have
476 no difference with AARCH64_OPND_QLF_S_B in encoding. They are here purely
477 for syntactical reasons and is an exception from normal AArch64
478 disassembly scheme. */
00c2093f 479 AARCH64_OPND_QLF_S_4B,
df678013 480 AARCH64_OPND_QLF_S_2H,
a06ea964
NC		 481
482 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
483 register list; indicating register shape.
484 They are also used for the immediate shift operand in e.g. SSHR. Such
485 a use is only for the ease of operand encoding/decoding and qualifier
486 sequence matching; such a use should not be applied widely; use the value
487 constraint qualifiers for immediate operands wherever possible. */
a3b3345a 488 AARCH64_OPND_QLF_V_4B,
a06ea964
NC		 489 AARCH64_OPND_QLF_V_8B,
490 AARCH64_OPND_QLF_V_16B,
3067d3b9 491 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 492 AARCH64_OPND_QLF_V_4H,
493 AARCH64_OPND_QLF_V_8H,
494 AARCH64_OPND_QLF_V_2S,
495 AARCH64_OPND_QLF_V_4S,
496 AARCH64_OPND_QLF_V_1D,
497 AARCH64_OPND_QLF_V_2D,
498 AARCH64_OPND_QLF_V_1Q,
499
d50c751e
RS		 500 AARCH64_OPND_QLF_P_Z,
501 AARCH64_OPND_QLF_P_M,
fb3265b3
SD		 502
503 /* Used in scaled signed immediate that are scaled by a Tag granule
504 like in stg, st2g, etc. */
505 AARCH64_OPND_QLF_imm_tag,
d50c751e 506
a06ea964 507 /* Constraint on value. */
a6a51754 508 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 509 AARCH64_OPND_QLF_imm_0_7,
510 AARCH64_OPND_QLF_imm_0_15,
511 AARCH64_OPND_QLF_imm_0_31,
512 AARCH64_OPND_QLF_imm_0_63,
513 AARCH64_OPND_QLF_imm_1_32,
514 AARCH64_OPND_QLF_imm_1_64,
515
516 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
517 or shift-ones. */
518 AARCH64_OPND_QLF_LSL,
519 AARCH64_OPND_QLF_MSL,
520
521 /* Special qualifier helping retrieve qualifier information during the
522 decoding time (currently not in use). */
523 AARCH64_OPND_QLF_RETRIEVE,
524};
525\f
526/* Instruction class. */
527
528enum aarch64_insn_class
529{
8382113f 530 aarch64_misc,
a06ea964
NC		 531 addsub_carry,
532 addsub_ext,
533 addsub_imm,
534 addsub_shift,
535 asimdall,
536 asimddiff,
537 asimdelem,
538 asimdext,
539 asimdimm,
540 asimdins,
541 asimdmisc,
542 asimdperm,
543 asimdsame,
544 asimdshf,
545 asimdtbl,
546 asisddiff,
547 asisdelem,
548 asisdlse,
549 asisdlsep,
550 asisdlso,
551 asisdlsop,
552 asisdmisc,
553 asisdone,
554 asisdpair,
555 asisdsame,
556 asisdshf,
557 bitfield,
558 branch_imm,
559 branch_reg,
560 compbranch,
561 condbranch,
562 condcmp_imm,
563 condcmp_reg,
564 condsel,
565 cryptoaes,
566 cryptosha2,
567 cryptosha3,
568 dp_1src,
569 dp_2src,
570 dp_3src,
571 exception,
572 extract,
573 float2fix,
574 float2int,
575 floatccmp,
576 floatcmp,
577 floatdp1,
578 floatdp2,
579 floatdp3,
580 floatimm,
581 floatsel,
582 ldst_immpost,
583 ldst_immpre,
584 ldst_imm9, /* immpost or immpre */
3f06e550 585 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 586 ldst_pos,
587 ldst_regoff,
588 ldst_unpriv,
589 ldst_unscaled,
590 ldstexcl,
591 ldstnapair_offs,
592 ldstpair_off,
593 ldstpair_indexed,
594 loadlit,
595 log_imm,
596 log_shift,
ee804238 597 lse_atomic,
a06ea964
NC		 598 movewide,
599 pcreladdr,
600 ic_system,
116b6019
RS		 601 sve_cpy,
602 sve_index,
603 sve_limm,
604 sve_misc,
605 sve_movprfx,
606 sve_pred_zm,
607 sve_shift_pred,
608 sve_shift_unpred,
609 sve_size_bhs,
610 sve_size_bhsd,
611 sve_size_hsd,
3bd82c86 612 sve_size_hsd2,
116b6019 613 sve_size_sd,
3c705960 614 sve_size_bh,
0a57e14f 615 sve_size_sd2,
41be57ca 616 sve_size_13,
3c17238b 617 sve_shift_tsz_hsd,
1be5f94f 618 sve_shift_tsz_bhsd,
fd1dc4a0 619 sve_size_tsz_bhs,
a06ea964 620 testbranch,
f42f1a1d
TC		 621 cryptosm3,
622 cryptosm4,
65a55fbb 623 dotproduct,
df678013 624 bfloat16,
a06ea964
NC		 625};
626
627/* Opcode enumerators. */
628
629enum aarch64_op
630{
631 OP_NIL,
632 OP_STRB_POS,
633 OP_LDRB_POS,
634 OP_LDRSB_POS,
635 OP_STRH_POS,
636 OP_LDRH_POS,
637 OP_LDRSH_POS,
638 OP_STR_POS,
639 OP_LDR_POS,
640 OP_STRF_POS,
641 OP_LDRF_POS,
642 OP_LDRSW_POS,
643 OP_PRFM_POS,
644
645 OP_STURB,
646 OP_LDURB,
647 OP_LDURSB,
648 OP_STURH,
649 OP_LDURH,
650 OP_LDURSH,
651 OP_STUR,
652 OP_LDUR,
653 OP_STURV,
654 OP_LDURV,
655 OP_LDURSW,
656 OP_PRFUM,
657
658 OP_LDR_LIT,
659 OP_LDRV_LIT,
660 OP_LDRSW_LIT,
661 OP_PRFM_LIT,
662
663 OP_ADD,
664 OP_B,
665 OP_BL,
666
667 OP_MOVN,
668 OP_MOVZ,
669 OP_MOVK,
670
671 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
672 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
673 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
674
675 OP_MOV_V, /* MOV alias for moving vector register. */
676
677 OP_ASR_IMM,
678 OP_LSR_IMM,
679 OP_LSL_IMM,
680
681 OP_BIC,
682
683 OP_UBFX,
684 OP_BFXIL,
685 OP_SBFX,
686 OP_SBFIZ,
687 OP_BFI,
d685192a 688 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 689 OP_UBFIZ,
690 OP_UXTB,
691 OP_UXTH,
692 OP_UXTW,
693
a06ea964
NC		 694 OP_CINC,
695 OP_CINV,
696 OP_CNEG,
697 OP_CSET,
698 OP_CSETM,
699
700 OP_FCVT,
701 OP_FCVTN,
702 OP_FCVTN2,
703 OP_FCVTL,
704 OP_FCVTL2,
705 OP_FCVTXN_S, /* Scalar version. */
706
707 OP_ROR_IMM,
708
e30181a5
YZ		 709 OP_SXTL,
710 OP_SXTL2,
711 OP_UXTL,
712 OP_UXTL2,
713
c0890d26
RS		 714 OP_MOV_P_P,
715 OP_MOV_Z_P_Z,
716 OP_MOV_Z_V,
717 OP_MOV_Z_Z,
718 OP_MOV_Z_Zi,
719 OP_MOVM_P_P_P,
720 OP_MOVS_P_P,
721 OP_MOVZS_P_P_P,
722 OP_MOVZ_P_P_P,
723 OP_NOTS_P_P_P_Z,
724 OP_NOT_P_P_P_Z,
725
c2c4ff8d
SN		 726 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
727
a06ea964
NC		 728 OP_TOTAL_NUM, /* Pseudo. */
729};
730
1d482394
TC		 731/* Error types. */
732enum err_type
733{
734 ERR_OK,
735 ERR_UND,
736 ERR_UNP,
737 ERR_NYI,
a68f4cd2 738 ERR_VFI,
1d482394
TC		 739 ERR_NR_ENTRIES
740};
741
a06ea964
NC		 742/* Maximum number of operands an instruction can have. */
743#define AARCH64_MAX_OPND_NUM 6
744/* Maximum number of qualifier sequences an instruction can have. */
745#define AARCH64_MAX_QLF_SEQ_NUM 10
746/* Operand qualifier typedef; optimized for the size. */
747typedef unsigned char aarch64_opnd_qualifier_t;
748/* Operand qualifier sequence typedef. */
749typedef aarch64_opnd_qualifier_t \
750 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
751
752/* FIXME: improve the efficiency. */
753static inline bfd_boolean
754empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
755{
756 int i;
757 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
758 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
759 return FALSE;
760 return TRUE;
761}
762
7e84b55d
TC		 763/* Forward declare error reporting type. */
764typedef struct aarch64_operand_error aarch64_operand_error;
765/* Forward declare instruction sequence type. */
766typedef struct aarch64_instr_sequence aarch64_instr_sequence;
767/* Forward declare instruction definition. */
768typedef struct aarch64_inst aarch64_inst;
769
a06ea964
NC		 770/* This structure holds information for a particular opcode. */
771
772struct aarch64_opcode
773{
774 /* The name of the mnemonic. */
775 const char *name;
776
777 /* The opcode itself. Those bits which will be filled in with
778 operands are zeroes. */
779 aarch64_insn opcode;
780
781 /* The opcode mask. This is used by the disassembler. This is a
782 mask containing ones indicating those bits which must match the
783 opcode field, and zeroes indicating those bits which need not
784 match (and are presumably filled in by operands). */
785 aarch64_insn mask;
786
787 /* Instruction class. */
788 enum aarch64_insn_class iclass;
789
790 /* Enumerator identifier. */
791 enum aarch64_op op;
792
793 /* Which architecture variant provides this instruction. */
794 const aarch64_feature_set *avariant;
795
796 /* An array of operand codes. Each code is an index into the
797 operand table. They appear in the order which the operands must
798 appear in assembly code, and are terminated by a zero. */
799 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
800
801 /* A list of operand qualifier code sequence. Each operand qualifier
802 code qualifies the corresponding operand code. Each operand
803 qualifier sequence specifies a valid opcode variant and related
804 constraint on operands. */
805 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
806
807 /* Flags providing information about this instruction */
eae424ae
TC		 808 uint64_t flags;
809
810 /* Extra constraints on the instruction that the verifier checks. */
811 uint32_t constraints;
4bd13cde 812
0c608d6b
RS		 813 /* If nonzero, this operand and operand 0 are both registers and
814 are required to have the same register number. */
815 unsigned char tied_operand;
816
4bd13cde 817 /* If non-NULL, a function to verify that a given instruction is valid. */
755b748f
TC		 818 enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
819 bfd_vma, bfd_boolean, aarch64_operand_error *,
820 struct aarch64_instr_sequence *);
a06ea964
NC		 821};
822
823typedef struct aarch64_opcode aarch64_opcode;
824
825/* Table describing all the AArch64 opcodes. */
826extern aarch64_opcode aarch64_opcode_table[];
827
828/* Opcode flags. */
829#define F_ALIAS (1 << 0)
830#define F_HAS_ALIAS (1 << 1)
831/* Disassembly preference priority 1-3 (the larger the higher). If nothing
832 is specified, it is the priority 0 by default, i.e. the lowest priority. */
833#define F_P1 (1 << 2)
834#define F_P2 (2 << 2)
835#define F_P3 (3 << 2)
836/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
837#define F_COND (1 << 4)
838/* Instruction has the field of 'sf'. */
839#define F_SF (1 << 5)
840/* Instruction has the field of 'size:Q'. */
841#define F_SIZEQ (1 << 6)
842/* Floating-point instruction has the field of 'type'. */
843#define F_FPTYPE (1 << 7)
844/* AdvSIMD scalar instruction has the field of 'size'. */
845#define F_SSIZE (1 << 8)
846/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
847#define F_T (1 << 9)
848/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
849#define F_GPRSIZE_IN_Q (1 << 10)
850/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
851#define F_LDS_SIZE (1 << 11)
852/* Optional operand; assume maximum of 1 operand can be optional. */
853#define F_OPD0_OPT (1 << 12)
854#define F_OPD1_OPT (2 << 12)
855#define F_OPD2_OPT (3 << 12)
856#define F_OPD3_OPT (4 << 12)
857#define F_OPD4_OPT (5 << 12)
858/* Default value for the optional operand when omitted from the assembly. */
859#define F_DEFAULT(X) (((X) & 0x1f) << 15)
860/* Instruction that is an alias of another instruction needs to be
861 encoded/decoded by converting it to/from the real form, followed by
862 the encoding/decoding according to the rules of the real opcode.
863 This compares to the direct coding using the alias's information.
864 N.B. this flag requires F_ALIAS to be used together. */
865#define F_CONV (1 << 20)
866/* Use together with F_ALIAS to indicate an alias opcode is a programmer
867 friendly pseudo instruction available only in the assembly code (thus will
868 not show up in the disassembly). */
869#define F_PSEUDO (1 << 21)
870/* Instruction has miscellaneous encoding/decoding rules. */
871#define F_MISC (1 << 22)
872/* Instruction has the field of 'N'; used in conjunction with F_SF. */
873#define F_N (1 << 23)
874/* Opcode dependent field. */
875#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 876/* Instruction has the field of 'sz'. */
877#define F_LSE_SZ (1 << 27)
4989adac
RS		 878/* Require an exact qualifier match, even for NIL qualifiers. */
879#define F_STRICT (1ULL << 28)
f9830ec1
TC		 880/* This system instruction is used to read system registers. */
881#define F_SYS_READ (1ULL << 29)
882/* This system instruction is used to write system registers. */
883#define F_SYS_WRITE (1ULL << 30)
eae424ae
TC		 884/* This instruction has an extra constraint on it that imposes a requirement on
885 subsequent instructions. */
886#define F_SCAN (1ULL << 31)
887/* Next bit is 32. */
888
889/* Instruction constraints. */
890/* This instruction has a predication constraint on the instruction at PC+4. */
891#define C_SCAN_MOVPRFX (1U << 0)
892/* This instruction's operation width is determined by the operand with the
893 largest element size. */
894#define C_MAX_ELEM (1U << 1)
895/* Next bit is 2. */
a06ea964
NC		 896
897static inline bfd_boolean
898alias_opcode_p (const aarch64_opcode *opcode)
899{
900 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
901}
902
903static inline bfd_boolean
904opcode_has_alias (const aarch64_opcode *opcode)
905{
906 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
907}
908
909/* Priority for disassembling preference. */
910static inline int
911opcode_priority (const aarch64_opcode *opcode)
912{
913 return (opcode->flags >> 2) & 0x3;
914}
915
916static inline bfd_boolean
917pseudo_opcode_p (const aarch64_opcode *opcode)
918{
919 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
920}
921
922static inline bfd_boolean
923optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
924{
925 return (((opcode->flags >> 12) & 0x7) == idx + 1)
926 ? TRUE : FALSE;
927}
928
929static inline aarch64_insn
930get_optional_operand_default_value (const aarch64_opcode *opcode)
931{
932 return (opcode->flags >> 15) & 0x1f;
933}
934
935static inline unsigned int
936get_opcode_dependent_value (const aarch64_opcode *opcode)
937{
938 return (opcode->flags >> 24) & 0x7;
939}
940
941static inline bfd_boolean
942opcode_has_special_coder (const aarch64_opcode *opcode)
943{
ee804238 944 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 945 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
946 : FALSE;
947}
948\f
949struct aarch64_name_value_pair
950{
951 const char * name;
952 aarch64_insn value;
953};
954
955extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964 956extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
fd195909 957extern const struct aarch64_name_value_pair aarch64_barrier_dsb_nxs_options [4];
a06ea964 958extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 959extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 960
fa63795f
AC		 961#define AARCH64_MAX_SYSREG_NAME_LEN 32
962
49eec193
YZ		 963typedef struct
964{
965 const char * name;
966 aarch64_insn value;
967 uint32_t flags;
14962256
AC		 968
969 /* A set of features, all of which are required for this system register to be
970 available. */
971 aarch64_feature_set features;
49eec193
YZ		 972} aarch64_sys_reg;
973
974extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 975extern const aarch64_sys_reg aarch64_pstatefields [];
f7cb161e 976extern bfd_boolean aarch64_sys_reg_deprecated_p (const uint32_t);
f21cce2c
MW		 977extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
978 const aarch64_sys_reg *);
49eec193 979
a06ea964
NC		 980typedef struct
981{
875880c6 982 const char *name;
a06ea964 983 uint32_t value;
ea2deeec 984 uint32_t flags ;
a06ea964
NC		 985} aarch64_sys_ins_reg;
986
ea2deeec 987extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6 988extern bfd_boolean
38cf07a6
AC		 989aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
990 const char *reg_name, aarch64_insn,
f7cb161e 991 uint32_t, aarch64_feature_set);
ea2deeec 992
a06ea964
NC		 993extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
994extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
995extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
996extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
2ac435d4 997extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
a06ea964
NC		 998
999/* Shift/extending operator kinds.
1000 N.B. order is important; keep aarch64_operand_modifiers synced. */
1001enum aarch64_modifier_kind
1002{
1003 AARCH64_MOD_NONE,
1004 AARCH64_MOD_MSL,
1005 AARCH64_MOD_ROR,
1006 AARCH64_MOD_ASR,
1007 AARCH64_MOD_LSR,
1008 AARCH64_MOD_LSL,
1009 AARCH64_MOD_UXTB,
1010 AARCH64_MOD_UXTH,
1011 AARCH64_MOD_UXTW,
1012 AARCH64_MOD_UXTX,
1013 AARCH64_MOD_SXTB,
1014 AARCH64_MOD_SXTH,
1015 AARCH64_MOD_SXTW,
1016 AARCH64_MOD_SXTX,
2442d846 1017 AARCH64_MOD_MUL,
98907a70 1018 AARCH64_MOD_MUL_VL,
a06ea964
NC		 1019};
1020
1021bfd_boolean
1022aarch64_extend_operator_p (enum aarch64_modifier_kind);
1023
1024enum aarch64_modifier_kind
1025aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
1026/* Condition. */
1027
1028typedef struct
1029{
1030 /* A list of names with the first one as the disassembly preference;
1031 terminated by NULL if fewer than 3. */
bb7eff52 1032 const char *names[4];
a06ea964
NC		 1033 aarch64_insn value;
1034} aarch64_cond;
1035
1036extern const aarch64_cond aarch64_conds[16];
1037
1038const aarch64_cond* get_cond_from_value (aarch64_insn value);
1039const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
1040\f
1041/* Structure representing an operand. */
1042
1043struct aarch64_opnd_info
1044{
1045 enum aarch64_opnd type;
1046 aarch64_opnd_qualifier_t qualifier;
1047 int idx;
1048
1049 union
1050 {
1051 struct
1052 {
1053 unsigned regno;
1054 } reg;
1055 struct
1056 {
dab26bf4
RS		 1057 unsigned int regno;
1058 int64_t index;
a06ea964
NC		 1059 } reglane;
1060 /* e.g. LVn. */
1061 struct
1062 {
1063 unsigned first_regno : 5;
1064 unsigned num_regs : 3;
1065 /* 1 if it is a list of reg element. */
1066 unsigned has_index : 1;
1067 /* Lane index; valid only when has_index is 1. */
dab26bf4 1068 int64_t index;
a06ea964
NC		 1069 } reglist;
1070 /* e.g. immediate or pc relative address offset. */
1071 struct
1072 {
1073 int64_t value;
1074 unsigned is_fp : 1;
1075 } imm;
1076 /* e.g. address in STR (register offset). */
1077 struct
1078 {
1079 unsigned base_regno;
1080 struct
1081 {
1082 union
1083 {
1084 int imm;
1085 unsigned regno;
1086 };
1087 unsigned is_reg;
1088 } offset;
1089 unsigned pcrel : 1; /* PC-relative. */
1090 unsigned writeback : 1;
1091 unsigned preind : 1; /* Pre-indexed. */
1092 unsigned postind : 1; /* Post-indexed. */
1093 } addr;
561a72d4
TC		 1094
1095 struct
1096 {
1097 /* The encoding of the system register. */
1098 aarch64_insn value;
1099
1100 /* The system register flags. */
1101 uint32_t flags;
1102 } sysreg;
1103
a06ea964 1104 const aarch64_cond *cond;
a06ea964
NC		 1105 /* The encoding of the PSTATE field. */
1106 aarch64_insn pstatefield;
1107 const aarch64_sys_ins_reg *sysins_op;
1108 const struct aarch64_name_value_pair *barrier;
9ed608f9 1109 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 1110 const struct aarch64_name_value_pair *prfop;
1111 };
1112
1113 /* Operand shifter; in use when the operand is a register offset address,
1114 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
1115 struct
1116 {
1117 enum aarch64_modifier_kind kind;
a06ea964
NC		 1118 unsigned operator_present: 1; /* Only valid during encoding. */
1119 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1120 unsigned amount_present: 1;
2442d846 1121 int64_t amount;
a06ea964
NC		 1122 } shifter;
1123
1124 unsigned skip:1; /* Operand is not completed if there is a fixup needed
1125 to be done on it. In some (but not all) of these
1126 cases, we need to tell libopcodes to skip the
1127 constraint checking and the encoding for this
1128 operand, so that the libopcodes can pick up the
1129 right opcode before the operand is fixed-up. This
1130 flag should only be used during the
1131 assembling/encoding. */
1132 unsigned present:1; /* Whether this operand is present in the assembly
1133 line; not used during the disassembly. */
1134};
1135
1136typedef struct aarch64_opnd_info aarch64_opnd_info;
1137
1138/* Structure representing an instruction.
1139
1140 It is used during both the assembling and disassembling. The assembler
1141 fills an aarch64_inst after a successful parsing and then passes it to the
1142 encoding routine to do the encoding. During the disassembling, the
1143 disassembler calls the decoding routine to decode a binary instruction; on a
1144 successful return, such a structure will be filled with information of the
1145 instruction; then the disassembler uses the information to print out the
1146 instruction. */
1147
1148struct aarch64_inst
1149{
1150 /* The value of the binary instruction. */
1151 aarch64_insn value;
1152
1153 /* Corresponding opcode entry. */
1154 const aarch64_opcode *opcode;
1155
1156 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1157 const aarch64_cond *cond;
1158
1159 /* Operands information. */
1160 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1161};
1162
ff605452
SD		 1163/* Defining the HINT #imm values for the aarch64_hint_options. */
1164#define HINT_OPD_CSYNC 0x11
1165#define HINT_OPD_C 0x22
1166#define HINT_OPD_J 0x24
1167#define HINT_OPD_JC 0x26
1168#define HINT_OPD_NULL 0x00
1169
a06ea964
NC		 1170\f
1171/* Diagnosis related declaration and interface. */
1172
1173/* Operand error kind enumerators.
1174
1175 AARCH64_OPDE_RECOVERABLE
1176 Less severe error found during the parsing, very possibly because that
1177 GAS has picked up a wrong instruction template for the parsing.
1178
1179 AARCH64_OPDE_SYNTAX_ERROR
1180 General syntax error; it can be either a user error, or simply because
1181 that GAS is trying a wrong instruction template.
1182
1183 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1184 Definitely a user syntax error.
1185
1186 AARCH64_OPDE_INVALID_VARIANT
1187 No syntax error, but the operands are not a valid combination, e.g.
1188 FMOV D0,S0
1189
0c608d6b
RS		 1190 AARCH64_OPDE_UNTIED_OPERAND
1191 The asm failed to use the same register for a destination operand
1192 and a tied source operand.
1193
a06ea964
NC		 1194 AARCH64_OPDE_OUT_OF_RANGE
1195 Error about some immediate value out of a valid range.
1196
1197 AARCH64_OPDE_UNALIGNED
1198 Error about some immediate value not properly aligned (i.e. not being a
1199 multiple times of a certain value).
1200
1201 AARCH64_OPDE_REG_LIST
1202 Error about the register list operand having unexpected number of
1203 registers.
1204
1205 AARCH64_OPDE_OTHER_ERROR
1206 Error of the highest severity and used for any severe issue that does not
1207 fall into any of the above categories.
1208
1209 The enumerators are only interesting to GAS. They are declared here (in
1210 libopcodes) because that some errors are detected (and then notified to GAS)
1211 by libopcodes (rather than by GAS solely).
1212
1213 The first three errors are only deteced by GAS while the
1214 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1215 only libopcodes has the information about the valid variants of each
1216 instruction.
1217
1218 The enumerators have an increasing severity. This is helpful when there are
1219 multiple instruction templates available for a given mnemonic name (e.g.
1220 FMOV); this mechanism will help choose the most suitable template from which
1221 the generated diagnostics can most closely describe the issues, if any. */
1222
1223enum aarch64_operand_error_kind
1224{
1225 AARCH64_OPDE_NIL,
1226 AARCH64_OPDE_RECOVERABLE,
1227 AARCH64_OPDE_SYNTAX_ERROR,
1228 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1229 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1230 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1231 AARCH64_OPDE_OUT_OF_RANGE,
1232 AARCH64_OPDE_UNALIGNED,
1233 AARCH64_OPDE_REG_LIST,
1234 AARCH64_OPDE_OTHER_ERROR
1235};
1236
1237/* N.B. GAS assumes that this structure work well with shallow copy. */
1238struct aarch64_operand_error
1239{
1240 enum aarch64_operand_error_kind kind;
1241 int index;
1242 const char *error;
1243 int data[3]; /* Some data for extra information. */
7d02540a 1244 bfd_boolean non_fatal;
a06ea964
NC		 1245};
1246
7e84b55d
TC		 1247/* AArch64 sequence structure used to track instructions with F_SCAN
1248 dependencies for both assembler and disassembler. */
1249struct aarch64_instr_sequence
1250{
1251 /* The instruction that caused this sequence to be opened. */
1252 aarch64_inst *instr;
1253 /* The number of instructions the above instruction allows to be kept in the
1254 sequence before an automatic close is done. */
1255 int num_insns;
1256 /* The instructions currently added to the sequence. */
1257 aarch64_inst **current_insns;
1258 /* The number of instructions already in the sequence. */
1259 int next_insn;
1260};
a06ea964
NC		 1261
1262/* Encoding entrypoint. */
1263
1264extern int
1265aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1266 aarch64_insn *, aarch64_opnd_qualifier_t *,
7e84b55d 1267 aarch64_operand_error *, aarch64_instr_sequence *);
a06ea964
NC		 1268
1269extern const aarch64_opcode *
1270aarch64_replace_opcode (struct aarch64_inst *,
1271 const aarch64_opcode *);
1272
1273/* Given the opcode enumerator OP, return the pointer to the corresponding
1274 opcode entry. */
1275
1276extern const aarch64_opcode *
1277aarch64_get_opcode (enum aarch64_op);
1278
1279/* Generate the string representation of an operand. */
1280extern void
1281aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
7d02540a 1282 const aarch64_opnd_info *, int, int *, bfd_vma *,
38cf07a6
AC		 1283 char **,
1284 aarch64_feature_set features);
a06ea964
NC		 1285
1286/* Miscellaneous interface. */
1287
1288extern int
1289aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1290
1291extern aarch64_opnd_qualifier_t
1292aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1293 const aarch64_opnd_qualifier_t, int);
1294
a68f4cd2
TC		 1295extern bfd_boolean
1296aarch64_is_destructive_by_operands (const aarch64_opcode *);
1297
a06ea964
NC		 1298extern int
1299aarch64_num_of_operands (const aarch64_opcode *);
1300
1301extern int
1302aarch64_stack_pointer_p (const aarch64_opnd_info *);
1303
e141d84e
YQ		 1304extern int
1305aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1306
1d482394 1307extern enum err_type
561a72d4 1308aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
a68f4cd2
TC		 1309 aarch64_operand_error *);
1310
1311extern void
1312init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
36f4aab1 1313
a06ea964
NC		 1314/* Given an operand qualifier, return the expected data element size
1315 of a qualified operand. */
1316extern unsigned char
1317aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1318
1319extern enum aarch64_operand_class
1320aarch64_get_operand_class (enum aarch64_opnd);
1321
1322extern const char *
1323aarch64_get_operand_name (enum aarch64_opnd);
1324
1325extern const char *
1326aarch64_get_operand_desc (enum aarch64_opnd);
1327
e950b345
RS		 1328extern bfd_boolean
1329aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1330
a06ea964
NC		 1331#ifdef DEBUG_AARCH64
1332extern int debug_dump;
1333
1334extern void
1335aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1336
1337#define DEBUG_TRACE(M, ...) \
1338 { \
1339 if (debug_dump) \
1340 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1341 }
1342
1343#define DEBUG_TRACE_IF(C, M, ...) \
1344 { \
1345 if (debug_dump && (C)) \
1346 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1347 }
1348#else /* !DEBUG_AARCH64 */
1349#define DEBUG_TRACE(M, ...) ;
1350#define DEBUG_TRACE_IF(C, M, ...) ;
1351#endif /* DEBUG_AARCH64 */
1352
245d2e3f
RS		 1353extern const char *const aarch64_sve_pattern_array[32];
1354extern const char *const aarch64_sve_prfop_array[16];
1355
d3e12b29
YQ		 1356#ifdef __cplusplus
1357}
1358#endif
1359
a06ea964 1360#endif /* OPCODE_AARCH64_H */
A mirror of the official binutils-gdb repository