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Simplify the psymbol hash function
[thirdparty/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
2571583a 3 Copyright (C) 2009-2017 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
c0e7cef7
NC		 40#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
41#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
b6b9ca0c
TC		 42#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
43#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
44#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
a06ea964 45#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 46#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 47#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 48#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
49#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
50#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 51#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 52#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 53#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 54#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 55#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 56#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 57#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 58#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 59#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 60#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
d74d4880 61#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
f482d304 62#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
65a55fbb 63#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
a06ea964
NC		 64
65/* Architectures are the sum of the base and extensions. */
66#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
67 AARCH64_FEATURE_FP \
68 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 69#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
70 AARCH64_FEATURE_CRC \
250aafa4 71 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 72 | AARCH64_FEATURE_LSE \
73 | AARCH64_FEATURE_PAN \
74 | AARCH64_FEATURE_LOR \
75 | AARCH64_FEATURE_RDMA)
1924ff75 76#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 77 AARCH64_FEATURE_V8_2 \
1924ff75
SN		 78 | AARCH64_FEATURE_RAS)
79#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 80 AARCH64_FEATURE_V8_3 \
f482d304
RS		 81 | AARCH64_FEATURE_RCPC \
82 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c
TC		 83#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
84 AARCH64_FEATURE_V8_4)
88f0ea34 85
a06ea964
NC		 86#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
87#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
88
89/* CPU-specific features. */
21b81e67 90typedef unsigned long long aarch64_feature_set;
a06ea964 91
93d8990c
SN		 92#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
93 ((~(CPU) & (FEAT)) == 0)
94
95#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 96 (((CPU) & (FEAT)) != 0)
97
93d8990c
SN		 98#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
99 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
100
a06ea964
NC		 101#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
102 do \
103 { \
104 (TARG) = (F1) | (F2); \
105 } \
106 while (0)
107
108#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
109 do \
110 { \
111 (TARG) = (F1) &~ (F2); \
112 } \
113 while (0)
114
115#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
116
a06ea964
NC		 117enum aarch64_operand_class
118{
119 AARCH64_OPND_CLASS_NIL,
120 AARCH64_OPND_CLASS_INT_REG,
121 AARCH64_OPND_CLASS_MODIFIED_REG,
122 AARCH64_OPND_CLASS_FP_REG,
123 AARCH64_OPND_CLASS_SIMD_REG,
124 AARCH64_OPND_CLASS_SIMD_ELEMENT,
125 AARCH64_OPND_CLASS_SISD_REG,
126 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 127 AARCH64_OPND_CLASS_SVE_REG,
128 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 129 AARCH64_OPND_CLASS_ADDRESS,
130 AARCH64_OPND_CLASS_IMMEDIATE,
131 AARCH64_OPND_CLASS_SYSTEM,
68a64283 132 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 133};
134
135/* Operand code that helps both parsing and coding.
136 Keep AARCH64_OPERANDS synced. */
137
138enum aarch64_opnd
139{
140 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
141
142 AARCH64_OPND_Rd, /* Integer register as destination. */
143 AARCH64_OPND_Rn, /* Integer register as source. */
144 AARCH64_OPND_Rm, /* Integer register as source. */
145 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
146 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
147 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
148 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
149 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
150
151 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
152 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 153 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 154 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 155 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
156 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
157
158 AARCH64_OPND_Fd, /* Floating-point Fd. */
159 AARCH64_OPND_Fn, /* Floating-point Fn. */
160 AARCH64_OPND_Fm, /* Floating-point Fm. */
161 AARCH64_OPND_Fa, /* Floating-point Fa. */
162 AARCH64_OPND_Ft, /* Floating-point Ft. */
163 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
164
165 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
166 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
167 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
168
169 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
170 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
171 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
172 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
173 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
174 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
175 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
176 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
177 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
178 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
179 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
180 structure to all lanes. */
181 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
182
a6a51754
RL		 183 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
184 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 185
186 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
187 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
188 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
189 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
190 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
191 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
192 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
193 (no encoding). */
194 AARCH64_OPND_IMM0, /* Immediate for #0. */
195 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
196 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
197 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
198 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
199 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
200 AARCH64_OPND_IMM, /* Immediate. */
201 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
202 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
203 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
204 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
205 AARCH64_OPND_BIT_NUM, /* Immediate. */
206 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
207 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 208 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 209 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
210 each condition flag. */
211
212 AARCH64_OPND_LIMM, /* Logical Immediate. */
213 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
214 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
215 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
216 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 217 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
218 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
219 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 220
221 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 222 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 223
224 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
225 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
226 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
227 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
228 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
229
230 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
231 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
232 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
233 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
234 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
235 negative or unaligned and there is
236 no writeback allowed. This operand code
237 is only used to support the programmer-
238 friendly feature of using LDR/STR as the
239 the mnemonic name for LDUR/STUR instructions
240 wherever there is no ambiguity. */
3f06e550 241 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
a06ea964
NC		 242 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
243 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
244 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
245
246 AARCH64_OPND_SYSREG, /* System register operand. */
247 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
248 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
249 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
250 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
251 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
252 AARCH64_OPND_BARRIER, /* Barrier operand. */
253 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
254 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 255 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
f11ad6bc 256
582e12bf 257 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
98907a70
RS		 258 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
259 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
260 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
261 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
262 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
263 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 264 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
265 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
266 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
267 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
268 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
269 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
270 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
271 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
272 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
273 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
274 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
275 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
276 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
277 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
278 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
279 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
280 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
281 Bit 14 controls S/U choice. */
282 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
283 Bit 22 controls S/U choice. */
284 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
285 Bit 14 controls S/U choice. */
286 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
287 Bit 22 controls S/U choice. */
288 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
289 Bit 14 controls S/U choice. */
290 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
291 Bit 22 controls S/U choice. */
292 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
293 Bit 14 controls S/U choice. */
294 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
295 Bit 22 controls S/U choice. */
296 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
297 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
298 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
299 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
300 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
301 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
302 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 303 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
304 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 305 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
306 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
307 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
308 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS		 309 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
310 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
e950b345
RS		 311 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
312 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
313 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 314 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 315 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 316 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 317 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
318 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
319 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
320 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
321 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
322 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
323 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
324 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 325 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
326 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 327 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
328 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
329 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
330 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
331 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
332 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
333 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
334 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
335 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
336 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
337 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
338 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 339 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
340 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
341 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
342 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 343 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
344 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
345 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
346 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
347 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS		 348 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
349 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
350 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS		 351 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
352 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
353 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
354 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
355 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
a06ea964
NC		 356};
357
358/* Qualifier constrains an operand. It either specifies a variant of an
359 operand type or limits values available to an operand type.
360
361 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
362
363enum aarch64_opnd_qualifier
364{
365 /* Indicating no further qualification on an operand. */
366 AARCH64_OPND_QLF_NIL,
367
368 /* Qualifying an operand which is a general purpose (integer) register;
369 indicating the operand data size or a specific register. */
370 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
371 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
372 AARCH64_OPND_QLF_WSP, /* WSP. */
373 AARCH64_OPND_QLF_SP, /* SP. */
374
375 /* Qualifying an operand which is a floating-point register, a SIMD
376 vector element or a SIMD vector element list; indicating operand data
377 size or the size of each SIMD vector element in the case of a SIMD
378 vector element list.
379 These qualifiers are also used to qualify an address operand to
380 indicate the size of data element a load/store instruction is
381 accessing.
382 They are also used for the immediate shift operand in e.g. SSHR. Such
383 a use is only for the ease of operand encoding/decoding and qualifier
384 sequence matching; such a use should not be applied widely; use the value
385 constraint qualifiers for immediate operands wherever possible. */
386 AARCH64_OPND_QLF_S_B,
387 AARCH64_OPND_QLF_S_H,
388 AARCH64_OPND_QLF_S_S,
389 AARCH64_OPND_QLF_S_D,
390 AARCH64_OPND_QLF_S_Q,
391
392 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
393 register list; indicating register shape.
394 They are also used for the immediate shift operand in e.g. SSHR. Such
395 a use is only for the ease of operand encoding/decoding and qualifier
396 sequence matching; such a use should not be applied widely; use the value
397 constraint qualifiers for immediate operands wherever possible. */
398 AARCH64_OPND_QLF_V_8B,
399 AARCH64_OPND_QLF_V_16B,
3067d3b9 400 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 401 AARCH64_OPND_QLF_V_4H,
402 AARCH64_OPND_QLF_V_8H,
403 AARCH64_OPND_QLF_V_2S,
404 AARCH64_OPND_QLF_V_4S,
405 AARCH64_OPND_QLF_V_1D,
406 AARCH64_OPND_QLF_V_2D,
407 AARCH64_OPND_QLF_V_1Q,
408
d50c751e
RS		 409 AARCH64_OPND_QLF_P_Z,
410 AARCH64_OPND_QLF_P_M,
411
a06ea964 412 /* Constraint on value. */
a6a51754 413 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 414 AARCH64_OPND_QLF_imm_0_7,
415 AARCH64_OPND_QLF_imm_0_15,
416 AARCH64_OPND_QLF_imm_0_31,
417 AARCH64_OPND_QLF_imm_0_63,
418 AARCH64_OPND_QLF_imm_1_32,
419 AARCH64_OPND_QLF_imm_1_64,
420
421 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
422 or shift-ones. */
423 AARCH64_OPND_QLF_LSL,
424 AARCH64_OPND_QLF_MSL,
425
426 /* Special qualifier helping retrieve qualifier information during the
427 decoding time (currently not in use). */
428 AARCH64_OPND_QLF_RETRIEVE,
429};
430\f
431/* Instruction class. */
432
433enum aarch64_insn_class
434{
435 addsub_carry,
436 addsub_ext,
437 addsub_imm,
438 addsub_shift,
439 asimdall,
440 asimddiff,
441 asimdelem,
442 asimdext,
443 asimdimm,
444 asimdins,
445 asimdmisc,
446 asimdperm,
447 asimdsame,
448 asimdshf,
449 asimdtbl,
450 asisddiff,
451 asisdelem,
452 asisdlse,
453 asisdlsep,
454 asisdlso,
455 asisdlsop,
456 asisdmisc,
457 asisdone,
458 asisdpair,
459 asisdsame,
460 asisdshf,
461 bitfield,
462 branch_imm,
463 branch_reg,
464 compbranch,
465 condbranch,
466 condcmp_imm,
467 condcmp_reg,
468 condsel,
469 cryptoaes,
470 cryptosha2,
471 cryptosha3,
472 dp_1src,
473 dp_2src,
474 dp_3src,
475 exception,
476 extract,
477 float2fix,
478 float2int,
479 floatccmp,
480 floatcmp,
481 floatdp1,
482 floatdp2,
483 floatdp3,
484 floatimm,
485 floatsel,
486 ldst_immpost,
487 ldst_immpre,
488 ldst_imm9, /* immpost or immpre */
3f06e550 489 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 490 ldst_pos,
491 ldst_regoff,
492 ldst_unpriv,
493 ldst_unscaled,
494 ldstexcl,
495 ldstnapair_offs,
496 ldstpair_off,
497 ldstpair_indexed,
498 loadlit,
499 log_imm,
500 log_shift,
ee804238 501 lse_atomic,
a06ea964
NC		 502 movewide,
503 pcreladdr,
504 ic_system,
116b6019
RS		 505 sve_cpy,
506 sve_index,
507 sve_limm,
508 sve_misc,
509 sve_movprfx,
510 sve_pred_zm,
511 sve_shift_pred,
512 sve_shift_unpred,
513 sve_size_bhs,
514 sve_size_bhsd,
515 sve_size_hsd,
516 sve_size_sd,
a06ea964 517 testbranch,
65a55fbb 518 dotproduct,
a06ea964
NC		 519};
520
521/* Opcode enumerators. */
522
523enum aarch64_op
524{
525 OP_NIL,
526 OP_STRB_POS,
527 OP_LDRB_POS,
528 OP_LDRSB_POS,
529 OP_STRH_POS,
530 OP_LDRH_POS,
531 OP_LDRSH_POS,
532 OP_STR_POS,
533 OP_LDR_POS,
534 OP_STRF_POS,
535 OP_LDRF_POS,
536 OP_LDRSW_POS,
537 OP_PRFM_POS,
538
539 OP_STURB,
540 OP_LDURB,
541 OP_LDURSB,
542 OP_STURH,
543 OP_LDURH,
544 OP_LDURSH,
545 OP_STUR,
546 OP_LDUR,
547 OP_STURV,
548 OP_LDURV,
549 OP_LDURSW,
550 OP_PRFUM,
551
552 OP_LDR_LIT,
553 OP_LDRV_LIT,
554 OP_LDRSW_LIT,
555 OP_PRFM_LIT,
556
557 OP_ADD,
558 OP_B,
559 OP_BL,
560
561 OP_MOVN,
562 OP_MOVZ,
563 OP_MOVK,
564
565 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
566 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
567 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
568
569 OP_MOV_V, /* MOV alias for moving vector register. */
570
571 OP_ASR_IMM,
572 OP_LSR_IMM,
573 OP_LSL_IMM,
574
575 OP_BIC,
576
577 OP_UBFX,
578 OP_BFXIL,
579 OP_SBFX,
580 OP_SBFIZ,
581 OP_BFI,
d685192a 582 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 583 OP_UBFIZ,
584 OP_UXTB,
585 OP_UXTH,
586 OP_UXTW,
587
a06ea964
NC		 588 OP_CINC,
589 OP_CINV,
590 OP_CNEG,
591 OP_CSET,
592 OP_CSETM,
593
594 OP_FCVT,
595 OP_FCVTN,
596 OP_FCVTN2,
597 OP_FCVTL,
598 OP_FCVTL2,
599 OP_FCVTXN_S, /* Scalar version. */
600
601 OP_ROR_IMM,
602
e30181a5
YZ		 603 OP_SXTL,
604 OP_SXTL2,
605 OP_UXTL,
606 OP_UXTL2,
607
c0890d26
RS		 608 OP_MOV_P_P,
609 OP_MOV_Z_P_Z,
610 OP_MOV_Z_V,
611 OP_MOV_Z_Z,
612 OP_MOV_Z_Zi,
613 OP_MOVM_P_P_P,
614 OP_MOVS_P_P,
615 OP_MOVZS_P_P_P,
616 OP_MOVZ_P_P_P,
617 OP_NOTS_P_P_P_Z,
618 OP_NOT_P_P_P_Z,
619
c2c4ff8d
SN		 620 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
621
a06ea964
NC		 622 OP_TOTAL_NUM, /* Pseudo. */
623};
624
625/* Maximum number of operands an instruction can have. */
626#define AARCH64_MAX_OPND_NUM 6
627/* Maximum number of qualifier sequences an instruction can have. */
628#define AARCH64_MAX_QLF_SEQ_NUM 10
629/* Operand qualifier typedef; optimized for the size. */
630typedef unsigned char aarch64_opnd_qualifier_t;
631/* Operand qualifier sequence typedef. */
632typedef aarch64_opnd_qualifier_t \
633 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
634
635/* FIXME: improve the efficiency. */
636static inline bfd_boolean
637empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
638{
639 int i;
640 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
641 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
642 return FALSE;
643 return TRUE;
644}
645
646/* This structure holds information for a particular opcode. */
647
648struct aarch64_opcode
649{
650 /* The name of the mnemonic. */
651 const char *name;
652
653 /* The opcode itself. Those bits which will be filled in with
654 operands are zeroes. */
655 aarch64_insn opcode;
656
657 /* The opcode mask. This is used by the disassembler. This is a
658 mask containing ones indicating those bits which must match the
659 opcode field, and zeroes indicating those bits which need not
660 match (and are presumably filled in by operands). */
661 aarch64_insn mask;
662
663 /* Instruction class. */
664 enum aarch64_insn_class iclass;
665
666 /* Enumerator identifier. */
667 enum aarch64_op op;
668
669 /* Which architecture variant provides this instruction. */
670 const aarch64_feature_set *avariant;
671
672 /* An array of operand codes. Each code is an index into the
673 operand table. They appear in the order which the operands must
674 appear in assembly code, and are terminated by a zero. */
675 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
676
677 /* A list of operand qualifier code sequence. Each operand qualifier
678 code qualifies the corresponding operand code. Each operand
679 qualifier sequence specifies a valid opcode variant and related
680 constraint on operands. */
681 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
682
683 /* Flags providing information about this instruction */
684 uint32_t flags;
4bd13cde 685
0c608d6b
RS		 686 /* If nonzero, this operand and operand 0 are both registers and
687 are required to have the same register number. */
688 unsigned char tied_operand;
689
4bd13cde
NC		 690 /* If non-NULL, a function to verify that a given instruction is valid. */
691 bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
a06ea964
NC		 692};
693
694typedef struct aarch64_opcode aarch64_opcode;
695
696/* Table describing all the AArch64 opcodes. */
697extern aarch64_opcode aarch64_opcode_table[];
698
699/* Opcode flags. */
700#define F_ALIAS (1 << 0)
701#define F_HAS_ALIAS (1 << 1)
702/* Disassembly preference priority 1-3 (the larger the higher). If nothing
703 is specified, it is the priority 0 by default, i.e. the lowest priority. */
704#define F_P1 (1 << 2)
705#define F_P2 (2 << 2)
706#define F_P3 (3 << 2)
707/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
708#define F_COND (1 << 4)
709/* Instruction has the field of 'sf'. */
710#define F_SF (1 << 5)
711/* Instruction has the field of 'size:Q'. */
712#define F_SIZEQ (1 << 6)
713/* Floating-point instruction has the field of 'type'. */
714#define F_FPTYPE (1 << 7)
715/* AdvSIMD scalar instruction has the field of 'size'. */
716#define F_SSIZE (1 << 8)
717/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
718#define F_T (1 << 9)
719/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
720#define F_GPRSIZE_IN_Q (1 << 10)
721/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
722#define F_LDS_SIZE (1 << 11)
723/* Optional operand; assume maximum of 1 operand can be optional. */
724#define F_OPD0_OPT (1 << 12)
725#define F_OPD1_OPT (2 << 12)
726#define F_OPD2_OPT (3 << 12)
727#define F_OPD3_OPT (4 << 12)
728#define F_OPD4_OPT (5 << 12)
729/* Default value for the optional operand when omitted from the assembly. */
730#define F_DEFAULT(X) (((X) & 0x1f) << 15)
731/* Instruction that is an alias of another instruction needs to be
732 encoded/decoded by converting it to/from the real form, followed by
733 the encoding/decoding according to the rules of the real opcode.
734 This compares to the direct coding using the alias's information.
735 N.B. this flag requires F_ALIAS to be used together. */
736#define F_CONV (1 << 20)
737/* Use together with F_ALIAS to indicate an alias opcode is a programmer
738 friendly pseudo instruction available only in the assembly code (thus will
739 not show up in the disassembly). */
740#define F_PSEUDO (1 << 21)
741/* Instruction has miscellaneous encoding/decoding rules. */
742#define F_MISC (1 << 22)
743/* Instruction has the field of 'N'; used in conjunction with F_SF. */
744#define F_N (1 << 23)
745/* Opcode dependent field. */
746#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 747/* Instruction has the field of 'sz'. */
748#define F_LSE_SZ (1 << 27)
4989adac
RS		 749/* Require an exact qualifier match, even for NIL qualifiers. */
750#define F_STRICT (1ULL << 28)
751/* Next bit is 29. */
a06ea964
NC		 752
753static inline bfd_boolean
754alias_opcode_p (const aarch64_opcode *opcode)
755{
756 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
757}
758
759static inline bfd_boolean
760opcode_has_alias (const aarch64_opcode *opcode)
761{
762 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
763}
764
765/* Priority for disassembling preference. */
766static inline int
767opcode_priority (const aarch64_opcode *opcode)
768{
769 return (opcode->flags >> 2) & 0x3;
770}
771
772static inline bfd_boolean
773pseudo_opcode_p (const aarch64_opcode *opcode)
774{
775 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
776}
777
778static inline bfd_boolean
779optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
780{
781 return (((opcode->flags >> 12) & 0x7) == idx + 1)
782 ? TRUE : FALSE;
783}
784
785static inline aarch64_insn
786get_optional_operand_default_value (const aarch64_opcode *opcode)
787{
788 return (opcode->flags >> 15) & 0x1f;
789}
790
791static inline unsigned int
792get_opcode_dependent_value (const aarch64_opcode *opcode)
793{
794 return (opcode->flags >> 24) & 0x7;
795}
796
797static inline bfd_boolean
798opcode_has_special_coder (const aarch64_opcode *opcode)
799{
ee804238 800 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 801 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
802 : FALSE;
803}
804\f
805struct aarch64_name_value_pair
806{
807 const char * name;
808 aarch64_insn value;
809};
810
811extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 812extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
813extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 814extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 815
49eec193
YZ		 816typedef struct
817{
818 const char * name;
819 aarch64_insn value;
820 uint32_t flags;
821} aarch64_sys_reg;
822
823extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 824extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 825extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 826extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
827 const aarch64_sys_reg *);
828extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
829 const aarch64_sys_reg *);
49eec193 830
a06ea964
NC		 831typedef struct
832{
875880c6 833 const char *name;
a06ea964 834 uint32_t value;
ea2deeec 835 uint32_t flags ;
a06ea964
NC		 836} aarch64_sys_ins_reg;
837
ea2deeec 838extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 839extern bfd_boolean
840aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
841 const aarch64_sys_ins_reg *);
ea2deeec 842
a06ea964
NC		 843extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
844extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
845extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
846extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
847
848/* Shift/extending operator kinds.
849 N.B. order is important; keep aarch64_operand_modifiers synced. */
850enum aarch64_modifier_kind
851{
852 AARCH64_MOD_NONE,
853 AARCH64_MOD_MSL,
854 AARCH64_MOD_ROR,
855 AARCH64_MOD_ASR,
856 AARCH64_MOD_LSR,
857 AARCH64_MOD_LSL,
858 AARCH64_MOD_UXTB,
859 AARCH64_MOD_UXTH,
860 AARCH64_MOD_UXTW,
861 AARCH64_MOD_UXTX,
862 AARCH64_MOD_SXTB,
863 AARCH64_MOD_SXTH,
864 AARCH64_MOD_SXTW,
865 AARCH64_MOD_SXTX,
2442d846 866 AARCH64_MOD_MUL,
98907a70 867 AARCH64_MOD_MUL_VL,
a06ea964
NC		 868};
869
870bfd_boolean
871aarch64_extend_operator_p (enum aarch64_modifier_kind);
872
873enum aarch64_modifier_kind
874aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
875/* Condition. */
876
877typedef struct
878{
879 /* A list of names with the first one as the disassembly preference;
880 terminated by NULL if fewer than 3. */
bb7eff52 881 const char *names[4];
a06ea964
NC		 882 aarch64_insn value;
883} aarch64_cond;
884
885extern const aarch64_cond aarch64_conds[16];
886
887const aarch64_cond* get_cond_from_value (aarch64_insn value);
888const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
889\f
890/* Structure representing an operand. */
891
892struct aarch64_opnd_info
893{
894 enum aarch64_opnd type;
895 aarch64_opnd_qualifier_t qualifier;
896 int idx;
897
898 union
899 {
900 struct
901 {
902 unsigned regno;
903 } reg;
904 struct
905 {
dab26bf4
RS		 906 unsigned int regno;
907 int64_t index;
a06ea964
NC		 908 } reglane;
909 /* e.g. LVn. */
910 struct
911 {
912 unsigned first_regno : 5;
913 unsigned num_regs : 3;
914 /* 1 if it is a list of reg element. */
915 unsigned has_index : 1;
916 /* Lane index; valid only when has_index is 1. */
dab26bf4 917 int64_t index;
a06ea964
NC		 918 } reglist;
919 /* e.g. immediate or pc relative address offset. */
920 struct
921 {
922 int64_t value;
923 unsigned is_fp : 1;
924 } imm;
925 /* e.g. address in STR (register offset). */
926 struct
927 {
928 unsigned base_regno;
929 struct
930 {
931 union
932 {
933 int imm;
934 unsigned regno;
935 };
936 unsigned is_reg;
937 } offset;
938 unsigned pcrel : 1; /* PC-relative. */
939 unsigned writeback : 1;
940 unsigned preind : 1; /* Pre-indexed. */
941 unsigned postind : 1; /* Post-indexed. */
942 } addr;
943 const aarch64_cond *cond;
944 /* The encoding of the system register. */
945 aarch64_insn sysreg;
946 /* The encoding of the PSTATE field. */
947 aarch64_insn pstatefield;
948 const aarch64_sys_ins_reg *sysins_op;
949 const struct aarch64_name_value_pair *barrier;
9ed608f9 950 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 951 const struct aarch64_name_value_pair *prfop;
952 };
953
954 /* Operand shifter; in use when the operand is a register offset address,
955 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
956 struct
957 {
958 enum aarch64_modifier_kind kind;
a06ea964
NC		 959 unsigned operator_present: 1; /* Only valid during encoding. */
960 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
961 unsigned amount_present: 1;
2442d846 962 int64_t amount;
a06ea964
NC		 963 } shifter;
964
965 unsigned skip:1; /* Operand is not completed if there is a fixup needed
966 to be done on it. In some (but not all) of these
967 cases, we need to tell libopcodes to skip the
968 constraint checking and the encoding for this
969 operand, so that the libopcodes can pick up the
970 right opcode before the operand is fixed-up. This
971 flag should only be used during the
972 assembling/encoding. */
973 unsigned present:1; /* Whether this operand is present in the assembly
974 line; not used during the disassembly. */
975};
976
977typedef struct aarch64_opnd_info aarch64_opnd_info;
978
979/* Structure representing an instruction.
980
981 It is used during both the assembling and disassembling. The assembler
982 fills an aarch64_inst after a successful parsing and then passes it to the
983 encoding routine to do the encoding. During the disassembling, the
984 disassembler calls the decoding routine to decode a binary instruction; on a
985 successful return, such a structure will be filled with information of the
986 instruction; then the disassembler uses the information to print out the
987 instruction. */
988
989struct aarch64_inst
990{
991 /* The value of the binary instruction. */
992 aarch64_insn value;
993
994 /* Corresponding opcode entry. */
995 const aarch64_opcode *opcode;
996
997 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
998 const aarch64_cond *cond;
999
1000 /* Operands information. */
1001 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1002};
1003
1004typedef struct aarch64_inst aarch64_inst;
1005\f
1006/* Diagnosis related declaration and interface. */
1007
1008/* Operand error kind enumerators.
1009
1010 AARCH64_OPDE_RECOVERABLE
1011 Less severe error found during the parsing, very possibly because that
1012 GAS has picked up a wrong instruction template for the parsing.
1013
1014 AARCH64_OPDE_SYNTAX_ERROR
1015 General syntax error; it can be either a user error, or simply because
1016 that GAS is trying a wrong instruction template.
1017
1018 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1019 Definitely a user syntax error.
1020
1021 AARCH64_OPDE_INVALID_VARIANT
1022 No syntax error, but the operands are not a valid combination, e.g.
1023 FMOV D0,S0
1024
0c608d6b
RS		 1025 AARCH64_OPDE_UNTIED_OPERAND
1026 The asm failed to use the same register for a destination operand
1027 and a tied source operand.
1028
a06ea964
NC		 1029 AARCH64_OPDE_OUT_OF_RANGE
1030 Error about some immediate value out of a valid range.
1031
1032 AARCH64_OPDE_UNALIGNED
1033 Error about some immediate value not properly aligned (i.e. not being a
1034 multiple times of a certain value).
1035
1036 AARCH64_OPDE_REG_LIST
1037 Error about the register list operand having unexpected number of
1038 registers.
1039
1040 AARCH64_OPDE_OTHER_ERROR
1041 Error of the highest severity and used for any severe issue that does not
1042 fall into any of the above categories.
1043
1044 The enumerators are only interesting to GAS. They are declared here (in
1045 libopcodes) because that some errors are detected (and then notified to GAS)
1046 by libopcodes (rather than by GAS solely).
1047
1048 The first three errors are only deteced by GAS while the
1049 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1050 only libopcodes has the information about the valid variants of each
1051 instruction.
1052
1053 The enumerators have an increasing severity. This is helpful when there are
1054 multiple instruction templates available for a given mnemonic name (e.g.
1055 FMOV); this mechanism will help choose the most suitable template from which
1056 the generated diagnostics can most closely describe the issues, if any. */
1057
1058enum aarch64_operand_error_kind
1059{
1060 AARCH64_OPDE_NIL,
1061 AARCH64_OPDE_RECOVERABLE,
1062 AARCH64_OPDE_SYNTAX_ERROR,
1063 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1064 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1065 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1066 AARCH64_OPDE_OUT_OF_RANGE,
1067 AARCH64_OPDE_UNALIGNED,
1068 AARCH64_OPDE_REG_LIST,
1069 AARCH64_OPDE_OTHER_ERROR
1070};
1071
1072/* N.B. GAS assumes that this structure work well with shallow copy. */
1073struct aarch64_operand_error
1074{
1075 enum aarch64_operand_error_kind kind;
1076 int index;
1077 const char *error;
1078 int data[3]; /* Some data for extra information. */
1079};
1080
1081typedef struct aarch64_operand_error aarch64_operand_error;
1082
1083/* Encoding entrypoint. */
1084
1085extern int
1086aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1087 aarch64_insn *, aarch64_opnd_qualifier_t *,
1088 aarch64_operand_error *);
1089
1090extern const aarch64_opcode *
1091aarch64_replace_opcode (struct aarch64_inst *,
1092 const aarch64_opcode *);
1093
1094/* Given the opcode enumerator OP, return the pointer to the corresponding
1095 opcode entry. */
1096
1097extern const aarch64_opcode *
1098aarch64_get_opcode (enum aarch64_op);
1099
1100/* Generate the string representation of an operand. */
1101extern void
1102aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1103 const aarch64_opnd_info *, int, int *, bfd_vma *);
1104
1105/* Miscellaneous interface. */
1106
1107extern int
1108aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1109
1110extern aarch64_opnd_qualifier_t
1111aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1112 const aarch64_opnd_qualifier_t, int);
1113
1114extern int
1115aarch64_num_of_operands (const aarch64_opcode *);
1116
1117extern int
1118aarch64_stack_pointer_p (const aarch64_opnd_info *);
1119
e141d84e
YQ		 1120extern int
1121aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1122
36f4aab1 1123extern int
43cdf5ae 1124aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
36f4aab1 1125
a06ea964
NC		 1126/* Given an operand qualifier, return the expected data element size
1127 of a qualified operand. */
1128extern unsigned char
1129aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1130
1131extern enum aarch64_operand_class
1132aarch64_get_operand_class (enum aarch64_opnd);
1133
1134extern const char *
1135aarch64_get_operand_name (enum aarch64_opnd);
1136
1137extern const char *
1138aarch64_get_operand_desc (enum aarch64_opnd);
1139
e950b345
RS		 1140extern bfd_boolean
1141aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1142
a06ea964
NC		 1143#ifdef DEBUG_AARCH64
1144extern int debug_dump;
1145
1146extern void
1147aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1148
1149#define DEBUG_TRACE(M, ...) \
1150 { \
1151 if (debug_dump) \
1152 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1153 }
1154
1155#define DEBUG_TRACE_IF(C, M, ...) \
1156 { \
1157 if (debug_dump && (C)) \
1158 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1159 }
1160#else /* !DEBUG_AARCH64 */
1161#define DEBUG_TRACE(M, ...) ;
1162#define DEBUG_TRACE_IF(C, M, ...) ;
1163#endif /* DEBUG_AARCH64 */
1164
245d2e3f
RS		 1165extern const char *const aarch64_sve_pattern_array[32];
1166extern const char *const aarch64_sve_prfop_array[16];
1167
d3e12b29
YQ		 1168#ifdef __cplusplus
1169}
1170#endif
1171
a06ea964 1172#endif /* OPCODE_AARCH64_H */
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