]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - include/opcode/aarch64.h
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Automatic date update in version.in
[thirdparty/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
219d1afa 3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
c0e7cef7
NC		 40#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
41#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
b6b9ca0c
TC		 42#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
43#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
44#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
a06ea964 45#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 46#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 47#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 48#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
49#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
50#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 51#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 52#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 53#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 54#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 55#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 56#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 57#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 58#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 59#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 60#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
d74d4880 61#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
f482d304 62#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
65a55fbb 63#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
d0f7791c 64#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
a06ea964
NC		 65
66/* Architectures are the sum of the base and extensions. */
67#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
68 AARCH64_FEATURE_FP \
69 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 70#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
71 AARCH64_FEATURE_CRC \
250aafa4 72 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 73 | AARCH64_FEATURE_LSE \
74 | AARCH64_FEATURE_PAN \
75 | AARCH64_FEATURE_LOR \
76 | AARCH64_FEATURE_RDMA)
1924ff75 77#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 78 AARCH64_FEATURE_V8_2 \
1924ff75
SN		 79 | AARCH64_FEATURE_RAS)
80#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 81 AARCH64_FEATURE_V8_3 \
f482d304
RS		 82 | AARCH64_FEATURE_RCPC \
83 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c 84#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
981b557a 85 AARCH64_FEATURE_V8_4 \
d0f7791c
TC		 86 | AARCH64_FEATURE_DOTPROD \
87 | AARCH64_FEATURE_F16_FML)
88f0ea34 88
a06ea964
NC		 89#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
90#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
91
92/* CPU-specific features. */
21b81e67 93typedef unsigned long long aarch64_feature_set;
a06ea964 94
93d8990c
SN		 95#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
96 ((~(CPU) & (FEAT)) == 0)
97
98#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 99 (((CPU) & (FEAT)) != 0)
100
93d8990c
SN		 101#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
102 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
103
a06ea964
NC		 104#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
105 do \
106 { \
107 (TARG) = (F1) | (F2); \
108 } \
109 while (0)
110
111#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
112 do \
113 { \
114 (TARG) = (F1) &~ (F2); \
115 } \
116 while (0)
117
118#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
119
a06ea964
NC		 120enum aarch64_operand_class
121{
122 AARCH64_OPND_CLASS_NIL,
123 AARCH64_OPND_CLASS_INT_REG,
124 AARCH64_OPND_CLASS_MODIFIED_REG,
125 AARCH64_OPND_CLASS_FP_REG,
126 AARCH64_OPND_CLASS_SIMD_REG,
127 AARCH64_OPND_CLASS_SIMD_ELEMENT,
128 AARCH64_OPND_CLASS_SISD_REG,
129 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 130 AARCH64_OPND_CLASS_SVE_REG,
131 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 132 AARCH64_OPND_CLASS_ADDRESS,
133 AARCH64_OPND_CLASS_IMMEDIATE,
134 AARCH64_OPND_CLASS_SYSTEM,
68a64283 135 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 136};
137
138/* Operand code that helps both parsing and coding.
139 Keep AARCH64_OPERANDS synced. */
140
141enum aarch64_opnd
142{
143 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
144
145 AARCH64_OPND_Rd, /* Integer register as destination. */
146 AARCH64_OPND_Rn, /* Integer register as source. */
147 AARCH64_OPND_Rm, /* Integer register as source. */
148 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
149 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
150 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
151 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
152 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
153
154 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
155 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 156 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 157 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 158 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
159 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
160
161 AARCH64_OPND_Fd, /* Floating-point Fd. */
162 AARCH64_OPND_Fn, /* Floating-point Fn. */
163 AARCH64_OPND_Fm, /* Floating-point Fm. */
164 AARCH64_OPND_Fa, /* Floating-point Fa. */
165 AARCH64_OPND_Ft, /* Floating-point Ft. */
166 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
167
168 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
169 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
170 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
171
f42f1a1d 172 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
a06ea964
NC		 173 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
174 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
175 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
176 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
177 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
178 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
179 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
180 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
181 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
182 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
183 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
184 structure to all lanes. */
185 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
186
a6a51754
RL		 187 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
188 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 189
190 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
f42f1a1d 191 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
a06ea964
NC		 192 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
193 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
194 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
195 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
196 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
197 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
198 (no encoding). */
199 AARCH64_OPND_IMM0, /* Immediate for #0. */
200 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
201 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
202 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
203 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
204 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
205 AARCH64_OPND_IMM, /* Immediate. */
f42f1a1d 206 AARCH64_OPND_IMM_2, /* Immediate. */
a06ea964
NC		 207 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
208 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
209 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
210 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
211 AARCH64_OPND_BIT_NUM, /* Immediate. */
212 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
213 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 214 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 215 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
216 each condition flag. */
217
218 AARCH64_OPND_LIMM, /* Logical Immediate. */
219 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
220 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
221 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
222 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 223 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
224 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
225 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 226
227 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 228 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 229
230 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
231 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
232 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
233 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
234 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
235
236 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
237 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
238 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
239 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
240 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
241 negative or unaligned and there is
242 no writeback allowed. This operand code
243 is only used to support the programmer-
244 friendly feature of using LDR/STR as the
245 the mnemonic name for LDUR/STUR instructions
246 wherever there is no ambiguity. */
3f06e550 247 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
a06ea964
NC		 248 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
249 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
f42f1a1d 250 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
a06ea964
NC		 251 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
252
253 AARCH64_OPND_SYSREG, /* System register operand. */
254 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
255 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
256 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
257 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
258 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
259 AARCH64_OPND_BARRIER, /* Barrier operand. */
260 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
261 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 262 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
f11ad6bc 263
582e12bf 264 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
98907a70
RS		 265 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
266 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
267 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
268 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
269 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
270 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 271 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
272 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
273 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
274 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
c8d59609 275 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
4df068de
RS		 276 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
277 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
278 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
279 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
280 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
281 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
282 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
283 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
284 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
285 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
286 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
287 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
288 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
289 Bit 14 controls S/U choice. */
290 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
291 Bit 22 controls S/U choice. */
292 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
293 Bit 14 controls S/U choice. */
294 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
295 Bit 22 controls S/U choice. */
296 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
297 Bit 14 controls S/U choice. */
298 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
299 Bit 22 controls S/U choice. */
300 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
301 Bit 14 controls S/U choice. */
302 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
303 Bit 22 controls S/U choice. */
304 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
305 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
306 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
307 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
308 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
309 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
310 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 311 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
312 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 313 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
314 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
315 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
316 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS		 317 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
318 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
e950b345
RS		 319 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
320 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
321 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 322 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 323 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 324 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 325 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
326 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
327 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
328 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
329 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
330 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
331 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
332 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 333 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
334 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 335 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
336 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
337 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
338 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
339 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
340 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
341 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
342 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
343 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
344 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
345 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
346 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 347 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
348 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
349 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
350 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 351 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
352 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
353 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
354 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
355 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS		 356 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
357 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
358 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS		 359 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
360 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
361 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
362 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
363 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
f42f1a1d 364 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
a06ea964
NC		 365};
366
367/* Qualifier constrains an operand. It either specifies a variant of an
368 operand type or limits values available to an operand type.
369
370 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
371
372enum aarch64_opnd_qualifier
373{
374 /* Indicating no further qualification on an operand. */
375 AARCH64_OPND_QLF_NIL,
376
377 /* Qualifying an operand which is a general purpose (integer) register;
378 indicating the operand data size or a specific register. */
379 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
380 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
381 AARCH64_OPND_QLF_WSP, /* WSP. */
382 AARCH64_OPND_QLF_SP, /* SP. */
383
384 /* Qualifying an operand which is a floating-point register, a SIMD
385 vector element or a SIMD vector element list; indicating operand data
386 size or the size of each SIMD vector element in the case of a SIMD
387 vector element list.
388 These qualifiers are also used to qualify an address operand to
389 indicate the size of data element a load/store instruction is
390 accessing.
391 They are also used for the immediate shift operand in e.g. SSHR. Such
392 a use is only for the ease of operand encoding/decoding and qualifier
393 sequence matching; such a use should not be applied widely; use the value
394 constraint qualifiers for immediate operands wherever possible. */
395 AARCH64_OPND_QLF_S_B,
396 AARCH64_OPND_QLF_S_H,
397 AARCH64_OPND_QLF_S_S,
398 AARCH64_OPND_QLF_S_D,
399 AARCH64_OPND_QLF_S_Q,
00c2093f
TC		 400 /* This type qualifier has a special meaning in that it means that 4 x 1 byte
401 are selected by the instruction. Other than that it has no difference
402 with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical
403 reasons and is an exception from normal AArch64 disassembly scheme. */
404 AARCH64_OPND_QLF_S_4B,
a06ea964
NC		 405
406 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
407 register list; indicating register shape.
408 They are also used for the immediate shift operand in e.g. SSHR. Such
409 a use is only for the ease of operand encoding/decoding and qualifier
410 sequence matching; such a use should not be applied widely; use the value
411 constraint qualifiers for immediate operands wherever possible. */
a3b3345a 412 AARCH64_OPND_QLF_V_4B,
a06ea964
NC		 413 AARCH64_OPND_QLF_V_8B,
414 AARCH64_OPND_QLF_V_16B,
3067d3b9 415 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 416 AARCH64_OPND_QLF_V_4H,
417 AARCH64_OPND_QLF_V_8H,
418 AARCH64_OPND_QLF_V_2S,
419 AARCH64_OPND_QLF_V_4S,
420 AARCH64_OPND_QLF_V_1D,
421 AARCH64_OPND_QLF_V_2D,
422 AARCH64_OPND_QLF_V_1Q,
423
d50c751e
RS		 424 AARCH64_OPND_QLF_P_Z,
425 AARCH64_OPND_QLF_P_M,
426
a06ea964 427 /* Constraint on value. */
a6a51754 428 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 429 AARCH64_OPND_QLF_imm_0_7,
430 AARCH64_OPND_QLF_imm_0_15,
431 AARCH64_OPND_QLF_imm_0_31,
432 AARCH64_OPND_QLF_imm_0_63,
433 AARCH64_OPND_QLF_imm_1_32,
434 AARCH64_OPND_QLF_imm_1_64,
435
436 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
437 or shift-ones. */
438 AARCH64_OPND_QLF_LSL,
439 AARCH64_OPND_QLF_MSL,
440
441 /* Special qualifier helping retrieve qualifier information during the
442 decoding time (currently not in use). */
443 AARCH64_OPND_QLF_RETRIEVE,
444};
445\f
446/* Instruction class. */
447
448enum aarch64_insn_class
449{
450 addsub_carry,
451 addsub_ext,
452 addsub_imm,
453 addsub_shift,
454 asimdall,
455 asimddiff,
456 asimdelem,
457 asimdext,
458 asimdimm,
459 asimdins,
460 asimdmisc,
461 asimdperm,
462 asimdsame,
463 asimdshf,
464 asimdtbl,
465 asisddiff,
466 asisdelem,
467 asisdlse,
468 asisdlsep,
469 asisdlso,
470 asisdlsop,
471 asisdmisc,
472 asisdone,
473 asisdpair,
474 asisdsame,
475 asisdshf,
476 bitfield,
477 branch_imm,
478 branch_reg,
479 compbranch,
480 condbranch,
481 condcmp_imm,
482 condcmp_reg,
483 condsel,
484 cryptoaes,
485 cryptosha2,
486 cryptosha3,
487 dp_1src,
488 dp_2src,
489 dp_3src,
490 exception,
491 extract,
492 float2fix,
493 float2int,
494 floatccmp,
495 floatcmp,
496 floatdp1,
497 floatdp2,
498 floatdp3,
499 floatimm,
500 floatsel,
501 ldst_immpost,
502 ldst_immpre,
503 ldst_imm9, /* immpost or immpre */
3f06e550 504 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 505 ldst_pos,
506 ldst_regoff,
507 ldst_unpriv,
508 ldst_unscaled,
509 ldstexcl,
510 ldstnapair_offs,
511 ldstpair_off,
512 ldstpair_indexed,
513 loadlit,
514 log_imm,
515 log_shift,
ee804238 516 lse_atomic,
a06ea964
NC		 517 movewide,
518 pcreladdr,
519 ic_system,
116b6019
RS		 520 sve_cpy,
521 sve_index,
522 sve_limm,
523 sve_misc,
524 sve_movprfx,
525 sve_pred_zm,
526 sve_shift_pred,
527 sve_shift_unpred,
528 sve_size_bhs,
529 sve_size_bhsd,
530 sve_size_hsd,
531 sve_size_sd,
a06ea964 532 testbranch,
f42f1a1d
TC		 533 cryptosm3,
534 cryptosm4,
65a55fbb 535 dotproduct,
a06ea964
NC		 536};
537
538/* Opcode enumerators. */
539
540enum aarch64_op
541{
542 OP_NIL,
543 OP_STRB_POS,
544 OP_LDRB_POS,
545 OP_LDRSB_POS,
546 OP_STRH_POS,
547 OP_LDRH_POS,
548 OP_LDRSH_POS,
549 OP_STR_POS,
550 OP_LDR_POS,
551 OP_STRF_POS,
552 OP_LDRF_POS,
553 OP_LDRSW_POS,
554 OP_PRFM_POS,
555
556 OP_STURB,
557 OP_LDURB,
558 OP_LDURSB,
559 OP_STURH,
560 OP_LDURH,
561 OP_LDURSH,
562 OP_STUR,
563 OP_LDUR,
564 OP_STURV,
565 OP_LDURV,
566 OP_LDURSW,
567 OP_PRFUM,
568
569 OP_LDR_LIT,
570 OP_LDRV_LIT,
571 OP_LDRSW_LIT,
572 OP_PRFM_LIT,
573
574 OP_ADD,
575 OP_B,
576 OP_BL,
577
578 OP_MOVN,
579 OP_MOVZ,
580 OP_MOVK,
581
582 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
583 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
584 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
585
586 OP_MOV_V, /* MOV alias for moving vector register. */
587
588 OP_ASR_IMM,
589 OP_LSR_IMM,
590 OP_LSL_IMM,
591
592 OP_BIC,
593
594 OP_UBFX,
595 OP_BFXIL,
596 OP_SBFX,
597 OP_SBFIZ,
598 OP_BFI,
d685192a 599 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 600 OP_UBFIZ,
601 OP_UXTB,
602 OP_UXTH,
603 OP_UXTW,
604
a06ea964
NC		 605 OP_CINC,
606 OP_CINV,
607 OP_CNEG,
608 OP_CSET,
609 OP_CSETM,
610
611 OP_FCVT,
612 OP_FCVTN,
613 OP_FCVTN2,
614 OP_FCVTL,
615 OP_FCVTL2,
616 OP_FCVTXN_S, /* Scalar version. */
617
618 OP_ROR_IMM,
619
e30181a5
YZ		 620 OP_SXTL,
621 OP_SXTL2,
622 OP_UXTL,
623 OP_UXTL2,
624
c0890d26
RS		 625 OP_MOV_P_P,
626 OP_MOV_Z_P_Z,
627 OP_MOV_Z_V,
628 OP_MOV_Z_Z,
629 OP_MOV_Z_Zi,
630 OP_MOVM_P_P_P,
631 OP_MOVS_P_P,
632 OP_MOVZS_P_P_P,
633 OP_MOVZ_P_P_P,
634 OP_NOTS_P_P_P_Z,
635 OP_NOT_P_P_P_Z,
636
c2c4ff8d
SN		 637 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
638
a06ea964
NC		 639 OP_TOTAL_NUM, /* Pseudo. */
640};
641
642/* Maximum number of operands an instruction can have. */
643#define AARCH64_MAX_OPND_NUM 6
644/* Maximum number of qualifier sequences an instruction can have. */
645#define AARCH64_MAX_QLF_SEQ_NUM 10
646/* Operand qualifier typedef; optimized for the size. */
647typedef unsigned char aarch64_opnd_qualifier_t;
648/* Operand qualifier sequence typedef. */
649typedef aarch64_opnd_qualifier_t \
650 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
651
652/* FIXME: improve the efficiency. */
653static inline bfd_boolean
654empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
655{
656 int i;
657 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
658 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
659 return FALSE;
660 return TRUE;
661}
662
663/* This structure holds information for a particular opcode. */
664
665struct aarch64_opcode
666{
667 /* The name of the mnemonic. */
668 const char *name;
669
670 /* The opcode itself. Those bits which will be filled in with
671 operands are zeroes. */
672 aarch64_insn opcode;
673
674 /* The opcode mask. This is used by the disassembler. This is a
675 mask containing ones indicating those bits which must match the
676 opcode field, and zeroes indicating those bits which need not
677 match (and are presumably filled in by operands). */
678 aarch64_insn mask;
679
680 /* Instruction class. */
681 enum aarch64_insn_class iclass;
682
683 /* Enumerator identifier. */
684 enum aarch64_op op;
685
686 /* Which architecture variant provides this instruction. */
687 const aarch64_feature_set *avariant;
688
689 /* An array of operand codes. Each code is an index into the
690 operand table. They appear in the order which the operands must
691 appear in assembly code, and are terminated by a zero. */
692 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
693
694 /* A list of operand qualifier code sequence. Each operand qualifier
695 code qualifies the corresponding operand code. Each operand
696 qualifier sequence specifies a valid opcode variant and related
697 constraint on operands. */
698 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
699
700 /* Flags providing information about this instruction */
701 uint32_t flags;
4bd13cde 702
0c608d6b
RS		 703 /* If nonzero, this operand and operand 0 are both registers and
704 are required to have the same register number. */
705 unsigned char tied_operand;
706
4bd13cde
NC		 707 /* If non-NULL, a function to verify that a given instruction is valid. */
708 bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
a06ea964
NC		 709};
710
711typedef struct aarch64_opcode aarch64_opcode;
712
713/* Table describing all the AArch64 opcodes. */
714extern aarch64_opcode aarch64_opcode_table[];
715
716/* Opcode flags. */
717#define F_ALIAS (1 << 0)
718#define F_HAS_ALIAS (1 << 1)
719/* Disassembly preference priority 1-3 (the larger the higher). If nothing
720 is specified, it is the priority 0 by default, i.e. the lowest priority. */
721#define F_P1 (1 << 2)
722#define F_P2 (2 << 2)
723#define F_P3 (3 << 2)
724/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
725#define F_COND (1 << 4)
726/* Instruction has the field of 'sf'. */
727#define F_SF (1 << 5)
728/* Instruction has the field of 'size:Q'. */
729#define F_SIZEQ (1 << 6)
730/* Floating-point instruction has the field of 'type'. */
731#define F_FPTYPE (1 << 7)
732/* AdvSIMD scalar instruction has the field of 'size'. */
733#define F_SSIZE (1 << 8)
734/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
735#define F_T (1 << 9)
736/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
737#define F_GPRSIZE_IN_Q (1 << 10)
738/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
739#define F_LDS_SIZE (1 << 11)
740/* Optional operand; assume maximum of 1 operand can be optional. */
741#define F_OPD0_OPT (1 << 12)
742#define F_OPD1_OPT (2 << 12)
743#define F_OPD2_OPT (3 << 12)
744#define F_OPD3_OPT (4 << 12)
745#define F_OPD4_OPT (5 << 12)
746/* Default value for the optional operand when omitted from the assembly. */
747#define F_DEFAULT(X) (((X) & 0x1f) << 15)
748/* Instruction that is an alias of another instruction needs to be
749 encoded/decoded by converting it to/from the real form, followed by
750 the encoding/decoding according to the rules of the real opcode.
751 This compares to the direct coding using the alias's information.
752 N.B. this flag requires F_ALIAS to be used together. */
753#define F_CONV (1 << 20)
754/* Use together with F_ALIAS to indicate an alias opcode is a programmer
755 friendly pseudo instruction available only in the assembly code (thus will
756 not show up in the disassembly). */
757#define F_PSEUDO (1 << 21)
758/* Instruction has miscellaneous encoding/decoding rules. */
759#define F_MISC (1 << 22)
760/* Instruction has the field of 'N'; used in conjunction with F_SF. */
761#define F_N (1 << 23)
762/* Opcode dependent field. */
763#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 764/* Instruction has the field of 'sz'. */
765#define F_LSE_SZ (1 << 27)
4989adac
RS		 766/* Require an exact qualifier match, even for NIL qualifiers. */
767#define F_STRICT (1ULL << 28)
f9830ec1
TC		 768/* This system instruction is used to read system registers. */
769#define F_SYS_READ (1ULL << 29)
770/* This system instruction is used to write system registers. */
771#define F_SYS_WRITE (1ULL << 30)
772/* Next bit is 31. */
a06ea964
NC		 773
774static inline bfd_boolean
775alias_opcode_p (const aarch64_opcode *opcode)
776{
777 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
778}
779
780static inline bfd_boolean
781opcode_has_alias (const aarch64_opcode *opcode)
782{
783 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
784}
785
786/* Priority for disassembling preference. */
787static inline int
788opcode_priority (const aarch64_opcode *opcode)
789{
790 return (opcode->flags >> 2) & 0x3;
791}
792
793static inline bfd_boolean
794pseudo_opcode_p (const aarch64_opcode *opcode)
795{
796 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
797}
798
799static inline bfd_boolean
800optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
801{
802 return (((opcode->flags >> 12) & 0x7) == idx + 1)
803 ? TRUE : FALSE;
804}
805
806static inline aarch64_insn
807get_optional_operand_default_value (const aarch64_opcode *opcode)
808{
809 return (opcode->flags >> 15) & 0x1f;
810}
811
812static inline unsigned int
813get_opcode_dependent_value (const aarch64_opcode *opcode)
814{
815 return (opcode->flags >> 24) & 0x7;
816}
817
818static inline bfd_boolean
819opcode_has_special_coder (const aarch64_opcode *opcode)
820{
ee804238 821 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 822 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
823 : FALSE;
824}
825\f
826struct aarch64_name_value_pair
827{
828 const char * name;
829 aarch64_insn value;
830};
831
832extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 833extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
834extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 835extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 836
49eec193
YZ		 837typedef struct
838{
839 const char * name;
840 aarch64_insn value;
841 uint32_t flags;
842} aarch64_sys_reg;
843
844extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 845extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 846extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 847extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
848 const aarch64_sys_reg *);
849extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
850 const aarch64_sys_reg *);
49eec193 851
a06ea964
NC		 852typedef struct
853{
875880c6 854 const char *name;
a06ea964 855 uint32_t value;
ea2deeec 856 uint32_t flags ;
a06ea964
NC		 857} aarch64_sys_ins_reg;
858
ea2deeec 859extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 860extern bfd_boolean
861aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
862 const aarch64_sys_ins_reg *);
ea2deeec 863
a06ea964
NC		 864extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
865extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
866extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
867extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
868
869/* Shift/extending operator kinds.
870 N.B. order is important; keep aarch64_operand_modifiers synced. */
871enum aarch64_modifier_kind
872{
873 AARCH64_MOD_NONE,
874 AARCH64_MOD_MSL,
875 AARCH64_MOD_ROR,
876 AARCH64_MOD_ASR,
877 AARCH64_MOD_LSR,
878 AARCH64_MOD_LSL,
879 AARCH64_MOD_UXTB,
880 AARCH64_MOD_UXTH,
881 AARCH64_MOD_UXTW,
882 AARCH64_MOD_UXTX,
883 AARCH64_MOD_SXTB,
884 AARCH64_MOD_SXTH,
885 AARCH64_MOD_SXTW,
886 AARCH64_MOD_SXTX,
2442d846 887 AARCH64_MOD_MUL,
98907a70 888 AARCH64_MOD_MUL_VL,
a06ea964
NC		 889};
890
891bfd_boolean
892aarch64_extend_operator_p (enum aarch64_modifier_kind);
893
894enum aarch64_modifier_kind
895aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
896/* Condition. */
897
898typedef struct
899{
900 /* A list of names with the first one as the disassembly preference;
901 terminated by NULL if fewer than 3. */
bb7eff52 902 const char *names[4];
a06ea964
NC		 903 aarch64_insn value;
904} aarch64_cond;
905
906extern const aarch64_cond aarch64_conds[16];
907
908const aarch64_cond* get_cond_from_value (aarch64_insn value);
909const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
910\f
911/* Structure representing an operand. */
912
913struct aarch64_opnd_info
914{
915 enum aarch64_opnd type;
916 aarch64_opnd_qualifier_t qualifier;
917 int idx;
918
919 union
920 {
921 struct
922 {
923 unsigned regno;
924 } reg;
925 struct
926 {
dab26bf4
RS		 927 unsigned int regno;
928 int64_t index;
a06ea964
NC		 929 } reglane;
930 /* e.g. LVn. */
931 struct
932 {
933 unsigned first_regno : 5;
934 unsigned num_regs : 3;
935 /* 1 if it is a list of reg element. */
936 unsigned has_index : 1;
937 /* Lane index; valid only when has_index is 1. */
dab26bf4 938 int64_t index;
a06ea964
NC		 939 } reglist;
940 /* e.g. immediate or pc relative address offset. */
941 struct
942 {
943 int64_t value;
944 unsigned is_fp : 1;
945 } imm;
946 /* e.g. address in STR (register offset). */
947 struct
948 {
949 unsigned base_regno;
950 struct
951 {
952 union
953 {
954 int imm;
955 unsigned regno;
956 };
957 unsigned is_reg;
958 } offset;
959 unsigned pcrel : 1; /* PC-relative. */
960 unsigned writeback : 1;
961 unsigned preind : 1; /* Pre-indexed. */
962 unsigned postind : 1; /* Post-indexed. */
963 } addr;
561a72d4
TC		 964
965 struct
966 {
967 /* The encoding of the system register. */
968 aarch64_insn value;
969
970 /* The system register flags. */
971 uint32_t flags;
972 } sysreg;
973
a06ea964 974 const aarch64_cond *cond;
a06ea964
NC		 975 /* The encoding of the PSTATE field. */
976 aarch64_insn pstatefield;
977 const aarch64_sys_ins_reg *sysins_op;
978 const struct aarch64_name_value_pair *barrier;
9ed608f9 979 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 980 const struct aarch64_name_value_pair *prfop;
981 };
982
983 /* Operand shifter; in use when the operand is a register offset address,
984 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
985 struct
986 {
987 enum aarch64_modifier_kind kind;
a06ea964
NC		 988 unsigned operator_present: 1; /* Only valid during encoding. */
989 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
990 unsigned amount_present: 1;
2442d846 991 int64_t amount;
a06ea964
NC		 992 } shifter;
993
994 unsigned skip:1; /* Operand is not completed if there is a fixup needed
995 to be done on it. In some (but not all) of these
996 cases, we need to tell libopcodes to skip the
997 constraint checking and the encoding for this
998 operand, so that the libopcodes can pick up the
999 right opcode before the operand is fixed-up. This
1000 flag should only be used during the
1001 assembling/encoding. */
1002 unsigned present:1; /* Whether this operand is present in the assembly
1003 line; not used during the disassembly. */
1004};
1005
1006typedef struct aarch64_opnd_info aarch64_opnd_info;
1007
1008/* Structure representing an instruction.
1009
1010 It is used during both the assembling and disassembling. The assembler
1011 fills an aarch64_inst after a successful parsing and then passes it to the
1012 encoding routine to do the encoding. During the disassembling, the
1013 disassembler calls the decoding routine to decode a binary instruction; on a
1014 successful return, such a structure will be filled with information of the
1015 instruction; then the disassembler uses the information to print out the
1016 instruction. */
1017
1018struct aarch64_inst
1019{
1020 /* The value of the binary instruction. */
1021 aarch64_insn value;
1022
1023 /* Corresponding opcode entry. */
1024 const aarch64_opcode *opcode;
1025
1026 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1027 const aarch64_cond *cond;
1028
1029 /* Operands information. */
1030 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1031};
1032
1033typedef struct aarch64_inst aarch64_inst;
1034\f
1035/* Diagnosis related declaration and interface. */
1036
1037/* Operand error kind enumerators.
1038
1039 AARCH64_OPDE_RECOVERABLE
1040 Less severe error found during the parsing, very possibly because that
1041 GAS has picked up a wrong instruction template for the parsing.
1042
1043 AARCH64_OPDE_SYNTAX_ERROR
1044 General syntax error; it can be either a user error, or simply because
1045 that GAS is trying a wrong instruction template.
1046
1047 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1048 Definitely a user syntax error.
1049
1050 AARCH64_OPDE_INVALID_VARIANT
1051 No syntax error, but the operands are not a valid combination, e.g.
1052 FMOV D0,S0
1053
0c608d6b
RS		 1054 AARCH64_OPDE_UNTIED_OPERAND
1055 The asm failed to use the same register for a destination operand
1056 and a tied source operand.
1057
a06ea964
NC		 1058 AARCH64_OPDE_OUT_OF_RANGE
1059 Error about some immediate value out of a valid range.
1060
1061 AARCH64_OPDE_UNALIGNED
1062 Error about some immediate value not properly aligned (i.e. not being a
1063 multiple times of a certain value).
1064
1065 AARCH64_OPDE_REG_LIST
1066 Error about the register list operand having unexpected number of
1067 registers.
1068
1069 AARCH64_OPDE_OTHER_ERROR
1070 Error of the highest severity and used for any severe issue that does not
1071 fall into any of the above categories.
1072
1073 The enumerators are only interesting to GAS. They are declared here (in
1074 libopcodes) because that some errors are detected (and then notified to GAS)
1075 by libopcodes (rather than by GAS solely).
1076
1077 The first three errors are only deteced by GAS while the
1078 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1079 only libopcodes has the information about the valid variants of each
1080 instruction.
1081
1082 The enumerators have an increasing severity. This is helpful when there are
1083 multiple instruction templates available for a given mnemonic name (e.g.
1084 FMOV); this mechanism will help choose the most suitable template from which
1085 the generated diagnostics can most closely describe the issues, if any. */
1086
1087enum aarch64_operand_error_kind
1088{
1089 AARCH64_OPDE_NIL,
1090 AARCH64_OPDE_RECOVERABLE,
1091 AARCH64_OPDE_SYNTAX_ERROR,
1092 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1093 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1094 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1095 AARCH64_OPDE_OUT_OF_RANGE,
1096 AARCH64_OPDE_UNALIGNED,
1097 AARCH64_OPDE_REG_LIST,
1098 AARCH64_OPDE_OTHER_ERROR
1099};
1100
1101/* N.B. GAS assumes that this structure work well with shallow copy. */
1102struct aarch64_operand_error
1103{
1104 enum aarch64_operand_error_kind kind;
1105 int index;
1106 const char *error;
1107 int data[3]; /* Some data for extra information. */
7d02540a 1108 bfd_boolean non_fatal;
a06ea964
NC		 1109};
1110
1111typedef struct aarch64_operand_error aarch64_operand_error;
1112
1113/* Encoding entrypoint. */
1114
1115extern int
1116aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1117 aarch64_insn *, aarch64_opnd_qualifier_t *,
1118 aarch64_operand_error *);
1119
1120extern const aarch64_opcode *
1121aarch64_replace_opcode (struct aarch64_inst *,
1122 const aarch64_opcode *);
1123
1124/* Given the opcode enumerator OP, return the pointer to the corresponding
1125 opcode entry. */
1126
1127extern const aarch64_opcode *
1128aarch64_get_opcode (enum aarch64_op);
1129
1130/* Generate the string representation of an operand. */
1131extern void
1132aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
7d02540a
TC		 1133 const aarch64_opnd_info *, int, int *, bfd_vma *,
1134 char **);
a06ea964
NC		 1135
1136/* Miscellaneous interface. */
1137
1138extern int
1139aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1140
1141extern aarch64_opnd_qualifier_t
1142aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1143 const aarch64_opnd_qualifier_t, int);
1144
1145extern int
1146aarch64_num_of_operands (const aarch64_opcode *);
1147
1148extern int
1149aarch64_stack_pointer_p (const aarch64_opnd_info *);
1150
e141d84e
YQ		 1151extern int
1152aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1153
36f4aab1 1154extern int
561a72d4
TC		 1155aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
1156 aarch64_operand_error *errors);
36f4aab1 1157
a06ea964
NC		 1158/* Given an operand qualifier, return the expected data element size
1159 of a qualified operand. */
1160extern unsigned char
1161aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1162
1163extern enum aarch64_operand_class
1164aarch64_get_operand_class (enum aarch64_opnd);
1165
1166extern const char *
1167aarch64_get_operand_name (enum aarch64_opnd);
1168
1169extern const char *
1170aarch64_get_operand_desc (enum aarch64_opnd);
1171
e950b345
RS		 1172extern bfd_boolean
1173aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1174
a06ea964
NC		 1175#ifdef DEBUG_AARCH64
1176extern int debug_dump;
1177
1178extern void
1179aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1180
1181#define DEBUG_TRACE(M, ...) \
1182 { \
1183 if (debug_dump) \
1184 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1185 }
1186
1187#define DEBUG_TRACE_IF(C, M, ...) \
1188 { \
1189 if (debug_dump && (C)) \
1190 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1191 }
1192#else /* !DEBUG_AARCH64 */
1193#define DEBUG_TRACE(M, ...) ;
1194#define DEBUG_TRACE_IF(C, M, ...) ;
1195#endif /* DEBUG_AARCH64 */
1196
245d2e3f
RS		 1197extern const char *const aarch64_sve_pattern_array[32];
1198extern const char *const aarch64_sve_prfop_array[16];
1199
d3e12b29
YQ		 1200#ifdef __cplusplus
1201}
1202#endif
1203
a06ea964 1204#endif /* OPCODE_AARCH64_H */
A mirror of the official binutils-gdb repository