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Revert "arc: Update ARC's Gnu Assembler backend with ARCv3 ISA."
[thirdparty/binutils-gdb.git] / include / opcode / arc.h
CommitLineData
252b5132 1/* Opcode table for the ARC.
d87bef3a 2 Copyright (C) 1994-2023 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
252b5132 5
0d2bcfaf
NC		 6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
7 the GNU Binutils.
252b5132 8
0d2bcfaf
NC		 9 GAS/GDB is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
e4e42b45 11 the Free Software Foundation; either version 3, or (at your option)
0d2bcfaf 12 any later version.
252b5132 13
0d2bcfaf
NC		 14 GAS/GDB is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
886a2506 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0d2bcfaf
NC		 17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
e4e42b45 20 along with GAS or GDB; see the file COPYING3. If not, write to
e172dbf8
NC		 21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132 23
886a2506
NC		 24#ifndef OPCODE_ARC_H
25#define OPCODE_ARC_H
26
6b477896
TS		 27#ifdef __cplusplus
28extern "C" {
29#endif
30
4670103e 31#ifndef MAX_INSN_ARGS
4eb6f892 32#define MAX_INSN_ARGS 16
4670103e
CZ		 33#endif
34
35#ifndef MAX_INSN_FLGS
575dcd27 36#define MAX_INSN_FLGS 4
4670103e 37#endif
886a2506
NC		 38
39/* Instruction Class. */
40typedef enum
db18dbab
GM		 41{
42 ACL,
43 ARITH,
44 AUXREG,
6ec7c1ae
CZ		 45 BBIT0,
46 BBIT1,
47 BI,
48 BIH,
db18dbab 49 BITOP,
2b848ebd 50 BITSTREAM,
db18dbab
GM		 51 BMU,
52 BRANCH,
6ec7c1ae 53 BRCC,
db18dbab 54 CONTROL,
abe7c33b 55 DIVREM,
645d3342 56 DMA,
db18dbab
GM		 57 DPI,
58 DSP,
6ec7c1ae
CZ		 59 EI,
60 ENTER,
db18dbab
GM		 61 FLOAT,
62 INVALID,
6ec7c1ae 63 JLI,
db18dbab
GM		 64 JUMP,
65 KERNEL,
6ec7c1ae 66 LEAVE,
bb82aefe 67 LLOCK,
abe7c33b 68 LOAD,
db18dbab 69 LOGICAL,
6ec7c1ae 70 LOOP,
db18dbab 71 MEMORY,
c0c31e91 72 MISC,
abe7c33b
CZ		 73 MOVE,
74 MPY,
db18dbab 75 NET,
5a736821 76 PROTOCOL_DECODE,
2b848ebd 77 PMU,
6ec7c1ae
CZ		 78 POP,
79 PUSH,
bb82aefe 80 SCOND,
7179e0e6 81 SJLI,
abe7c33b 82 STORE,
6ec7c1ae 83 SUB,
7e126ba3 84 SWITCH,
c0c31e91 85 ULTRAIP,
2b848ebd 86 XY
db18dbab 87} insn_class_t;
886a2506
NC		 88
89/* Instruction Subclass. */
90typedef enum
db18dbab 91{
53a346d8
CZ		 92 NONE = 0,
93 CVT = (1U << 1),
94 BTSCN = (1U << 2),
95 CD = (1U << 3),
96 CD1 = CD,
97 CD2 = CD,
98 COND = (1U << 4),
99 DIV = (1U << 5),
100 DP = (1U << 6),
101 DPA = (1U << 7),
102 DPX = (1U << 8),
cd18a823 103 FASTMATH = (1U << 23),
53a346d8
CZ		 104 LL64 = (1U << 9),
105 MPY1E = (1U << 10),
106 MPY6E = (1U << 11),
107 MPY7E = (1U << 12),
108 MPY8E = (1U << 13),
109 MPY9E = (1U << 14),
110 NPS400 = (1U << 15),
111 QUARKSE1 = (1U << 16),
112 QUARKSE2 = (1U << 17),
113 SHFT1 = (1U << 18),
114 SHFT2 = (1U << 19),
115 SWAP = (1U << 20),
116 SP = (1U << 21),
117 SPX = (1U << 22)
db18dbab 118} insn_subclass_t;
886a2506
NC		 119
120/* Flags class. */
121typedef enum
db18dbab
GM		 122{
123 F_CLASS_NONE = 0,
1ae8ab47 124
db18dbab
GM		 125 /* At most one flag from the set of flags can appear in the
126 instruction. */
127 F_CLASS_OPTIONAL = (1 << 0),
1ae8ab47 128
db18dbab
GM		 129 /* Exactly one from from the set of flags must appear in the
130 instruction. */
131 F_CLASS_REQUIRED = (1 << 1),
f36e33da 132
db18dbab
GM		 133 /* The conditional code can be extended over the standard variants
134 via .extCondCode pseudo-op. */
135 F_CLASS_EXTEND = (1 << 2),
d9eca1df 136
db18dbab 137 /* Condition code flag. */
6ec7c1ae
CZ		 138 F_CLASS_COND = (1 << 3),
139
140 /* Write back mode. */
141 F_CLASS_WB = (1 << 4),
142
143 /* Data size. */
144 F_CLASS_ZZ = (1 << 5),
145
146 /* Implicit flag. */
147 F_CLASS_IMPLICIT = (1 << 6)
db18dbab 148} flag_class_t;
886a2506
NC		 149
150/* The opcode table is an array of struct arc_opcode. */
151struct arc_opcode
152{
153 /* The opcode name. */
c0c31e91 154 const char * name;
886a2506
NC		 155
156 /* The opcode itself. Those bits which will be filled in with
157 operands are zeroes. */
bdfe53e3 158 unsigned long long opcode;
886a2506
NC		 159
160 /* The opcode mask. This is used by the disassembler. This is a
161 mask containing ones indicating those bits which must match the
162 opcode field, and zeroes indicating those bits which need not
163 match (and are presumably filled in by operands). */
bdfe53e3 164 unsigned long long mask;
886a2506
NC		 165
166 /* One bit flags for the opcode. These are primarily used to
167 indicate specific processors and environments support the
168 instructions. The defined values are listed below. */
169 unsigned cpu;
170
171 /* The instruction class. This is used by gdb. */
c810e0b8 172 insn_class_t insn_class;
886a2506
NC		 173
174 /* The instruction subclass. */
175 insn_subclass_t subclass;
176
177 /* An array of operand codes. Each code is an index into the
178 operand table. They appear in the order which the operands must
179 appear in assembly code, and are terminated by a zero. */
180 unsigned char operands[MAX_INSN_ARGS + 1];
181
182 /* An array of flag codes. Each code is an index into the flag
183 table. They appear in the order which the flags must appear in
184 assembly code, and are terminated by a zero. */
185 unsigned char flags[MAX_INSN_FLGS + 1];
186};
252b5132 187
886a2506
NC		 188/* The table itself is sorted by major opcode number, and is otherwise
189 in the order in which the disassembler should consider
190 instructions. */
191extern const struct arc_opcode arc_opcodes[];
886a2506 192
06fe285f
GM		 193/* Return length of an instruction represented by OPCODE, in bytes. */
194extern int arc_opcode_len (const struct arc_opcode *opcode);
195
886a2506 196/* CPU Availability. */
f36e33da 197#define ARC_OPCODE_NONE 0x0000
886a2506
NC		 198#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
199#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
200#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
201#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
04414221
CZ		 202#define ARC_OPCODE_ARC64 0x0010 /* ARC64 specific insns. */
203#define ARC_OPCODE_ARC32 0x0020 /* ARC32 specific insns. */
886a2506 204
f36e33da
CZ		 205/* CPU combi. */
206#define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
04414221
CZ		 207 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS \
208 | ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32)
f36e33da 209#define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
b6523c37 210#define ARC_OPCODE_ARCV1 (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700)
e5b06ef0 211#define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
04414221
CZ		 212#define ARC_OPCODE_ARCVx \
213 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64 \
214 | ARC_OPCODE_ARC32)
53a346d8 215#define ARC_OPCODE_ARCMPY6E (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCV2)
886a2506 216
886a2506
NC		 217/* The operands table is an array of struct arc_operand. */
218struct arc_operand
219{
220 /* The number of bits in the operand. */
221 unsigned int bits;
222
223 /* How far the operand is left shifted in the instruction. */
224 unsigned int shift;
225
226 /* The default relocation type for this operand. */
227 signed int default_reloc;
228
229 /* One bit syntax flags. */
230 unsigned int flags;
231
232 /* Insertion function. This is used by the assembler. To insert an
233 operand value into an instruction, check this field.
234
235 If it is NULL, execute
236 i |= (op & ((1 << o->bits) - 1)) << o->shift;
237 (i is the instruction which we are filling in, o is a pointer to
238 this structure, and op is the opcode value; this assumes twos
239 complement arithmetic).
240
241 If this field is not NULL, then simply call it with the
242 instruction and the operand value. It will return the new value
243 of the instruction. If the ERRMSG argument is not NULL, then if
244 the operand value is illegal, *ERRMSG will be set to a warning
245 string (the operand will be inserted in any case). If the
246 operand value is legal, *ERRMSG will be unchanged (most operands
247 can accept any value). */
bdfe53e3
AB		 248 unsigned long long (*insert) (unsigned long long instruction,
249 long long int op,
250 const char **errmsg);
886a2506
NC		 251
252 /* Extraction function. This is used by the disassembler. To
253 extract this operand type from an instruction, check this field.
254
255 If it is NULL, compute
256 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
257 if ((o->flags & ARC_OPERAND_SIGNED) != 0
258 && (op & (1 << (o->bits - 1))) != 0)
259 op -= 1 << o->bits;
260 (i is the instruction, o is a pointer to this structure, and op
261 is the result; this assumes twos complement arithmetic).
262
263 If this field is not NULL, then simply call it with the
264 instruction value. It will return the value of the operand. If
265 the INVALID argument is not NULL, *INVALID will be set to
266 TRUE if this operand type can not actually be extracted from
267 this operand (i.e., the instruction does not match). If the
268 operand is valid, *INVALID will not be changed. */
9193bc42 269 long long int (*extract) (unsigned long long instruction, bool *invalid);
886a2506 270};
0d2bcfaf 271
886a2506
NC		 272/* Elements in the table are retrieved by indexing with values from
273 the operands field of the arc_opcodes table. */
274extern const struct arc_operand arc_operands[];
275extern const unsigned arc_num_operands;
276extern const unsigned arc_Toperand;
277extern const unsigned arc_NToperand;
252b5132 278
886a2506 279/* Values defined for the flags field of a struct arc_operand. */
0d2bcfaf 280
886a2506
NC		 281/* This operand does not actually exist in the assembler input. This
282 is used to support extended mnemonics, for which two operands fields
283 are identical. The assembler should call the insert function with
284 any op value. The disassembler should call the extract function,
285 ignore the return value, and check the value placed in the invalid
286 argument. */
287#define ARC_OPERAND_FAKE 0x0001
252b5132 288
886a2506
NC		 289/* This operand names an integer register. */
290#define ARC_OPERAND_IR 0x0002
0d2bcfaf 291
886a2506
NC		 292/* This operand takes signed values. */
293#define ARC_OPERAND_SIGNED 0x0004
252b5132 294
886a2506
NC		 295/* This operand takes unsigned values. This exists primarily so that
296 a flags value of 0 can be treated as end-of-arguments. */
297#define ARC_OPERAND_UNSIGNED 0x0008
252b5132 298
886a2506
NC		 299/* This operand takes long immediate values. */
300#define ARC_OPERAND_LIMM 0x0010
252b5132 301
886a2506
NC		 302/* This operand is identical like the previous one. */
303#define ARC_OPERAND_DUPLICATE 0x0020
0d2bcfaf 304
886a2506
NC		 305/* This operand is PC relative. Used for internal relocs. */
306#define ARC_OPERAND_PCREL 0x0040
0d2bcfaf 307
886a2506
NC		 308/* This operand is truncated. The truncation is done accordingly to
309 operand alignment attribute. */
310#define ARC_OPERAND_TRUNCATE 0x0080
0d2bcfaf 311
886a2506
NC		 312/* This operand is 16bit aligned. */
313#define ARC_OPERAND_ALIGNED16 0x0100
0d2bcfaf 314
886a2506
NC		 315/* This operand is 32bit aligned. */
316#define ARC_OPERAND_ALIGNED32 0x0200
0d2bcfaf 317
886a2506
NC		 318/* This operand can be ignored by matching process if it is not
319 present. */
320#define ARC_OPERAND_IGNORE 0x0400
0d2bcfaf 321
886a2506
NC		 322/* Don't check the range when matching. */
323#define ARC_OPERAND_NCHK 0x0800
0d2bcfaf 324
886a2506
NC		 325/* Mark the braket possition. */
326#define ARC_OPERAND_BRAKET 0x1000
252b5132 327
db18dbab
GM		 328/* Address type operand for NPS400. */
329#define ARC_OPERAND_ADDRTYPE 0x2000
330
331/* Mark the colon position. */
332#define ARC_OPERAND_COLON 0x4000
333
04414221
CZ		 334/* Mark a floating point register. */
335#define ARC_OPERAND_FP 0x8000
336
886a2506 337/* Mask for selecting the type for typecheck purposes. */
db18dbab
GM		 338#define ARC_OPERAND_TYPECHECK_MASK \
339 (ARC_OPERAND_IR \
340 | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED \
341 | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET \
342 | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
343
344/* Macro to determine if an operand is a fake operand. */
345#define ARC_OPERAND_IS_FAKE(op) \
346 ((operand->flags & ARC_OPERAND_FAKE) \
347 && !((operand->flags & ARC_OPERAND_BRAKET) \
348 || (operand->flags & ARC_OPERAND_COLON)))
252b5132 349
886a2506
NC		 350/* The flags structure. */
351struct arc_flag_operand
352{
353 /* The flag name. */
c0c31e91 354 const char * name;
0d2bcfaf 355
886a2506
NC		 356 /* The flag code. */
357 unsigned code;
252b5132 358
886a2506
NC		 359 /* The number of bits in the operand. */
360 unsigned int bits;
252b5132 361
886a2506
NC		 362 /* How far the operand is left shifted in the instruction. */
363 unsigned int shift;
252b5132 364
886a2506
NC		 365 /* Available for disassembler. */
366 unsigned char favail;
84037f8c
KD		 367};
368
886a2506
NC		 369/* The flag operands table. */
370extern const struct arc_flag_operand arc_flag_operands[];
371extern const unsigned arc_num_flag_operands;
0d2bcfaf 372
886a2506
NC		 373/* The flag's class structure. */
374struct arc_flag_class
375{
376 /* Flag class. */
c810e0b8 377 flag_class_t flag_class;
252b5132 378
886a2506
NC		 379 /* List of valid flags (codes). */
380 unsigned flags[256];
04414221
CZ		 381
382 /* Some special cases needs to use insert/extract functions for
383 flags as well. The function prototypes are identically like the
384 one used for insertion/extraction of an operand. The reason
385 beeing the ability of reusing these functions. */
386 unsigned long long (*insert) (unsigned long long instruction,
387 long long int op,
388 const char **errmsg);
389 long long int (*extract) (unsigned long long instruction,
390 bool *invalid);
886a2506 391};
252b5132 392
886a2506 393extern const struct arc_flag_class arc_flag_classes[];
252b5132 394
886a2506
NC		 395/* Structure for special cases. */
396struct arc_flag_special
397{
398 /* Name of special case instruction. */
399 const char *name;
252b5132 400
886a2506
NC		 401 /* List of flags applicable for special case instruction. */
402 unsigned flags[32];
403};
252b5132 404
886a2506
NC		 405extern const struct arc_flag_special arc_flag_special_cases[];
406extern const unsigned arc_num_flag_special;
407
408/* Relocation equivalence structure. */
409struct arc_reloc_equiv_tab
410{
411 const char * name; /* String to lookup. */
412 const char * mnemonic; /* Extra matching condition. */
24b368f8 413 unsigned flags[32]; /* Extra matching condition. */
886a2506
NC		 414 signed int oldreloc; /* Old relocation. */
415 signed int newreloc; /* New relocation. */
416};
252b5132 417
886a2506
NC		 418extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
419extern const unsigned arc_num_equiv_tab;
252b5132 420
886a2506
NC		 421/* Structure for operand operations for pseudo/alias instructions. */
422struct arc_operand_operation
423{
424 /* The index for operand from operand array. */
425 unsigned operand_idx;
252b5132 426
886a2506
NC		 427 /* Defines if it needs the operand inserted by the assembler or
428 whether this operand comes from the pseudo instruction's
429 operands. */
430 unsigned char needs_insert;
252b5132 431
886a2506
NC		 432 /* Count we have to add to the operand. Use negative number to
433 subtract from the operand. Also use this number to add to 0 if
434 the operand needs to be inserted (i.e. needs_insert == 1). */
435 int count;
252b5132 436
886a2506
NC		 437 /* Index of the operand to swap with. To be done AFTER applying
438 inc_count. */
439 unsigned swap_operand_idx;
252b5132
RH		 440};
441
886a2506
NC		 442/* Structure for pseudo/alias instructions. */
443struct arc_pseudo_insn
444{
445 /* Mnemonic for pseudo/alias insn. */
c0c31e91 446 const char * mnemonic_p;
252b5132 447
886a2506 448 /* Mnemonic for real instruction. */
c0c31e91 449 const char * mnemonic_r;
252b5132 450
886a2506 451 /* Flag that will have to be added (if any). */
c0c31e91 452 const char * flag_r;
252b5132 453
886a2506
NC		 454 /* Amount of operands. */
455 unsigned operand_cnt;
252b5132 456
886a2506
NC		 457 /* Array of operand operations. */
458 struct arc_operand_operation operand[6];
459};
252b5132 460
886a2506
NC		 461extern const struct arc_pseudo_insn arc_pseudo_insns[];
462extern const unsigned arc_num_pseudo_insn;
04414221
CZ		 463extern const struct arc_pseudo_insn arc64_pseudo_insns[];
464extern const unsigned arc64_num_pseudo_insn;
252b5132 465
886a2506
NC		 466/* Structure for AUXILIARY registers. */
467struct arc_aux_reg
468{
469 /* Register address. */
470 int address;
252b5132 471
f36e33da
CZ		 472 /* One bit flags for the opcode. These are primarily used to
473 indicate specific processors and environments support the
474 instructions. */
475 unsigned cpu;
476
8ddf6b2a
CZ		 477 /* AUX register subclass. */
478 insn_subclass_t subclass;
479
480 /* Register name. */
c0c31e91 481 const char * name;
886a2506
NC		 482
483 /* Size of the string. */
484 size_t length;
485};
486
487extern const struct arc_aux_reg arc_aux_regs[];
488extern const unsigned arc_num_aux_regs;
489
4670103e
CZ		 490extern const struct arc_opcode arc_relax_opcodes[];
491extern const unsigned arc_num_relax_opcodes;
492
4b0c052e
AB		 493/* Macro used for generating one class of NPS instructions. */
494#define NPS_CMEM_HIGH_VALUE 0x57f0
495
f2dd8838
CZ		 496/* Macros to help generating regular pattern instructions. */
497#define FIELDA(word) (word & 0x3F)
498#define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
499#define FIELDC(word) ((word & 0x3F) << 6)
500#define FIELDF (0x01 << 15)
501#define FIELDQ (0x1F)
04414221 502#define HARD_FIELDF (0x00)
f2dd8838 503
04414221
CZ		 504#define INSN3OP(MOP,SOP) \
505 (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16) | HARD_FIELDF)
f2dd8838
CZ		 506#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
507#define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
508
509#define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP))
510#define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62))
511#define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62))
512#define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
513#define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62))
514#define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
515#define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
516#define INSN3OP_0LL(MOP,SOP) \
517 (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
518#define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22))
519#define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
520#define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
521#define INSN3OP_0LU(MOP,SOP) \
522 (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
523#define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22))
524#define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
525#define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
526#define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
527#define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
528#define INSN3OP_C0LL(MOP,SOP) \
529 (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
530#define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
531#define INSN3OP_C0LU(MOP,SOP) \
532 (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
533
2e272202
GM		 534#define MASK_32BIT(VAL) (0xffffffff & (VAL))
535
536#define MINSN3OP_ABC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
537#define MINSN3OP_ALC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
538#define MINSN3OP_ABL (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63))))
539#define MINSN3OP_ALL (MASK_32BIT (~(FIELDF | FIELDA (63))))
540#define MINSN3OP_0BC (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
541#define MINSN3OP_0LC (MASK_32BIT (~(FIELDF | FIELDC (63))))
542#define MINSN3OP_0BL (MASK_32BIT (~(FIELDF | FIELDB (63))))
543#define MINSN3OP_0LL (MASK_32BIT (~(FIELDF)))
544#define MINSN3OP_ABU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
545#define MINSN3OP_ALU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
546#define MINSN3OP_0BU (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
547#define MINSN3OP_0LU (MASK_32BIT (~(FIELDF | FIELDC (63))))
548#define MINSN3OP_BBS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
549#define MINSN3OP_0LS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
550#define MINSN3OP_CBBC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
551#define MINSN3OP_CBBL (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63))))
552#define MINSN3OP_C0LC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
553#define MINSN3OP_C0LL (MASK_32BIT (~(FIELDF | FIELDQ)))
554#define MINSN3OP_CBBU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
555#define MINSN3OP_C0LU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
f2dd8838
CZ		 556
557#define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
558#define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
559#define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
560#define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
561#define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
562#define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
563
2e272202
GM		 564#define MINSN2OP_BC (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
565#define MINSN2OP_BL (MASK_32BIT ((~(FIELDF | FIELDB (63)))))
566#define MINSN2OP_0C (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
567#define MINSN2OP_0L (MASK_32BIT ((~(FIELDF))))
568#define MINSN2OP_BU (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
569#define MINSN2OP_0U (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
f2dd8838 570
b99747ae
CZ		 571/* Various constants used when defining an extension instruction. */
572#define ARC_SYNTAX_3OP (1 << 0)
573#define ARC_SYNTAX_2OP (1 << 1)
945e0f82
CZ		 574#define ARC_SYNTAX_1OP (1 << 2)
575#define ARC_SYNTAX_NOP (1 << 3)
576#define ARC_SYNTAX_MASK (0x0F)
577
578#define ARC_OP1_MUST_BE_IMM (1 << 0)
579#define ARC_OP1_IMM_IMPLIED (1 << 1)
b99747ae
CZ		 580
581#define ARC_SUFFIX_NONE (1 << 0)
582#define ARC_SUFFIX_COND (1 << 1)
583#define ARC_SUFFIX_FLAG (1 << 2)
584
f36e33da
CZ		 585#define ARC_REGISTER_READONLY (1 << 0)
586#define ARC_REGISTER_WRITEONLY (1 << 1)
587#define ARC_REGISTER_NOSHORT_CUT (1 << 2)
b99747ae
CZ		 588
589/* Constants needed to initialize extension instructions. */
590extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
591extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
592extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
593extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
594
595extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
596extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
597extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
598extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
599extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
600extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
601extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
602extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
603extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
604extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
605extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
606extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
607
608extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
609extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
610extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
611
612extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
613extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
614extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
615
616extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
617extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
618extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
619extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
620extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
621extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
622
623extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
624extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
625extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
626extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
627
945e0f82
CZ		 628extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
629extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
630extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
631
db18dbab
GM		 632/* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
633 Instruction Set Reference Manual v2.4 for a description of address types. */
634
635typedef enum
636{
637 /* Addresses in memory. */
638
639 /* Buffer descriptor. */
640 ARC_NPS400_ADDRTYPE_BD,
641
642 /* Job identifier. */
643 ARC_NPS400_ADDRTYPE_JID,
644
645 /* Linked Buffer Descriptor. */
646 ARC_NPS400_ADDRTYPE_LBD,
647
648 /* Multicast Buffer Descriptor. */
649 ARC_NPS400_ADDRTYPE_MBD,
650
651 /* Summarized Address. */
652 ARC_NPS400_ADDRTYPE_SD,
653
654 /* SMEM Security Context Local Memory. */
655 ARC_NPS400_ADDRTYPE_SM,
656
657 /* Extended Address. */
658 ARC_NPS400_ADDRTYPE_XA,
659
660 /* Extended Summarized Address. */
661 ARC_NPS400_ADDRTYPE_XD,
662
663 /* CMEM offset addresses. */
664
665 /* On-demand Counter Descriptor. */
666 ARC_NPS400_ADDRTYPE_CD,
667
668 /* CMEM Buffer Descriptor. */
669 ARC_NPS400_ADDRTYPE_CBD,
670
671 /* CMEM Job Identifier. */
672 ARC_NPS400_ADDRTYPE_CJID,
673
674 /* CMEM Linked Buffer Descriptor. */
675 ARC_NPS400_ADDRTYPE_CLBD,
676
677 /* CMEM Offset. */
678 ARC_NPS400_ADDRTYPE_CM,
679
680 /* CMEM Summarized Address. */
681 ARC_NPS400_ADDRTYPE_CSD,
682
683 /* CMEM Extended Address. */
684 ARC_NPS400_ADDRTYPE_CXA,
685
686 /* CMEM Extended Summarized Address. */
687 ARC_NPS400_ADDRTYPE_CXD
688
689} arc_nps_address_type;
690
691#define ARC_NUM_ADDRTYPES 16
692
04414221
CZ		 693/*ARC64 floating point enums. */
694#define P_HALF 0
695#define P_SINGLE 1
696#define P_DOUBLE 2
697
698#define TOPF_FMADD 0
699#define TOPF_FMSUB 1
700#define TOPF_FNMADD 2
701#define TOPF_FNMSUB 3
702#define TOPF_VFMADD 4
703#define TOPF_VFMSUB 5
704#define TOPF_VFNMADD 6
705#define TOPF_VFNMSUB 7
706#define TOPF_VFMADDS 0xC
707#define TOPF_VFMSUBS 0xD
708#define TOPF_VFNMADDS 0xE
709#define TOPF_VFNMSUBS 0xF
710
711#define DOPF_FADD 0
712#define DOPF_FSUB 1
713#define DOPF_FMUL 2
714#define DOPF_FDIV 3
715#define DOPF_FCMP 4
716#define DOPF_FCMPF 5
717#define DOPF_FMIN 6
718#define DOPF_FMAX 7
719#define DOPF_FSGNJ 8
720#define DOPF_FSGNJN 10
721#define DOPF_FSGNJX 11
722#define DOPF_VFADD 0x10
723#define DOPF_VFSUB 0x11
724#define DOPF_VFMUL 0x12
725#define DOPF_VFDIV 0x13
726#define DOPF_VFADDS 0x14
727#define DOPF_VFSUBS 0x15
728#define DOPF_VFMULS 0x16
729#define DOPF_VFDIVS 0x17
730#define DOPF_VFUNPKL 0x18
731#define DOPF_VFUNPKM 0x19
732#define DOPF_VFPACKL 0x1a
733#define DOPF_VFPACKM 0x1b
734#define DOPF_VFBFLYL 0x1c
735#define DOPF_VFBFLYM 0x1d
736#define DOPF_VFADDSUB 0x1e
737#define DOPF_VFSUBADD 0x1f
738
739#define SOPF_FSQRT 0
740#define SOPF_VFSQRT 1
741#define SOPF_VFEXCH 2
742
743#define COPF_FMOV 0
744#define COPF_VFMOV 1
745
746#define FUINT2S 0
747#define FS2UINT 0
748#define FINT2S 0
749#define FS2INT 0
750#define FSRND 0
751#define F2UINT_RZ 0
752#define FSINT_RZ 0
753#define FSRND_RZ 0
754#define FMVI2S 0
755#define FMVS2I 0
756#define FS2H 0
757#define FH2S 0
758#define FS2H_RZ 0
759
760#define FUINT2D 1
761#define FS2UL 1
762#define FINT2D 1
763#define FS2L 1
764#define FS2D 1
765#define FS2UL_RZ 1
766#define FS2L_RZ 1
767
768#define FUL2S 2
769#define FD2UINT 2
770#define FL2S 2
771#define FD2INT 2
772#define FD2S 2
773#define FD2UINT_RZ 2
774#define FD2INT_RZ 2
775
776#define FUL2D 3
777#define FD2UL 3
778#define FL2D 3
779#define FD2L 3
780#define FDRND 3
781#define FD2UL_RZ 3
782#define FD2L_RZ 3
783#define FDRND_RZ 3
784#define FMVL2D 3
785#define FMVD2L 3
786
6b477896
TS		 787#ifdef __cplusplus
788}
789#endif
790
886a2506 791#endif /* OPCODE_ARC_H */
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