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252b5132 | 1 | /* ppc.h -- Header file for PowerPC opcode table |
9622b051 | 2 | Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 |
fc1e7121 | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | Written by Ian Lance Taylor, Cygnus Support |
5 | ||
6 | This file is part of GDB, GAS, and the GNU binutils. | |
7 | ||
8 | GDB, GAS, and the GNU binutils are free software; you can redistribute | |
9 | them and/or modify them under the terms of the GNU General Public | |
10 | License as published by the Free Software Foundation; either version | |
11 | 1, or (at your option) any later version. | |
12 | ||
13 | GDB, GAS, and the GNU binutils are distributed in the hope that they | |
14 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
15 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
16 | the GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this file; see the file COPYING. If not, write to the Free | |
e172dbf8 | 20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
252b5132 RH |
21 | |
22 | #ifndef PPC_H | |
23 | #define PPC_H | |
24 | ||
25 | /* The opcode table is an array of struct powerpc_opcode. */ | |
26 | ||
27 | struct powerpc_opcode | |
28 | { | |
29 | /* The opcode name. */ | |
30 | const char *name; | |
31 | ||
32 | /* The opcode itself. Those bits which will be filled in with | |
33 | operands are zeroes. */ | |
34 | unsigned long opcode; | |
35 | ||
36 | /* The opcode mask. This is used by the disassembler. This is a | |
37 | mask containing ones indicating those bits which must match the | |
38 | opcode field, and zeroes indicating those bits which need not | |
39 | match (and are presumably filled in by operands). */ | |
40 | unsigned long mask; | |
41 | ||
42 | /* One bit flags for the opcode. These are used to indicate which | |
43 | specific processors support the instructions. The defined values | |
44 | are listed below. */ | |
45 | unsigned long flags; | |
46 | ||
47 | /* An array of operand codes. Each code is an index into the | |
48 | operand table. They appear in the order which the operands must | |
49 | appear in assembly code, and are terminated by a zero. */ | |
50 | unsigned char operands[8]; | |
51 | }; | |
52 | ||
53 | /* The table itself is sorted by major opcode number, and is otherwise | |
54 | in the order in which the disassembler should consider | |
55 | instructions. */ | |
56 | extern const struct powerpc_opcode powerpc_opcodes[]; | |
57 | extern const int powerpc_num_opcodes; | |
58 | ||
59 | /* Values defined for the flags field of a struct powerpc_opcode. */ | |
60 | ||
61 | /* Opcode is defined for the PowerPC architecture. */ | |
68d23d21 | 62 | #define PPC_OPCODE_PPC 1 |
252b5132 RH |
63 | |
64 | /* Opcode is defined for the POWER (RS/6000) architecture. */ | |
68d23d21 | 65 | #define PPC_OPCODE_POWER 2 |
252b5132 RH |
66 | |
67 | /* Opcode is defined for the POWER2 (Rios 2) architecture. */ | |
68d23d21 | 68 | #define PPC_OPCODE_POWER2 4 |
252b5132 RH |
69 | |
70 | /* Opcode is only defined on 32 bit architectures. */ | |
68d23d21 | 71 | #define PPC_OPCODE_32 8 |
252b5132 RH |
72 | |
73 | /* Opcode is only defined on 64 bit architectures. */ | |
68d23d21 | 74 | #define PPC_OPCODE_64 0x10 |
252b5132 RH |
75 | |
76 | /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 | |
77 | is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, | |
78 | but it also supports many additional POWER instructions. */ | |
68d23d21 | 79 | #define PPC_OPCODE_601 0x20 |
252b5132 RH |
80 | |
81 | /* Opcode is supported in both the Power and PowerPC architectures | |
82 | (ie, compiler's -mcpu=common or assembler's -mcom). */ | |
68d23d21 | 83 | #define PPC_OPCODE_COMMON 0x40 |
252b5132 RH |
84 | |
85 | /* Opcode is supported for any Power or PowerPC platform (this is | |
86 | for the assembler's -many option, and it eliminates duplicates). */ | |
68d23d21 | 87 | #define PPC_OPCODE_ANY 0x80 |
252b5132 | 88 | |
45c18104 | 89 | /* Opcode is supported as part of the 64-bit bridge. */ |
68d23d21 | 90 | #define PPC_OPCODE_64_BRIDGE 0x100 |
45c18104 | 91 | |
966f959b | 92 | /* Opcode is supported by Altivec Vector Unit */ |
68d23d21 | 93 | #define PPC_OPCODE_ALTIVEC 0x200 |
418c1742 MG |
94 | |
95 | /* Opcode is supported by PowerPC 403 processor. */ | |
68d23d21 | 96 | #define PPC_OPCODE_403 0x400 |
418c1742 | 97 | |
a09cf9bd | 98 | /* Opcode is supported by PowerPC BookE processor. */ |
68d23d21 | 99 | #define PPC_OPCODE_BOOKE 0x800 |
418c1742 | 100 | |
a09cf9bd | 101 | /* Opcode is only supported by 64-bit PowerPC BookE processor. */ |
68d23d21 AM |
102 | #define PPC_OPCODE_BOOKE64 0x1000 |
103 | ||
104 | /* Opcode is supported by PowerPC 440 processor. */ | |
105 | #define PPC_OPCODE_440 0x2000 | |
966f959b | 106 | |
fc1e7121 | 107 | /* Opcode is only supported by Power4 architecture. */ |
68d23d21 | 108 | #define PPC_OPCODE_POWER4 0x4000 |
fc1e7121 AM |
109 | |
110 | /* Opcode isn't supported by Power4 architecture. */ | |
68d23d21 | 111 | #define PPC_OPCODE_NOPOWER4 0x8000 |
fc1e7121 | 112 | |
0449635d | 113 | /* Opcode is only supported by POWERPC Classic architecture. */ |
68d23d21 | 114 | #define PPC_OPCODE_CLASSIC 0x10000 |
0449635d EZ |
115 | |
116 | /* Opcode is only supported by e500x2 Core. */ | |
68d23d21 | 117 | #define PPC_OPCODE_SPE 0x20000 |
0449635d EZ |
118 | |
119 | /* Opcode is supported by e500x2 Integer select APU. */ | |
68d23d21 | 120 | #define PPC_OPCODE_ISEL 0x40000 |
0449635d EZ |
121 | |
122 | /* Opcode is an e500 SPE floating point instruction. */ | |
68d23d21 | 123 | #define PPC_OPCODE_EFS 0x80000 |
0449635d EZ |
124 | |
125 | /* Opcode is supported by branch locking APU. */ | |
68d23d21 | 126 | #define PPC_OPCODE_BRLOCK 0x100000 |
0449635d EZ |
127 | |
128 | /* Opcode is supported by performance monitor APU. */ | |
68d23d21 | 129 | #define PPC_OPCODE_PMR 0x200000 |
0449635d EZ |
130 | |
131 | /* Opcode is supported by cache locking APU. */ | |
68d23d21 | 132 | #define PPC_OPCODE_CACHELCK 0x400000 |
0449635d EZ |
133 | |
134 | /* Opcode is supported by machine check APU. */ | |
68d23d21 | 135 | #define PPC_OPCODE_RFMCI 0x800000 |
0449635d | 136 | |
f4411256 | 137 | /* Opcode is only supported by Power5 architecture. */ |
9622b051 | 138 | #define PPC_OPCODE_POWER5 0x1000000 |
f4411256 | 139 | |
36ae0db3 | 140 | /* Opcode is supported by PowerPC e300 family. */ |
9622b051 AM |
141 | #define PPC_OPCODE_E300 0x2000000 |
142 | ||
143 | /* Opcode is only supported by Power6 architecture. */ | |
144 | #define PPC_OPCODE_POWER6 0x4000000 | |
145 | ||
36ae0db3 | 146 | |
252b5132 RH |
147 | /* A macro to extract the major opcode from an instruction. */ |
148 | #define PPC_OP(i) (((i) >> 26) & 0x3f) | |
149 | \f | |
150 | /* The operands table is an array of struct powerpc_operand. */ | |
151 | ||
152 | struct powerpc_operand | |
153 | { | |
154 | /* The number of bits in the operand. */ | |
155 | int bits; | |
156 | ||
157 | /* How far the operand is left shifted in the instruction. */ | |
158 | int shift; | |
159 | ||
160 | /* Insertion function. This is used by the assembler. To insert an | |
161 | operand value into an instruction, check this field. | |
162 | ||
163 | If it is NULL, execute | |
fdd12ef3 | 164 | i |= (op & ((1 << o->bits) - 1)) << o->shift; |
252b5132 RH |
165 | (i is the instruction which we are filling in, o is a pointer to |
166 | this structure, and op is the opcode value; this assumes twos | |
167 | complement arithmetic). | |
168 | ||
169 | If this field is not NULL, then simply call it with the | |
170 | instruction and the operand value. It will return the new value | |
171 | of the instruction. If the ERRMSG argument is not NULL, then if | |
172 | the operand value is illegal, *ERRMSG will be set to a warning | |
173 | string (the operand will be inserted in any case). If the | |
174 | operand value is legal, *ERRMSG will be unchanged (most operands | |
175 | can accept any value). */ | |
8cf3f354 AM |
176 | unsigned long (*insert) |
177 | (unsigned long instruction, long op, int dialect, const char **errmsg); | |
252b5132 RH |
178 | |
179 | /* Extraction function. This is used by the disassembler. To | |
180 | extract this operand type from an instruction, check this field. | |
181 | ||
182 | If it is NULL, compute | |
fdd12ef3 | 183 | op = ((i) >> o->shift) & ((1 << o->bits) - 1); |
252b5132 RH |
184 | if ((o->flags & PPC_OPERAND_SIGNED) != 0 |
185 | && (op & (1 << (o->bits - 1))) != 0) | |
186 | op -= 1 << o->bits; | |
187 | (i is the instruction, o is a pointer to this structure, and op | |
188 | is the result; this assumes twos complement arithmetic). | |
189 | ||
190 | If this field is not NULL, then simply call it with the | |
191 | instruction value. It will return the value of the operand. If | |
192 | the INVALID argument is not NULL, *INVALID will be set to | |
193 | non-zero if this operand type can not actually be extracted from | |
194 | this operand (i.e., the instruction does not match). If the | |
195 | operand is valid, *INVALID will not be changed. */ | |
8cf3f354 | 196 | long (*extract) (unsigned long instruction, int dialect, int *invalid); |
252b5132 RH |
197 | |
198 | /* One bit syntax flags. */ | |
199 | unsigned long flags; | |
200 | }; | |
201 | ||
202 | /* Elements in the table are retrieved by indexing with values from | |
203 | the operands field of the powerpc_opcodes table. */ | |
204 | ||
205 | extern const struct powerpc_operand powerpc_operands[]; | |
206 | ||
207 | /* Values defined for the flags field of a struct powerpc_operand. */ | |
208 | ||
209 | /* This operand takes signed values. */ | |
210 | #define PPC_OPERAND_SIGNED (01) | |
211 | ||
212 | /* This operand takes signed values, but also accepts a full positive | |
213 | range of values when running in 32 bit mode. That is, if bits is | |
214 | 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, | |
215 | this flag is ignored. */ | |
216 | #define PPC_OPERAND_SIGNOPT (02) | |
217 | ||
218 | /* This operand does not actually exist in the assembler input. This | |
219 | is used to support extended mnemonics such as mr, for which two | |
220 | operands fields are identical. The assembler should call the | |
221 | insert function with any op value. The disassembler should call | |
222 | the extract function, ignore the return value, and check the value | |
223 | placed in the valid argument. */ | |
224 | #define PPC_OPERAND_FAKE (04) | |
225 | ||
226 | /* The next operand should be wrapped in parentheses rather than | |
227 | separated from this one by a comma. This is used for the load and | |
228 | store instructions which want their operands to look like | |
229 | reg,displacement(reg) | |
230 | */ | |
231 | #define PPC_OPERAND_PARENS (010) | |
232 | ||
233 | /* This operand may use the symbolic names for the CR fields, which | |
234 | are | |
235 | lt 0 gt 1 eq 2 so 3 un 3 | |
236 | cr0 0 cr1 1 cr2 2 cr3 3 | |
237 | cr4 4 cr5 5 cr6 6 cr7 7 | |
238 | These may be combined arithmetically, as in cr2*4+gt. These are | |
239 | only supported on the PowerPC, not the POWER. */ | |
240 | #define PPC_OPERAND_CR (020) | |
241 | ||
242 | /* This operand names a register. The disassembler uses this to print | |
243 | register names with a leading 'r'. */ | |
244 | #define PPC_OPERAND_GPR (040) | |
245 | ||
fdd12ef3 AM |
246 | /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ |
247 | #define PPC_OPERAND_GPR_0 (0100) | |
248 | ||
252b5132 RH |
249 | /* This operand names a floating point register. The disassembler |
250 | prints these with a leading 'f'. */ | |
fdd12ef3 | 251 | #define PPC_OPERAND_FPR (0200) |
252b5132 RH |
252 | |
253 | /* This operand is a relative branch displacement. The disassembler | |
254 | prints these symbolically if possible. */ | |
fdd12ef3 | 255 | #define PPC_OPERAND_RELATIVE (0400) |
252b5132 RH |
256 | |
257 | /* This operand is an absolute branch address. The disassembler | |
258 | prints these symbolically if possible. */ | |
fdd12ef3 | 259 | #define PPC_OPERAND_ABSOLUTE (01000) |
252b5132 RH |
260 | |
261 | /* This operand is optional, and is zero if omitted. This is used for | |
2a309db0 | 262 | example, in the optional BF field in the comparison instructions. The |
252b5132 RH |
263 | assembler must count the number of operands remaining on the line, |
264 | and the number of operands remaining for the opcode, and decide | |
265 | whether this operand is present or not. The disassembler should | |
266 | print this operand out only if it is not zero. */ | |
fdd12ef3 | 267 | #define PPC_OPERAND_OPTIONAL (02000) |
252b5132 RH |
268 | |
269 | /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand | |
270 | is omitted, then for the next operand use this operand value plus | |
271 | 1, ignoring the next operand field for the opcode. This wretched | |
272 | hack is needed because the Power rotate instructions can take | |
273 | either 4 or 5 operands. The disassembler should print this operand | |
274 | out regardless of the PPC_OPERAND_OPTIONAL field. */ | |
fdd12ef3 | 275 | #define PPC_OPERAND_NEXT (04000) |
252b5132 RH |
276 | |
277 | /* This operand should be regarded as a negative number for the | |
278 | purposes of overflow checking (i.e., the normal most negative | |
279 | number is disallowed and one more than the normal most positive | |
280 | number is allowed). This flag will only be set for a signed | |
281 | operand. */ | |
fdd12ef3 | 282 | #define PPC_OPERAND_NEGATIVE (010000) |
966f959b C |
283 | |
284 | /* This operand names a vector unit register. The disassembler | |
285 | prints these with a leading 'v'. */ | |
fdd12ef3 | 286 | #define PPC_OPERAND_VR (020000) |
966f959b | 287 | |
a6959011 | 288 | /* This operand is for the DS field in a DS form instruction. */ |
fdd12ef3 | 289 | #define PPC_OPERAND_DS (040000) |
adadcc0c AM |
290 | |
291 | /* This operand is for the DQ field in a DQ form instruction. */ | |
fdd12ef3 | 292 | #define PPC_OPERAND_DQ (0100000) |
252b5132 RH |
293 | \f |
294 | /* The POWER and PowerPC assemblers use a few macros. We keep them | |
295 | with the operands table for simplicity. The macro table is an | |
296 | array of struct powerpc_macro. */ | |
297 | ||
298 | struct powerpc_macro | |
299 | { | |
300 | /* The macro name. */ | |
301 | const char *name; | |
302 | ||
303 | /* The number of operands the macro takes. */ | |
304 | unsigned int operands; | |
305 | ||
306 | /* One bit flags for the opcode. These are used to indicate which | |
307 | specific processors support the instructions. The values are the | |
308 | same as those for the struct powerpc_opcode flags field. */ | |
309 | unsigned long flags; | |
310 | ||
311 | /* A format string to turn the macro into a normal instruction. | |
312 | Each %N in the string is replaced with operand number N (zero | |
313 | based). */ | |
314 | const char *format; | |
315 | }; | |
316 | ||
317 | extern const struct powerpc_macro powerpc_macros[]; | |
318 | extern const int powerpc_num_macros; | |
319 | ||
320 | #endif /* PPC_H */ |