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252b5132 | 1 | /* ppc.h -- Header file for PowerPC opcode table |
d87bef3a | 2 | Copyright (C) 1994-2023 Free Software Foundation, Inc. |
252b5132 RH |
3 | Written by Ian Lance Taylor, Cygnus Support |
4 | ||
e4e42b45 NC |
5 | This file is part of GDB, GAS, and the GNU binutils. |
6 | ||
7 | GDB, GAS, and the GNU binutils are free software; you can redistribute | |
8 | them and/or modify them under the terms of the GNU General Public | |
9 | License as published by the Free Software Foundation; either version 3, | |
10 | or (at your option) any later version. | |
11 | ||
12 | GDB, GAS, and the GNU binutils are distributed in the hope that they | |
13 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
14 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
15 | the GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this file; see the file COPYING3. If not, write to the Free | |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
20 | MA 02110-1301, USA. */ | |
252b5132 RH |
21 | |
22 | #ifndef PPC_H | |
23 | #define PPC_H | |
24 | ||
3dfb1b6d | 25 | #include <stdint.h> |
b961e85b | 26 | |
1fe0971e TS |
27 | #ifdef __cplusplus |
28 | extern "C" { | |
29 | #endif | |
30 | ||
b961e85b | 31 | typedef uint64_t ppc_cpu_t; |
8e5eb8e1 DS |
32 | typedef uint16_t ppc_opindex_t; |
33 | ||
34 | /* Smaller of ppc_opindex_t and fx_pcrel_adjust maximum. Note that | |
35 | values extracted from fx_pcrel_adjust are masked with this constant, | |
36 | effectively making the field unsigned. */ | |
37 | #define PPC_OPINDEX_MAX 0xffff | |
fa452fa6 | 38 | |
252b5132 RH |
39 | /* The opcode table is an array of struct powerpc_opcode. */ |
40 | ||
41 | struct powerpc_opcode | |
42 | { | |
43 | /* The opcode name. */ | |
44 | const char *name; | |
45 | ||
46 | /* The opcode itself. Those bits which will be filled in with | |
47 | operands are zeroes. */ | |
0f873fd5 | 48 | uint64_t opcode; |
252b5132 RH |
49 | |
50 | /* The opcode mask. This is used by the disassembler. This is a | |
51 | mask containing ones indicating those bits which must match the | |
52 | opcode field, and zeroes indicating those bits which need not | |
53 | match (and are presumably filled in by operands). */ | |
0f873fd5 | 54 | uint64_t mask; |
252b5132 RH |
55 | |
56 | /* One bit flags for the opcode. These are used to indicate which | |
57 | specific processors support the instructions. The defined values | |
58 | are listed below. */ | |
fa452fa6 | 59 | ppc_cpu_t flags; |
252b5132 | 60 | |
1cb0a767 PB |
61 | /* One bit flags for the opcode. These are used to indicate which |
62 | specific processors no longer support the instructions. The defined | |
63 | values are listed below. */ | |
64 | ppc_cpu_t deprecated; | |
65 | ||
252b5132 RH |
66 | /* An array of operand codes. Each code is an index into the |
67 | operand table. They appear in the order which the operands must | |
68 | appear in assembly code, and are terminated by a zero. */ | |
8e5eb8e1 | 69 | ppc_opindex_t operands[8]; |
252b5132 RH |
70 | }; |
71 | ||
72 | /* The table itself is sorted by major opcode number, and is otherwise | |
73 | in the order in which the disassembler should consider | |
74 | instructions. */ | |
75 | extern const struct powerpc_opcode powerpc_opcodes[]; | |
2ceb7719 | 76 | extern const unsigned int powerpc_num_opcodes; |
dd7efa79 PB |
77 | extern const struct powerpc_opcode prefix_opcodes[]; |
78 | extern const unsigned int prefix_num_opcodes; | |
b9c361e0 | 79 | extern const struct powerpc_opcode vle_opcodes[]; |
2ceb7719 | 80 | extern const unsigned int vle_num_opcodes; |
61a457e5 AM |
81 | extern const struct powerpc_opcode lsp_opcodes[]; |
82 | extern const unsigned int lsp_num_opcodes; | |
74081948 | 83 | extern const struct powerpc_opcode spe2_opcodes[]; |
2ceb7719 | 84 | extern const unsigned int spe2_num_opcodes; |
252b5132 RH |
85 | |
86 | /* Values defined for the flags field of a struct powerpc_opcode. */ | |
87 | ||
88 | /* Opcode is defined for the PowerPC architecture. */ | |
52be03fd | 89 | #define PPC_OPCODE_PPC 0x1ull |
252b5132 RH |
90 | |
91 | /* Opcode is defined for the POWER (RS/6000) architecture. */ | |
52be03fd | 92 | #define PPC_OPCODE_POWER 0x2ull |
252b5132 RH |
93 | |
94 | /* Opcode is defined for the POWER2 (Rios 2) architecture. */ | |
52be03fd | 95 | #define PPC_OPCODE_POWER2 0x4ull |
252b5132 | 96 | |
c03dc33b AM |
97 | /* Opcode is only defined on 64 bit architectures. */ |
98 | #define PPC_OPCODE_64 0x8ull | |
99 | ||
252b5132 RH |
100 | /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 |
101 | is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, | |
102 | but it also supports many additional POWER instructions. */ | |
c03dc33b | 103 | #define PPC_OPCODE_601 0x10ull |
252b5132 RH |
104 | |
105 | /* Opcode is supported in both the Power and PowerPC architectures | |
f2bae120 AM |
106 | (ie, compiler's -mcpu=common or assembler's -mcom). More than just |
107 | the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER | |
108 | and PPC_OPCODE_POWER2 because many instructions changed mnemonics | |
109 | between POWER and POWERPC. */ | |
c03dc33b | 110 | #define PPC_OPCODE_COMMON 0x20ull |
252b5132 RH |
111 | |
112 | /* Opcode is supported for any Power or PowerPC platform (this is | |
113 | for the assembler's -many option, and it eliminates duplicates). */ | |
c03dc33b | 114 | #define PPC_OPCODE_ANY 0x40ull |
252b5132 | 115 | |
45c18104 | 116 | /* Opcode is supported as part of the 64-bit bridge. */ |
52be03fd | 117 | #define PPC_OPCODE_64_BRIDGE 0x80ull |
45c18104 | 118 | |
966f959b | 119 | /* Opcode is supported by Altivec Vector Unit */ |
52be03fd | 120 | #define PPC_OPCODE_ALTIVEC 0x100ull |
418c1742 MG |
121 | |
122 | /* Opcode is supported by PowerPC 403 processor. */ | |
52be03fd | 123 | #define PPC_OPCODE_403 0x200ull |
418c1742 | 124 | |
a09cf9bd | 125 | /* Opcode is supported by PowerPC BookE processor. */ |
52be03fd | 126 | #define PPC_OPCODE_BOOKE 0x400ull |
68d23d21 | 127 | |
fc1e7121 | 128 | /* Opcode is only supported by Power4 architecture. */ |
c03dc33b | 129 | #define PPC_OPCODE_POWER4 0x800ull |
fc1e7121 | 130 | |
c03dc33b AM |
131 | /* Opcode is only supported by e500x2 Core. |
132 | This bit, PPC_OPCODE_EFS, PPC_OPCODE_VLE, and all those with APU in | |
133 | their comment mark opcodes so that when those instructions are used | |
134 | an APUinfo entry can be generated. */ | |
135 | #define PPC_OPCODE_SPE 0x1000ull | |
0449635d | 136 | |
c03dc33b AM |
137 | /* Opcode is supported by Integer select APU. */ |
138 | #define PPC_OPCODE_ISEL 0x2000ull | |
0449635d EZ |
139 | |
140 | /* Opcode is an e500 SPE floating point instruction. */ | |
c03dc33b | 141 | #define PPC_OPCODE_EFS 0x4000ull |
0449635d EZ |
142 | |
143 | /* Opcode is supported by branch locking APU. */ | |
c03dc33b | 144 | #define PPC_OPCODE_BRLOCK 0x8000ull |
0449635d EZ |
145 | |
146 | /* Opcode is supported by performance monitor APU. */ | |
c03dc33b | 147 | #define PPC_OPCODE_PMR 0x10000ull |
0449635d EZ |
148 | |
149 | /* Opcode is supported by cache locking APU. */ | |
c03dc33b | 150 | #define PPC_OPCODE_CACHELCK 0x20000ull |
0449635d EZ |
151 | |
152 | /* Opcode is supported by machine check APU. */ | |
c03dc33b AM |
153 | #define PPC_OPCODE_RFMCI 0x40000ull |
154 | ||
155 | /* Opcode is supported by PowerPC 440 processor. */ | |
156 | #define PPC_OPCODE_440 0x80000ull | |
0449635d | 157 | |
f4411256 | 158 | /* Opcode is only supported by Power5 architecture. */ |
c03dc33b | 159 | #define PPC_OPCODE_POWER5 0x100000ull |
f4411256 | 160 | |
36ae0db3 | 161 | /* Opcode is supported by PowerPC e300 family. */ |
c03dc33b | 162 | #define PPC_OPCODE_E300 0x200000ull |
9622b051 AM |
163 | |
164 | /* Opcode is only supported by Power6 architecture. */ | |
c03dc33b | 165 | #define PPC_OPCODE_POWER6 0x400000ull |
9622b051 | 166 | |
ede602d7 | 167 | /* Opcode is only supported by PowerPC Cell family. */ |
c03dc33b | 168 | #define PPC_OPCODE_CELL 0x800000ull |
36ae0db3 | 169 | |
c3d65c1c | 170 | /* Opcode is supported by CPUs with paired singles support. */ |
c03dc33b | 171 | #define PPC_OPCODE_PPCPS 0x1000000ull |
c3d65c1c | 172 | |
19a6653c | 173 | /* Opcode is supported by Power E500MC */ |
c03dc33b | 174 | #define PPC_OPCODE_E500MC 0x2000000ull |
19a6653c | 175 | |
081ba1b3 | 176 | /* Opcode is supported by PowerPC 405 processor. */ |
c03dc33b | 177 | #define PPC_OPCODE_405 0x4000000ull |
081ba1b3 | 178 | |
9b4e5766 | 179 | /* Opcode is supported by Vector-Scalar (VSX) Unit */ |
c03dc33b AM |
180 | #define PPC_OPCODE_VSX 0x8000000ull |
181 | ||
182 | /* Opcode is only supported by Power7 architecture. */ | |
183 | #define PPC_OPCODE_POWER7 0x10000000ull | |
9b4e5766 | 184 | |
e0d602ec | 185 | /* Opcode is supported by A2. */ |
c03dc33b | 186 | #define PPC_OPCODE_A2 0x20000000ull |
e0d602ec | 187 | |
9fe54b1c | 188 | /* Opcode is supported by PowerPC 476 processor. */ |
52be03fd | 189 | #define PPC_OPCODE_476 0x40000000ull |
9fe54b1c | 190 | |
ce3d2015 | 191 | /* Opcode is supported by AppliedMicro Titan core */ |
c03dc33b | 192 | #define PPC_OPCODE_TITAN 0x80000000ull |
ce3d2015 | 193 | |
e01d869a | 194 | /* Opcode which is supported by the e500 family */ |
c03dc33b | 195 | #define PPC_OPCODE_E500 0x100000000ull |
e01d869a | 196 | |
aea77599 | 197 | /* Opcode is supported by Power E6500 */ |
c03dc33b | 198 | #define PPC_OPCODE_E6500 0x200000000ull |
aea77599 AM |
199 | |
200 | /* Opcode is supported by Thread management APU */ | |
c03dc33b | 201 | #define PPC_OPCODE_TMR 0x400000000ull |
aea77599 | 202 | |
b9c361e0 | 203 | /* Opcode which is supported by the VLE extension. */ |
c03dc33b | 204 | #define PPC_OPCODE_VLE 0x800000000ull |
b9c361e0 | 205 | |
5817ffd1 | 206 | /* Opcode is only supported by Power8 architecture. */ |
c03dc33b | 207 | #define PPC_OPCODE_POWER8 0x1000000000ull |
5817ffd1 | 208 | |
fa758a70 | 209 | /* Opcode is supported by ppc750cl/Gekko/Broadway. */ |
c03dc33b | 210 | #define PPC_OPCODE_750 0x2000000000ull |
ef5a96d5 AM |
211 | |
212 | /* Opcode is supported by ppc7450. */ | |
c03dc33b | 213 | #define PPC_OPCODE_7450 0x4000000000ull |
ef5a96d5 AM |
214 | |
215 | /* Opcode is supported by ppc821/850/860. */ | |
c03dc33b | 216 | #define PPC_OPCODE_860 0x8000000000ull |
ef5a96d5 | 217 | |
a680de9a | 218 | /* Opcode is only supported by Power9 architecture. */ |
c03dc33b | 219 | #define PPC_OPCODE_POWER9 0x10000000000ull |
a680de9a | 220 | |
52be03fd | 221 | /* Opcode is supported by e200z4. */ |
c03dc33b | 222 | #define PPC_OPCODE_E200Z4 0x20000000000ull |
52be03fd AM |
223 | |
224 | /* Disassemble to instructions matching later in the opcode table | |
225 | with fewer "mask" bits set rather than the earlist match. Fewer | |
226 | "mask" bits set imply a more general form of the opcode, in fact | |
227 | the underlying machine instruction. */ | |
c03dc33b | 228 | #define PPC_OPCODE_RAW 0x40000000000ull |
dfdaec14 | 229 | |
e3c2f928 AF |
230 | /* Opcode is supported by PowerPC LSP */ |
231 | #define PPC_OPCODE_LSP 0x80000000000ull | |
232 | ||
74081948 AF |
233 | /* Opcode is only supported by Freescale SPE2 APU. */ |
234 | #define PPC_OPCODE_SPE2 0x100000000000ull | |
235 | ||
236 | /* Opcode is supported by EFS2. */ | |
237 | #define PPC_OPCODE_EFS2 0x200000000000ull | |
238 | ||
7c1f4227 AM |
239 | /* Opcode is only supported by power10 architecture. */ |
240 | #define PPC_OPCODE_POWER10 0x400000000000ull | |
dd7efa79 | 241 | |
33ae8a3a DS |
242 | /* Opcode is only supported by SVP64 extensions (LibreSOC architecture). */ |
243 | #define PPC_OPCODE_SVP64 0x800000000000ull | |
244 | ||
29a6701e PB |
245 | /* Opcode is only supported by 'future' architecture. */ |
246 | #define PPC_OPCODE_FUTURE 0x1000000000000ull | |
247 | ||
252b5132 RH |
248 | /* A macro to extract the major opcode from an instruction. */ |
249 | #define PPC_OP(i) (((i) >> 26) & 0x3f) | |
b9c361e0 JL |
250 | |
251 | /* A macro to determine if the instruction is a 2-byte VLE insn. */ | |
252 | #define PPC_OP_SE_VLE(m) ((m) <= 0xffff) | |
253 | ||
254 | /* A macro to extract the major opcode from a VLE instruction. */ | |
255 | #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f) | |
256 | ||
257 | /* A macro to convert a VLE opcode to a VLE opcode segment. */ | |
258 | #define VLE_OP_TO_SEG(i) ((i) >> 1) | |
74081948 | 259 | |
61a457e5 AM |
260 | /* Map LSP insn to lookup segment for disassembly. */ |
261 | #define LSP_OP_TO_SEG(i) (((i) & 0x7ff) >> 6) | |
262 | ||
74081948 AF |
263 | /* A macro to extract the extended opcode from a SPE2 instruction. */ |
264 | #define SPE2_XOP(i) ((i) & 0x7ff) | |
265 | ||
266 | /* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment. */ | |
267 | #define SPE2_XOP_TO_SEG(i) ((i) >> 7) | |
dd7efa79 PB |
268 | |
269 | /* A macro to extract the prefix word from an 8-byte PREFIX instruction. */ | |
270 | #define PPC_GET_PREFIX(i) (((i) >> 32) & ((1LL << 32) - 1)) | |
271 | ||
272 | /* A macro to extract the suffix word from an 8-byte PREFIX instruction. */ | |
273 | #define PPC_GET_SUFFIX(i) ((i) & ((1LL << 32) - 1)) | |
274 | ||
275 | /* A macro to determine whether insn I is an 8-byte prefix instruction. */ | |
276 | #define PPC_PREFIX_P(i) (PPC_OP (PPC_GET_PREFIX (i)) == 0x1) | |
277 | ||
278 | /* A macro used to hash 8-byte PREFIX instructions. */ | |
279 | #define PPC_PREFIX_SEG(i) (PPC_OP (i) >> 1) | |
280 | ||
252b5132 RH |
281 | \f |
282 | /* The operands table is an array of struct powerpc_operand. */ | |
283 | ||
284 | struct powerpc_operand | |
285 | { | |
b84bf58a | 286 | /* A bitmask of bits in the operand. */ |
0f873fd5 | 287 | uint64_t bitm; |
252b5132 | 288 | |
b9c361e0 JL |
289 | /* The shift operation to be applied to the operand. No shift |
290 | is made if this is zero. For positive values, the operand | |
291 | is shifted left by SHIFT. For negative values, the operand | |
292 | is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate | |
293 | that BITM and SHIFT cannot be used to determine where the | |
294 | operand goes in the insn. */ | |
252b5132 RH |
295 | int shift; |
296 | ||
297 | /* Insertion function. This is used by the assembler. To insert an | |
298 | operand value into an instruction, check this field. | |
299 | ||
300 | If it is NULL, execute | |
b9c361e0 JL |
301 | if (o->shift >= 0) |
302 | i |= (op & o->bitm) << o->shift; | |
303 | else | |
304 | i |= (op & o->bitm) >> -o->shift; | |
252b5132 | 305 | (i is the instruction which we are filling in, o is a pointer to |
b84bf58a | 306 | this structure, and op is the operand value). |
252b5132 RH |
307 | |
308 | If this field is not NULL, then simply call it with the | |
309 | instruction and the operand value. It will return the new value | |
9cf7e568 AM |
310 | of the instruction. If the operand value is illegal, *ERRMSG |
311 | will be set to a warning string (the operand will be inserted in | |
312 | any case). If the operand value is legal, *ERRMSG will be | |
313 | unchanged (most operands can accept any value). */ | |
0f873fd5 PB |
314 | uint64_t (*insert) |
315 | (uint64_t instruction, int64_t op, ppc_cpu_t dialect, const char **errmsg); | |
252b5132 RH |
316 | |
317 | /* Extraction function. This is used by the disassembler. To | |
318 | extract this operand type from an instruction, check this field. | |
319 | ||
320 | If it is NULL, compute | |
b9c361e0 JL |
321 | if (o->shift >= 0) |
322 | op = (i >> o->shift) & o->bitm; | |
323 | else | |
324 | op = (i << -o->shift) & o->bitm; | |
b84bf58a AM |
325 | if ((o->flags & PPC_OPERAND_SIGNED) != 0) |
326 | sign_extend (op); | |
252b5132 | 327 | (i is the instruction, o is a pointer to this structure, and op |
b84bf58a | 328 | is the result). |
252b5132 RH |
329 | |
330 | If this field is not NULL, then simply call it with the | |
9cf7e568 AM |
331 | instruction value. It will return the value of the operand. |
332 | *INVALID will be set to one by the extraction function if this | |
333 | operand type can not be extracted from this operand (i.e., the | |
334 | instruction does not match). If the operand is valid, *INVALID | |
335 | will not be changed. *INVALID will always be non-negative when | |
336 | used to extract a field from an instruction. | |
337 | ||
338 | The extraction function is also called by both the assembler and | |
339 | disassembler if an operand is optional, in which case the | |
340 | function should return the default value of the operand. | |
341 | *INVALID is negative in this case, and is the negative count of | |
342 | omitted optional operands up to and including this operand. */ | |
0f873fd5 | 343 | int64_t (*extract) (uint64_t instruction, ppc_cpu_t dialect, int *invalid); |
252b5132 RH |
344 | |
345 | /* One bit syntax flags. */ | |
346 | unsigned long flags; | |
347 | }; | |
348 | ||
349 | /* Elements in the table are retrieved by indexing with values from | |
350 | the operands field of the powerpc_opcodes table. */ | |
351 | ||
352 | extern const struct powerpc_operand powerpc_operands[]; | |
b84bf58a | 353 | extern const unsigned int num_powerpc_operands; |
252b5132 | 354 | |
b9c361e0 | 355 | /* Use with the shift field of a struct powerpc_operand to indicate |
42952a96 AM |
356 | that BITM and SHIFT cannot be used to determine where the operand |
357 | goes in the insn. */ | |
358 | #define PPC_OPSHIFT_INV (1U << 30) | |
359 | /* A special case, 6-bit SH field. */ | |
360 | #define PPC_OPSHIFT_SH6 (2U << 30) | |
b9c361e0 | 361 | |
7e0de605 AM |
362 | /* Values defined for the flags field of a struct powerpc_operand. |
363 | Keep the register bits low: They need to fit in an unsigned short. */ | |
252b5132 | 364 | |
7e0de605 AM |
365 | /* This operand names a register. The disassembler uses this to print |
366 | register names with a leading 'r'. */ | |
367 | #define PPC_OPERAND_GPR (0x1) | |
252b5132 | 368 | |
7e0de605 AM |
369 | /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ |
370 | #define PPC_OPERAND_GPR_0 (0x2) | |
252b5132 | 371 | |
7e0de605 AM |
372 | /* This operand names a floating point register. The disassembler |
373 | prints these with a leading 'f'. */ | |
374 | #define PPC_OPERAND_FPR (0x4) | |
252b5132 | 375 | |
7e0de605 AM |
376 | /* This operand names a vector unit register. The disassembler |
377 | prints these with a leading 'v'. */ | |
378 | #define PPC_OPERAND_VR (0x8) | |
252b5132 | 379 | |
7e0de605 AM |
380 | /* This operand names a vector-scalar unit register. The disassembler |
381 | prints these with a leading 'vs'. */ | |
382 | #define PPC_OPERAND_VSR (0x10) | |
383 | ||
aa3c112f AM |
384 | /* This operand names a VSX accumulator. */ |
385 | #define PPC_OPERAND_ACC (0x20) | |
386 | ||
79e24d0a PB |
387 | /* This operand names a dense math register. */ |
388 | #define PPC_OPERAND_DMR (0x40) | |
389 | ||
7e0de605 AM |
390 | /* This operand may use the symbolic names for the CR fields (even |
391 | without -mregnames), which are | |
252b5132 RH |
392 | lt 0 gt 1 eq 2 so 3 un 3 |
393 | cr0 0 cr1 1 cr2 2 cr3 3 | |
394 | cr4 4 cr5 5 cr6 6 cr7 7 | |
395 | These may be combined arithmetically, as in cr2*4+gt. These are | |
396 | only supported on the PowerPC, not the POWER. */ | |
79e24d0a | 397 | #define PPC_OPERAND_CR_BIT (0x80) |
252b5132 | 398 | |
7e0de605 | 399 | /* This is a CR FIELD that does not use symbolic names (unless |
96a86c01 AM |
400 | -mregnames is in effect). If both PPC_OPERAND_CR_BIT and |
401 | PPC_OPERAND_CR_REG are set then treat the field as per | |
402 | PPC_OPERAND_CR_BIT for assembly, but as if neither of these | |
403 | bits are set for disassembly. */ | |
79e24d0a | 404 | #define PPC_OPERAND_CR_REG (0x100) |
252b5132 | 405 | |
7e0de605 | 406 | /* This operand names a special purpose register. */ |
79e24d0a | 407 | #define PPC_OPERAND_SPR (0x200) |
fdd12ef3 | 408 | |
7e0de605 | 409 | /* This operand names a paired-single graphics quantization register. */ |
79e24d0a | 410 | #define PPC_OPERAND_GQR (0x400) |
252b5132 RH |
411 | |
412 | /* This operand is a relative branch displacement. The disassembler | |
413 | prints these symbolically if possible. */ | |
79e24d0a | 414 | #define PPC_OPERAND_RELATIVE (0x800) |
252b5132 RH |
415 | |
416 | /* This operand is an absolute branch address. The disassembler | |
417 | prints these symbolically if possible. */ | |
79e24d0a | 418 | #define PPC_OPERAND_ABSOLUTE (0x1000) |
252b5132 | 419 | |
7e0de605 | 420 | /* This operand takes signed values. */ |
79e24d0a | 421 | #define PPC_OPERAND_SIGNED (0x2000) |
252b5132 | 422 | |
7e0de605 AM |
423 | /* This operand takes signed values, but also accepts a full positive |
424 | range of values when running in 32 bit mode. That is, if bits is | |
425 | 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, | |
426 | this flag is ignored. */ | |
79e24d0a | 427 | #define PPC_OPERAND_SIGNOPT (0x4000) |
966f959b | 428 | |
7e0de605 AM |
429 | /* The next operand should be wrapped in parentheses rather than |
430 | separated from this one by a comma. This is used for the load and | |
431 | store instructions which want their operands to look like | |
432 | reg,displacement(reg) | |
433 | */ | |
79e24d0a | 434 | #define PPC_OPERAND_PARENS (0x8000) |
966f959b | 435 | |
a6959011 | 436 | /* This operand is for the DS field in a DS form instruction. */ |
79e24d0a | 437 | #define PPC_OPERAND_DS (0x10000) |
adadcc0c AM |
438 | |
439 | /* This operand is for the DQ field in a DQ form instruction. */ | |
79e24d0a | 440 | #define PPC_OPERAND_DQ (0x20000) |
b84bf58a | 441 | |
7e0de605 AM |
442 | /* This operand should be regarded as a negative number for the |
443 | purposes of overflow checking (i.e., the normal most negative | |
444 | number is disallowed and one more than the normal most positive | |
445 | number is allowed). This flag will only be set for a signed | |
446 | operand. */ | |
79e24d0a | 447 | #define PPC_OPERAND_NEGATIVE (0x40000) |
7e0de605 | 448 | |
3896c469 | 449 | /* Valid range of operand is 0..n rather than 0..n-1. */ |
79e24d0a | 450 | #define PPC_OPERAND_PLUS1 (0x80000) |
081ba1b3 | 451 | |
7e0de605 AM |
452 | /* This operand is optional, and is zero if omitted. This is used for |
453 | example, in the optional BF field in the comparison instructions. The | |
454 | assembler must count the number of operands remaining on the line, | |
455 | and the number of operands remaining for the opcode, and decide | |
456 | whether this operand is present or not. The disassembler should | |
457 | print this operand out only if it is not zero. */ | |
79e24d0a | 458 | #define PPC_OPERAND_OPTIONAL (0x100000) |
b9c361e0 | 459 | |
7e0de605 AM |
460 | /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand |
461 | is omitted, then for the next operand use this operand value plus | |
462 | 1, ignoring the next operand field for the opcode. This wretched | |
463 | hack is needed because the Power rotate instructions can take | |
464 | either 4 or 5 operands. The disassembler should print this operand | |
465 | out regardless of the PPC_OPERAND_OPTIONAL field. */ | |
79e24d0a | 466 | #define PPC_OPERAND_NEXT (0x200000) |
11a0cf2e | 467 | |
a5721ba2 AM |
468 | /* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is |
469 | only optional when generating 32-bit code. */ | |
7e0de605 AM |
470 | #define PPC_OPERAND_OPTIONAL32 (0x400000) |
471 | ||
472 | /* Xilinx APU and FSL related operands */ | |
473 | #define PPC_OPERAND_FSL (0x800000) | |
474 | #define PPC_OPERAND_FCR (0x1000000) | |
475 | #define PPC_OPERAND_UDI (0x2000000) | |
252b5132 | 476 | |
59f08271 DS |
477 | /* Valid range of operand is 1..n rather than 0..n-1. |
478 | Before encoding, the operand value is decremented. | |
479 | After decoding, the operand value is incremented. */ | |
480 | #define PPC_OPERAND_NONZERO (0x4000000) | |
481 | ||
776fc418 | 482 | extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *); |
69fe9ce5 | 483 | |
0f873fd5 | 484 | static inline int64_t |
9cf7e568 AM |
485 | ppc_optional_operand_value (const struct powerpc_operand *operand, |
486 | uint64_t insn, | |
487 | ppc_cpu_t dialect, | |
488 | int num_optional) | |
11a0cf2e | 489 | { |
9cf7e568 AM |
490 | if (operand->extract) |
491 | return (*operand->extract) (insn, dialect, &num_optional); | |
11a0cf2e PB |
492 | return 0; |
493 | } | |
494 | ||
08dc996f | 495 | /* PowerPC VLE insns. */ |
bb6bf75e AM |
496 | #define E_OPCODE_MASK 0xfc00f800 |
497 | ||
08dc996f AM |
498 | /* Form I16L, uses 16A relocs. */ |
499 | #define E_OR2I_INSN 0x7000C000 | |
500 | #define E_AND2I_DOT_INSN 0x7000C800 | |
501 | #define E_OR2IS_INSN 0x7000D000 | |
502 | #define E_LIS_INSN 0x7000E000 | |
503 | #define E_AND2IS_DOT_INSN 0x7000E800 | |
504 | ||
505 | /* Form I16A, uses 16D relocs. */ | |
506 | #define E_ADD2I_DOT_INSN 0x70008800 | |
507 | #define E_ADD2IS_INSN 0x70009000 | |
508 | #define E_CMP16I_INSN 0x70009800 | |
509 | #define E_MULL2I_INSN 0x7000A000 | |
510 | #define E_CMPL16I_INSN 0x7000A800 | |
511 | #define E_CMPH16I_INSN 0x7000B000 | |
512 | #define E_CMPHL16I_INSN 0x7000B800 | |
513 | ||
bb6bf75e AM |
514 | #define E_LI_INSN 0x70000000 |
515 | #define E_LI_MASK 0xfc008000 | |
516 | ||
1fe0971e TS |
517 | #ifdef __cplusplus |
518 | } | |
519 | #endif | |
520 | ||
252b5132 | 521 | #endif /* PPC_H */ |