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Change boolean options to bool instead of int
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e23eba97 1/* riscv.h. RISC-V opcode list for GDB, the GNU debugger.
82704155 2 Copyright (C) 2011-2019 Free Software Foundation, Inc.
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3 Contributed by Andrew Waterman
4
5 This file is part of GDB, GAS, and the GNU binutils.
6
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 3, or (at your option) any later version.
11
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21#ifndef _RISCV_H_
22#define _RISCV_H_
23
24#include "riscv-opc.h"
25#include <stdlib.h>
26#include <stdint.h>
27
28typedef uint64_t insn_t;
29
30static inline unsigned int riscv_insn_length (insn_t insn)
31{
32 if ((insn & 0x3) != 0x3) /* RVC. */
33 return 2;
34 if ((insn & 0x1f) != 0x1f) /* Base ISA and extensions in 32-bit space. */
35 return 4;
36 if ((insn & 0x3f) == 0x1f) /* 48-bit extensions. */
37 return 6;
38 if ((insn & 0x7f) == 0x3f) /* 64-bit extensions. */
39 return 8;
40 /* Longer instructions not supported at the moment. */
41 return 2;
42}
43
44static const char * const riscv_rm[8] =
45{
46 "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
47};
48
49static const char * const riscv_pred_succ[16] =
50{
51 0, "w", "r", "rw", "o", "ow", "or", "orw",
52 "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
53};
54
55#define RVC_JUMP_BITS 11
56#define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
57
58#define RVC_BRANCH_BITS 8
59#define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)
60
61#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
62#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
63
64#define EXTRACT_ITYPE_IMM(x) \
65 (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
66#define EXTRACT_STYPE_IMM(x) \
67 (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
68#define EXTRACT_SBTYPE_IMM(x) \
69 ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
70#define EXTRACT_UTYPE_IMM(x) \
71 ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
72#define EXTRACT_UJTYPE_IMM(x) \
73 ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
74#define EXTRACT_RVC_IMM(x) \
75 (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
76#define EXTRACT_RVC_LUI_IMM(x) \
77 (EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS)
78#define EXTRACT_RVC_SIMM3(x) \
79 (RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2))
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80#define EXTRACT_RVC_UIMM8(x) \
81 (RV_X(x, 5, 8))
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82#define EXTRACT_RVC_ADDI4SPN_IMM(x) \
83 ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
84#define EXTRACT_RVC_ADDI16SP_IMM(x) \
85 ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
86#define EXTRACT_RVC_LW_IMM(x) \
87 ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
88#define EXTRACT_RVC_LD_IMM(x) \
89 ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
90#define EXTRACT_RVC_LWSP_IMM(x) \
91 ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
92#define EXTRACT_RVC_LDSP_IMM(x) \
93 ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
94#define EXTRACT_RVC_SWSP_IMM(x) \
95 ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
96#define EXTRACT_RVC_SDSP_IMM(x) \
97 ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
98#define EXTRACT_RVC_B_IMM(x) \
99 ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
100#define EXTRACT_RVC_J_IMM(x) \
101 ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
102
103#define ENCODE_ITYPE_IMM(x) \
104 (RV_X(x, 0, 12) << 20)
105#define ENCODE_STYPE_IMM(x) \
106 ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
107#define ENCODE_SBTYPE_IMM(x) \
108 ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
109#define ENCODE_UTYPE_IMM(x) \
110 (RV_X(x, 12, 20) << 12)
111#define ENCODE_UJTYPE_IMM(x) \
112 ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
113#define ENCODE_RVC_IMM(x) \
114 ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
115#define ENCODE_RVC_LUI_IMM(x) \
116 ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS)
117#define ENCODE_RVC_SIMM3(x) \
118 (RV_X(x, 0, 3) << 10)
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119#define ENCODE_RVC_UIMM8(x) \
120 (RV_X(x, 0, 8) << 5)
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121#define ENCODE_RVC_ADDI4SPN_IMM(x) \
122 ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
123#define ENCODE_RVC_ADDI16SP_IMM(x) \
124 ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
125#define ENCODE_RVC_LW_IMM(x) \
126 ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
127#define ENCODE_RVC_LD_IMM(x) \
128 ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
129#define ENCODE_RVC_LWSP_IMM(x) \
130 ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
131#define ENCODE_RVC_LDSP_IMM(x) \
132 ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
133#define ENCODE_RVC_SWSP_IMM(x) \
134 ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
135#define ENCODE_RVC_SDSP_IMM(x) \
136 ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
137#define ENCODE_RVC_B_IMM(x) \
138 ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
139#define ENCODE_RVC_J_IMM(x) \
140 ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
141
142#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
143#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
144#define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x))
145#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
146#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x))
147#define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x))
3342be5d 148#define VALID_RVC_LUI_IMM(x) (ENCODE_RVC_LUI_IMM(x) != 0 && EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x))
e23eba97 149#define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x))
0e35537d 150#define VALID_RVC_UIMM8(x) (EXTRACT_RVC_UIMM8(ENCODE_RVC_UIMM8(x)) == (x))
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151#define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x))
152#define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x))
153#define VALID_RVC_LW_IMM(x) (EXTRACT_RVC_LW_IMM(ENCODE_RVC_LW_IMM(x)) == (x))
154#define VALID_RVC_LD_IMM(x) (EXTRACT_RVC_LD_IMM(ENCODE_RVC_LD_IMM(x)) == (x))
155#define VALID_RVC_LWSP_IMM(x) (EXTRACT_RVC_LWSP_IMM(ENCODE_RVC_LWSP_IMM(x)) == (x))
156#define VALID_RVC_LDSP_IMM(x) (EXTRACT_RVC_LDSP_IMM(ENCODE_RVC_LDSP_IMM(x)) == (x))
157#define VALID_RVC_SWSP_IMM(x) (EXTRACT_RVC_SWSP_IMM(ENCODE_RVC_SWSP_IMM(x)) == (x))
158#define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x))
159#define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x))
160#define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x))
161
162#define RISCV_RTYPE(insn, rd, rs1, rs2) \
163 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
164#define RISCV_ITYPE(insn, rd, rs1, imm) \
165 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
166#define RISCV_STYPE(insn, rs1, rs2, imm) \
167 ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
168#define RISCV_SBTYPE(insn, rs1, rs2, target) \
169 ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target))
170#define RISCV_UTYPE(insn, rd, bigimm) \
171 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
172#define RISCV_UJTYPE(insn, rd, target) \
173 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target))
174
175#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
176#define RVC_NOP MATCH_C_ADDI
177
178#define RISCV_CONST_HIGH_PART(VALUE) \
179 (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
180#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
181#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
182#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
183
184#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
185#define RISCV_JUMP_ALIGN_BITS 1
186#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
187#define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)
188
189#define RISCV_IMM_BITS 12
190#define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
191#define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
192#define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
193#define RISCV_RVC_IMM_REACH (1LL << 6)
194#define RISCV_BRANCH_BITS RISCV_IMM_BITS
195#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
196#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
197#define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)
198
199/* RV fields. */
200
201#define OP_MASK_OP 0x7f
202#define OP_SH_OP 0
203#define OP_MASK_RS2 0x1f
204#define OP_SH_RS2 20
205#define OP_MASK_RS1 0x1f
206#define OP_SH_RS1 15
207#define OP_MASK_RS3 0x1f
208#define OP_SH_RS3 27
209#define OP_MASK_RD 0x1f
210#define OP_SH_RD 7
211#define OP_MASK_SHAMT 0x3f
212#define OP_SH_SHAMT 20
213#define OP_MASK_SHAMTW 0x1f
214#define OP_SH_SHAMTW 20
215#define OP_MASK_RM 0x7
216#define OP_SH_RM 12
217#define OP_MASK_PRED 0xf
218#define OP_SH_PRED 24
219#define OP_MASK_SUCC 0xf
220#define OP_SH_SUCC 20
221#define OP_MASK_AQ 0x1
222#define OP_SH_AQ 26
223#define OP_MASK_RL 0x1
224#define OP_SH_RL 25
225
226#define OP_MASK_CUSTOM_IMM 0x7f
227#define OP_SH_CUSTOM_IMM 25
228#define OP_MASK_CSR 0xfff
229#define OP_SH_CSR 20
230
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231#define OP_MASK_FUNCT3 0x7
232#define OP_SH_FUNCT3 12
233#define OP_MASK_FUNCT7 0x7f
234#define OP_SH_FUNCT7 25
235#define OP_MASK_FUNCT2 0x3
236#define OP_SH_FUNCT2 25
237
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238/* RVC fields. */
239
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240#define OP_MASK_OP2 0x3
241#define OP_SH_OP2 0
242
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243#define OP_MASK_CRS2 0x1f
244#define OP_SH_CRS2 2
245#define OP_MASK_CRS1S 0x7
246#define OP_SH_CRS1S 7
247#define OP_MASK_CRS2S 0x7
248#define OP_SH_CRS2S 2
249
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250#define OP_MASK_CFUNCT6 0x3f
251#define OP_SH_CFUNCT6 10
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252#define OP_MASK_CFUNCT4 0xf
253#define OP_SH_CFUNCT4 12
254#define OP_MASK_CFUNCT3 0x7
255#define OP_SH_CFUNCT3 13
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256#define OP_MASK_CFUNCT2 0x3
257#define OP_SH_CFUNCT2 5
0e35537d 258
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259/* ABI names for selected x-registers. */
260
261#define X_RA 1
262#define X_SP 2
263#define X_GP 3
264#define X_TP 4
265#define X_T0 5
266#define X_T1 6
267#define X_T2 7
268#define X_T3 28
269
270#define NGPR 32
271#define NFPR 32
272
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273/* These fake label defines are use by both the assembler, and
274 libopcodes. The assembler uses this when it needs to generate a fake
275 label, and libopcodes uses it to hide the fake labels in its output. */
276#define RISCV_FAKE_LABEL_NAME ".L0 "
277#define RISCV_FAKE_LABEL_CHAR ' '
278
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279/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
280 VALUE << SHIFT. VALUE is evaluated exactly once. */
281#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
282 (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
283 | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
284
285/* Extract bits MASK << SHIFT from STRUCT and shift them right
286 SHIFT places. */
287#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
288 (((STRUCT) >> (SHIFT)) & (MASK))
289
290/* Extract the operand given by FIELD from integer INSN. */
291#define EXTRACT_OPERAND(FIELD, INSN) \
292 EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
293
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294/* The maximal number of subset can be required. */
295#define MAX_SUBSET_NUM 4
296
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297/* This structure holds information for a particular instruction. */
298
299struct riscv_opcode
300{
301 /* The name of the instruction. */
302 const char *name;
43135d3b 303 /* The requirement of xlen for the instruction, 0 if no requirement. */
1080bf78 304 unsigned xlen_requirement;
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305 /* An array of ISA subset name (I, M, A, F, D, Xextension), must ended
306 with a NULL pointer sential. */
307 const char *subset[MAX_SUBSET_NUM];
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308 /* A string describing the arguments for this instruction. */
309 const char *args;
310 /* The basic opcode for the instruction. When assembling, this
311 opcode is modified by the arguments to produce the actual opcode
312 that is used. If pinfo is INSN_MACRO, then this is 0. */
313 insn_t match;
314 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
315 relevant portions of the opcode when disassembling. If the
316 actual opcode anded with the match field equals the opcode field,
317 then we have found the correct instruction. If pinfo is
318 INSN_MACRO, then this field is the macro identifier. */
319 insn_t mask;
320 /* A function to determine if a word corresponds to this instruction.
321 Usually, this computes ((word & mask) == match). */
322 int (*match_func) (const struct riscv_opcode *op, insn_t word);
323 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
324 of bits describing the instruction, notably any relevant hazard
325 information. */
326 unsigned long pinfo;
327};
328
329/* Instruction is a simple alias (e.g. "mv" for "addi"). */
330#define INSN_ALIAS 0x00000001
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331
332/* These are for setting insn_info fields.
333
334 Nonbranch is the default. Noninsn is used only if there is no match.
335 There are no condjsr or dref2 instructions. So that leaves condbranch,
336 branch, jsr, and dref that we need to handle here, encoded in 3 bits. */
337#define INSN_TYPE 0x0000000e
338
339/* Instruction is an unconditional branch. */
340#define INSN_BRANCH 0x00000002
341/* Instruction is a conditional branch. */
342#define INSN_CONDBRANCH 0x00000004
343/* Instruction is a jump to subroutine. */
344#define INSN_JSR 0x00000006
345/* Instruction is a data reference. */
346#define INSN_DREF 0x00000008
347
348/* We have 5 data reference sizes, which we can encode in 3 bits. */
349#define INSN_DATA_SIZE 0x00000070
350#define INSN_DATA_SIZE_SHIFT 4
351#define INSN_1_BYTE 0x00000010
352#define INSN_2_BYTE 0x00000020
353#define INSN_4_BYTE 0x00000030
354#define INSN_8_BYTE 0x00000040
355#define INSN_16_BYTE 0x00000050
356
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357/* Instruction is actually a macro. It should be ignored by the
358 disassembler, and requires special treatment by the assembler. */
359#define INSN_MACRO 0xffffffff
360
361/* This is a list of macro expanded instructions.
362
363 _I appended means immediate
364 _A appended means address
365 _AB appended means address with base register
366 _D appended means 64 bit floating point constant
367 _S appended means 32 bit floating point constant. */
368
369enum
370{
371 M_LA,
372 M_LLA,
373 M_LA_TLS_GD,
374 M_LA_TLS_IE,
375 M_LB,
376 M_LBU,
377 M_LH,
378 M_LHU,
379 M_LW,
380 M_LWU,
381 M_LD,
382 M_SB,
383 M_SH,
384 M_SW,
385 M_SD,
386 M_FLW,
387 M_FLD,
cc917fd9 388 M_FLQ,
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389 M_FSW,
390 M_FSD,
cc917fd9 391 M_FSQ,
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392 M_CALL,
393 M_J,
394 M_LI,
395 M_NUM_MACROS
396};
397
398
399extern const char * const riscv_gpr_names_numeric[NGPR];
400extern const char * const riscv_gpr_names_abi[NGPR];
401extern const char * const riscv_fpr_names_numeric[NFPR];
402extern const char * const riscv_fpr_names_abi[NFPR];
403
404extern const struct riscv_opcode riscv_opcodes[];
0e35537d 405extern const struct riscv_opcode riscv_insn_types[];
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406
407#endif /* _RISCV_H_ */