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RISC-V: Support Zcmp push/pop instructions.
[thirdparty/binutils-gdb.git] / include / opcode / riscv.h
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e23eba97 1/* riscv.h. RISC-V opcode list for GDB, the GNU debugger.
fd67aa11 2 Copyright (C) 2011-2024 Free Software Foundation, Inc.
e23eba97
NC		 3 Contributed by Andrew Waterman
4
5 This file is part of GDB, GAS, and the GNU binutils.
6
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 3, or (at your option) any later version.
11
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21#ifndef _RISCV_H_
22#define _RISCV_H_
23
24#include "riscv-opc.h"
25#include <stdlib.h>
26#include <stdint.h>
27
28typedef uint64_t insn_t;
29
30static inline unsigned int riscv_insn_length (insn_t insn)
31{
dcd709e0 32 if ((insn & 0x3) != 0x3) /* RVC instructions. */
e23eba97 33 return 2;
dcd709e0 34 if ((insn & 0x1f) != 0x1f) /* 32-bit instructions. */
e23eba97 35 return 4;
dcd709e0 36 if ((insn & 0x3f) == 0x1f) /* 48-bit instructions. */
e23eba97 37 return 6;
dcd709e0 38 if ((insn & 0x7f) == 0x3f) /* 64-bit instructions. */
e23eba97 39 return 8;
bb996692
JB		 40 /* 80- ... 176-bit instructions. */
41 if ((insn & 0x7f) == 0x7f && (insn & 0x7000) != 0x7000)
42 return 10 + ((insn >> 11) & 0xe);
73e30e72
TO		 43 /* Maximum value returned by this function. */
44#define RISCV_MAX_INSN_LEN 22
e23eba97
NC		 45 /* Longer instructions not supported at the moment. */
46 return 2;
47}
48
e23eba97
NC		 49#define RVC_JUMP_BITS 11
50#define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
51
52#define RVC_BRANCH_BITS 8
53#define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)
54
55#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
56#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
8b7419c4 57#define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n)))
e23eba97
NC		 58
59#define EXTRACT_ITYPE_IMM(x) \
60 (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
61#define EXTRACT_STYPE_IMM(x) \
62 (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
5a9f5403 63#define EXTRACT_BTYPE_IMM(x) \
e23eba97
NC		 64 ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
65#define EXTRACT_UTYPE_IMM(x) \
66 ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
5a9f5403 67#define EXTRACT_JTYPE_IMM(x) \
e23eba97 68 ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
5a9f5403 69#define EXTRACT_CITYPE_IMM(x) \
e23eba97 70 (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
5a9f5403
NC		 71#define EXTRACT_CITYPE_LUI_IMM(x) \
72 (EXTRACT_CITYPE_IMM (x) << RISCV_IMM_BITS)
73#define EXTRACT_CITYPE_ADDI16SP_IMM(x) \
e23eba97 74 ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
5a9f5403 75#define EXTRACT_CITYPE_LWSP_IMM(x) \
e23eba97 76 ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
5a9f5403 77#define EXTRACT_CITYPE_LDSP_IMM(x) \
e23eba97 78 ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
5a9f5403
NC		 79#define EXTRACT_CSSTYPE_IMM(x) \
80 (RV_X(x, 7, 6) << 0)
81#define EXTRACT_CSSTYPE_SWSP_IMM(x) \
e23eba97 82 ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
5a9f5403 83#define EXTRACT_CSSTYPE_SDSP_IMM(x) \
e23eba97 84 ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
5a9f5403
NC		 85#define EXTRACT_CIWTYPE_IMM(x) \
86 (RV_X(x, 5, 8))
87#define EXTRACT_CIWTYPE_ADDI4SPN_IMM(x) \
88 ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
89#define EXTRACT_CLTYPE_IMM(x) \
90 ((RV_X(x, 5, 2) << 0) | (RV_X(x, 10, 3) << 2))
91#define EXTRACT_CLTYPE_LW_IMM(x) \
92 ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
93#define EXTRACT_CLTYPE_LD_IMM(x) \
94 ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
95#define EXTRACT_CBTYPE_IMM(x) \
e23eba97 96 ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
5a9f5403 97#define EXTRACT_CJTYPE_IMM(x) \
e23eba97 98 ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
65e4a99a
NC		 99#define EXTRACT_RVV_VI_IMM(x) \
100 (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
101#define EXTRACT_RVV_VI_UIMM(x) \
102 (RV_X(x, 15, 5))
c8cb3734
CM		 103#define EXTRACT_RVV_VI_UIMM6(x) \
104 (RV_X(x, 15, 5) | (RV_X(x, 26, 1) << 5))
65e4a99a
NC		 105#define EXTRACT_RVV_OFFSET(x) \
106 (RV_X(x, 29, 3))
107#define EXTRACT_RVV_VB_IMM(x) \
108 (RV_X(x, 20, 10))
109#define EXTRACT_RVV_VC_IMM(x) \
110 (RV_X(x, 20, 11))
b5c37946
SJ		 111#define EXTRACT_ZCB_BYTE_UIMM(x) \
112 (RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1))
113#define EXTRACT_ZCB_HALFWORD_UIMM(x) \
114 (RV_X(x, 5, 1) << 1)
9132c815
J		 115#define EXTRACT_ZCMP_SPIMM(x) \
116 (RV_X(x, 2, 2) << 4)
ccb388ca 117/* Vendor-specific (CORE-V) extract macros. */
d1bd9787
MB		 118#define EXTRACT_CV_IS2_UIMM5(x) \
119 (RV_X(x, 20, 5))
ccb388ca
MB		 120#define EXTRACT_CV_IS3_UIMM5(x) \
121 (RV_X(x, 25, 5))
e23eba97
NC		 122
123#define ENCODE_ITYPE_IMM(x) \
124 (RV_X(x, 0, 12) << 20)
125#define ENCODE_STYPE_IMM(x) \
126 ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
5a9f5403 127#define ENCODE_BTYPE_IMM(x) \
e23eba97
NC		 128 ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
129#define ENCODE_UTYPE_IMM(x) \
130 (RV_X(x, 12, 20) << 12)
5a9f5403 131#define ENCODE_JTYPE_IMM(x) \
e23eba97 132 ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
5a9f5403 133#define ENCODE_CITYPE_IMM(x) \
e23eba97 134 ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
5a9f5403
NC		 135#define ENCODE_CITYPE_LUI_IMM(x) \
136 ENCODE_CITYPE_IMM ((x) >> RISCV_IMM_BITS)
137#define ENCODE_CITYPE_ADDI16SP_IMM(x) \
e23eba97 138 ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
5a9f5403 139#define ENCODE_CITYPE_LWSP_IMM(x) \
e23eba97 140 ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
5a9f5403 141#define ENCODE_CITYPE_LDSP_IMM(x) \
e23eba97 142 ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
5a9f5403
NC		 143#define ENCODE_CSSTYPE_IMM(x) \
144 (RV_X(x, 0, 6) << 7)
145#define ENCODE_CSSTYPE_SWSP_IMM(x) \
e23eba97 146 ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
5a9f5403 147#define ENCODE_CSSTYPE_SDSP_IMM(x) \
e23eba97 148 ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
5a9f5403
NC		 149#define ENCODE_CIWTYPE_IMM(x) \
150 (RV_X(x, 0, 8) << 5)
151#define ENCODE_CIWTYPE_ADDI4SPN_IMM(x) \
152 ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
153#define ENCODE_CLTYPE_IMM(x) \
154 ((RV_X(x, 0, 2) << 5) | (RV_X(x, 2, 3) << 10))
155#define ENCODE_CLTYPE_LW_IMM(x) \
156 ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
157#define ENCODE_CLTYPE_LD_IMM(x) \
158 ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
159#define ENCODE_CBTYPE_IMM(x) \
e23eba97 160 ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
5a9f5403 161#define ENCODE_CJTYPE_IMM(x) \
e23eba97 162 ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
65e4a99a
NC		 163#define ENCODE_RVV_VB_IMM(x) \
164 (RV_X(x, 0, 10) << 20)
165#define ENCODE_RVV_VC_IMM(x) \
166 (RV_X(x, 0, 11) << 20)
c8cb3734
CM		 167#define ENCODE_RVV_VI_UIMM6(x) \
168 (RV_X(x, 0, 5) << 15 | RV_X(x, 5, 1) << 26)
b5c37946
SJ		 169#define ENCODE_ZCB_BYTE_UIMM(x) \
170 ((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5))
171#define ENCODE_ZCB_HALFWORD_UIMM(x) \
172 (RV_X(x, 1, 1) << 5)
9132c815
J		 173#define ENCODE_ZCMP_SPIMM(x) \
174 (RV_X(x, 4, 2) << 2)
ccb388ca 175/* Vendor-specific (CORE-V) encode macros. */
d1bd9787
MB		 176#define ENCODE_CV_IS2_UIMM5(x) \
177 (RV_X(x, 0, 5) << 20)
ccb388ca
MB		 178#define ENCODE_CV_IS3_UIMM5(x) \
179 (RV_X(x, 0, 5) << 25)
e23eba97
NC		 180
181#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
182#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
5a9f5403 183#define VALID_BTYPE_IMM(x) (EXTRACT_BTYPE_IMM(ENCODE_BTYPE_IMM(x)) == (x))
e23eba97 184#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
5a9f5403
NC		 185#define VALID_JTYPE_IMM(x) (EXTRACT_JTYPE_IMM(ENCODE_JTYPE_IMM(x)) == (x))
186#define VALID_CITYPE_IMM(x) (EXTRACT_CITYPE_IMM(ENCODE_CITYPE_IMM(x)) == (x))
187#define VALID_CITYPE_LUI_IMM(x) (ENCODE_CITYPE_LUI_IMM(x) != 0 \
188 && EXTRACT_CITYPE_LUI_IMM(ENCODE_CITYPE_LUI_IMM(x)) == (x))
189#define VALID_CITYPE_ADDI16SP_IMM(x) (ENCODE_CITYPE_ADDI16SP_IMM(x) != 0 \
190 && EXTRACT_CITYPE_ADDI16SP_IMM(ENCODE_CITYPE_ADDI16SP_IMM(x)) == (x))
191#define VALID_CITYPE_LWSP_IMM(x) (EXTRACT_CITYPE_LWSP_IMM(ENCODE_CITYPE_LWSP_IMM(x)) == (x))
192#define VALID_CITYPE_LDSP_IMM(x) (EXTRACT_CITYPE_LDSP_IMM(ENCODE_CITYPE_LDSP_IMM(x)) == (x))
193#define VALID_CSSTYPE_IMM(x) (EXTRACT_CSSTYPE_IMM(ENCODE_CSSTYPE_IMM(x)) == (x))
194#define VALID_CSSTYPE_SWSP_IMM(x) (EXTRACT_CSSTYPE_SWSP_IMM(ENCODE_CSSTYPE_SWSP_IMM(x)) == (x))
195#define VALID_CSSTYPE_SDSP_IMM(x) (EXTRACT_CSSTYPE_SDSP_IMM(ENCODE_CSSTYPE_SDSP_IMM(x)) == (x))
196#define VALID_CIWTYPE_IMM(x) (EXTRACT_CIWTYPE_IMM(ENCODE_CIWTYPE_IMM(x)) == (x))
197#define VALID_CIWTYPE_ADDI4SPN_IMM(x) (EXTRACT_CIWTYPE_ADDI4SPN_IMM(ENCODE_CIWTYPE_ADDI4SPN_IMM(x)) == (x))
198#define VALID_CLTYPE_IMM(x) (EXTRACT_CLTYPE_IMM(ENCODE_CLTYPE_IMM(x)) == (x))
199#define VALID_CLTYPE_LW_IMM(x) (EXTRACT_CLTYPE_LW_IMM(ENCODE_CLTYPE_LW_IMM(x)) == (x))
200#define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x))
201#define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x))
202#define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x))
65e4a99a
NC		 203#define VALID_RVV_VB_IMM(x) (EXTRACT_RVV_VB_IMM(ENCODE_RVV_VB_IMM(x)) == (x))
204#define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x))
b5c37946
SJ		 205#define VALID_ZCB_BYTE_UIMM(x) (EXTRACT_ZCB_BYTE_UIMM(ENCODE_ZCB_BYTE_UIMM(x)) == (x))
206#define VALID_ZCB_HALFWORD_UIMM(x) (EXTRACT_ZCB_HALFWORD_UIMM(ENCODE_ZCB_HALFWORD_UIMM(x)) == (x))
9132c815 207#define VALID_ZCMP_SPIMM(x) (EXTRACT_ZCMP_SPIMM(ENCODE_ZCMP_SPIMM(x)) == (x))
e23eba97
NC		 208
209#define RISCV_RTYPE(insn, rd, rs1, rs2) \
210 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
211#define RISCV_ITYPE(insn, rd, rs1, imm) \
212 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
213#define RISCV_STYPE(insn, rs1, rs2, imm) \
214 ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
5a9f5403
NC		 215#define RISCV_BTYPE(insn, rs1, rs2, target) \
216 ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_BTYPE_IMM(target))
e23eba97
NC		 217#define RISCV_UTYPE(insn, rd, bigimm) \
218 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
5a9f5403
NC		 219#define RISCV_JTYPE(insn, rd, target) \
220 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_JTYPE_IMM(target))
e23eba97
NC		 221
222#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
223#define RVC_NOP MATCH_C_ADDI
224
225#define RISCV_CONST_HIGH_PART(VALUE) \
226 (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
227#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
228#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
229#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
230
231#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
232#define RISCV_JUMP_ALIGN_BITS 1
233#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
234#define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)
235
236#define RISCV_IMM_BITS 12
237#define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
238#define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
239#define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
240#define RISCV_RVC_IMM_REACH (1LL << 6)
241#define RISCV_BRANCH_BITS RISCV_IMM_BITS
242#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
243#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
244#define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)
245
246/* RV fields. */
247
248#define OP_MASK_OP 0x7f
249#define OP_SH_OP 0
250#define OP_MASK_RS2 0x1f
251#define OP_SH_RS2 20
252#define OP_MASK_RS1 0x1f
253#define OP_SH_RS1 15
1174d920 254#define OP_MASK_RS3 0x1fU
e23eba97
NC		 255#define OP_SH_RS3 27
256#define OP_MASK_RD 0x1f
257#define OP_SH_RD 7
258#define OP_MASK_SHAMT 0x3f
259#define OP_SH_SHAMT 20
260#define OP_MASK_SHAMTW 0x1f
261#define OP_SH_SHAMTW 20
262#define OP_MASK_RM 0x7
263#define OP_SH_RM 12
264#define OP_MASK_PRED 0xf
265#define OP_SH_PRED 24
266#define OP_MASK_SUCC 0xf
267#define OP_SH_SUCC 20
268#define OP_MASK_AQ 0x1
269#define OP_SH_AQ 26
270#define OP_MASK_RL 0x1
271#define OP_SH_RL 25
272
1174d920 273#define OP_MASK_CSR 0xfffU
e23eba97
NC		 274#define OP_SH_CSR 20
275
1942a048
NC		 276#define OP_MASK_FUNCT3 0x7
277#define OP_SH_FUNCT3 12
278#define OP_MASK_FUNCT7 0x7fU
279#define OP_SH_FUNCT7 25
280#define OP_MASK_FUNCT2 0x3
281#define OP_SH_FUNCT2 25
0e35537d 282
e23eba97
NC		 283/* RVC fields. */
284
1942a048
NC		 285#define OP_MASK_OP2 0x3
286#define OP_SH_OP2 0
287
288#define OP_MASK_CRS2 0x1f
289#define OP_SH_CRS2 2
290#define OP_MASK_CRS1S 0x7
291#define OP_SH_CRS1S 7
292#define OP_MASK_CRS2S 0x7
293#define OP_SH_CRS2S 2
294
295#define OP_MASK_CFUNCT6 0x3f
296#define OP_SH_CFUNCT6 10
297#define OP_MASK_CFUNCT4 0xf
298#define OP_SH_CFUNCT4 12
299#define OP_MASK_CFUNCT3 0x7
300#define OP_SH_CFUNCT3 13
301#define OP_MASK_CFUNCT2 0x3
302#define OP_SH_CFUNCT2 5
0e35537d 303
3d1cafa0 304/* Scalar crypto fields. */
305
306#define OP_SH_BS 30
307#define OP_MASK_BS 3
308#define OP_SH_RNUM 20
309#define OP_MASK_RNUM 0xf
310
65e4a99a
NC		 311/* RVV fields. */
312
313#define OP_MASK_VD 0x1f
314#define OP_SH_VD 7
315#define OP_MASK_VS1 0x1f
316#define OP_SH_VS1 15
317#define OP_MASK_VS2 0x1f
318#define OP_SH_VS2 20
319#define OP_MASK_VIMM 0x1f
320#define OP_SH_VIMM 15
321#define OP_MASK_VMASK 0x1
322#define OP_SH_VMASK 25
323#define OP_MASK_VFUNCT6 0x3f
324#define OP_SH_VFUNCT6 26
325#define OP_MASK_VLMUL 0x7
326#define OP_SH_VLMUL 0
327#define OP_MASK_VSEW 0x7
328#define OP_SH_VSEW 3
329#define OP_MASK_VTA 0x1
330#define OP_SH_VTA 6
331#define OP_MASK_VMA 0x1
332#define OP_SH_VMA 7
65e4a99a
NC		 333#define OP_MASK_VWD 0x1
334#define OP_SH_VWD 26
335
6a95962e
JM		 336#define OP_MASK_XTHEADVLMUL 0x3
337#define OP_SH_XTHEADVLMUL 0
338#define OP_MASK_XTHEADVSEW 0x7
339#define OP_SH_XTHEADVSEW 2
340#define OP_MASK_XTHEADVEDIV 0x3
341#define OP_SH_XTHEADVEDIV 5
342#define OP_MASK_XTHEADVTYPE_RES 0xf
343#define OP_SH_XTHEADVTYPE_RES 7
344
9132c815
J		 345/* Zc fields. */
346#define OP_MASK_REG_LIST 0xf
347#define OP_SH_REG_LIST 4
348#define ZCMP_SP_ALIGNMENT 16
349
65e4a99a
NC		 350#define NVECR 32
351#define NVECM 1
352
248bf6de
NC		 353/* SiFive fields. */
354#define OP_MASK_XSO2 0x3
355#define OP_SH_XSO2 26
356#define OP_MASK_XSO1 0x1
357#define OP_SH_XSO1 26
358
e23eba97
NC		 359/* ABI names for selected x-registers. */
360
361#define X_RA 1
362#define X_SP 2
363#define X_GP 3
364#define X_TP 4
365#define X_T0 5
366#define X_T1 6
367#define X_T2 7
9132c815
J		 368#define X_S0 8
369#define X_S1 9
370#define X_S2 18
371#define X_S10 26
372#define X_S11 27
e23eba97
NC		 373#define X_T3 28
374
375#define NGPR 32
376#define NFPR 32
377
884b49e3
AB		 378/* These fake label defines are use by both the assembler, and
379 libopcodes. The assembler uses this when it needs to generate a fake
380 label, and libopcodes uses it to hide the fake labels in its output. */
381#define RISCV_FAKE_LABEL_NAME ".L0 "
382#define RISCV_FAKE_LABEL_CHAR ' '
383
e23eba97
NC		 384/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
385 VALUE << SHIFT. VALUE is evaluated exactly once. */
386#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
387 (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
388 | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
389
390/* Extract bits MASK << SHIFT from STRUCT and shift them right
391 SHIFT places. */
392#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
393 (((STRUCT) >> (SHIFT)) & (MASK))
394
395/* Extract the operand given by FIELD from integer INSN. */
396#define EXTRACT_OPERAND(FIELD, INSN) \
02a63525 397 ((unsigned int) EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD))
e23eba97 398
8b7419c4
CM		 399/* Extract an unsigned immediate operand on position s with n bits. */
400#define EXTRACT_U_IMM(n, s, l) \
401 RV_X (l, s, n)
402
403/* Extract an signed immediate operand on position s with n bits. */
404#define EXTRACT_S_IMM(n, s, l) \
405 RV_X_SIGNED (l, s, n)
406
407/* Validate that unsigned n-bit immediate is within bounds. */
408#define VALIDATE_U_IMM(v, n) \
409 ((unsigned long) v < (1UL << n))
410
411/* Validate that signed n-bit immediate is within bounds. */
412#define VALIDATE_S_IMM(v, n) \
413 (v < (long) (1UL << (n-1)) && v >= -(offsetT) (1UL << (n-1)))
414
dcd709e0 415/* The maximal number of subset can be required. */
43135d3b
JW		 416#define MAX_SUBSET_NUM 4
417
7e9ad3a3 418/* All RISC-V instructions belong to at least one of these classes. */
7e9ad3a3 419enum riscv_insn_class
1942a048
NC		 420{
421 INSN_CLASS_NONE,
422
423 INSN_CLASS_I,
424 INSN_CLASS_C,
425 INSN_CLASS_A,
426 INSN_CLASS_M,
427 INSN_CLASS_F,
428 INSN_CLASS_D,
429 INSN_CLASS_Q,
430 INSN_CLASS_F_AND_C,
431 INSN_CLASS_D_AND_C,
b625eff8 432 INSN_CLASS_ZICOND,
1942a048
NC		 433 INSN_CLASS_ZICSR,
434 INSN_CLASS_ZIFENCEI,
2266f863
TO		 435 INSN_CLASS_ZIHINTNTL,
436 INSN_CLASS_ZIHINTNTL_AND_C,
1942a048 437 INSN_CLASS_ZIHINTPAUSE,
0938b032 438 INSN_CLASS_ZMMUL,
eb668e50 439 INSN_CLASS_ZAWRS,
136ea874
NC		 440 INSN_CLASS_F_INX,
441 INSN_CLASS_D_INX,
442 INSN_CLASS_Q_INX,
443 INSN_CLASS_ZFH_INX,
045f385d 444 INSN_CLASS_ZFHMIN,
136ea874
NC		 445 INSN_CLASS_ZFHMIN_INX,
446 INSN_CLASS_ZFHMIN_AND_D_INX,
447 INSN_CLASS_ZFHMIN_AND_Q_INX,
1f3fc45b
CM		 448 INSN_CLASS_ZFA,
449 INSN_CLASS_D_AND_ZFA,
450 INSN_CLASS_Q_AND_ZFA,
451 INSN_CLASS_ZFH_AND_ZFA,
239af8cb 452 INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA,
80d49d6a
KLC		 453 INSN_CLASS_ZBA,
454 INSN_CLASS_ZBB,
455 INSN_CLASS_ZBC,
9455c919 456 INSN_CLASS_ZBS,
3d1cafa0 457 INSN_CLASS_ZBKB,
458 INSN_CLASS_ZBKC,
459 INSN_CLASS_ZBKX,
460 INSN_CLASS_ZKND,
461 INSN_CLASS_ZKNE,
462 INSN_CLASS_ZKNH,
463 INSN_CLASS_ZKSED,
464 INSN_CLASS_ZKSH,
465 INSN_CLASS_ZBB_OR_ZBKB,
466 INSN_CLASS_ZBC_OR_ZBKC,
467 INSN_CLASS_ZKND_OR_ZKNE,
65e4a99a
NC		 468 INSN_CLASS_V,
469 INSN_CLASS_ZVEF,
c8cb3734 470 INSN_CLASS_ZVBB,
c0a98a85 471 INSN_CLASS_ZVBC,
ea1bd007 472 INSN_CLASS_ZVKB,
9d469329 473 INSN_CLASS_ZVKG,
fce8fef9 474 INSN_CLASS_ZVKNED,
62edb233 475 INSN_CLASS_ZVKNHA_OR_ZVKNHB,
5ec6edd0 476 INSN_CLASS_ZVKSED,
259a2647 477 INSN_CLASS_ZVKSH,
b5c37946
SJ		 478 INSN_CLASS_ZCB,
479 INSN_CLASS_ZCB_AND_ZBA,
480 INSN_CLASS_ZCB_AND_ZBB,
481 INSN_CLASS_ZCB_AND_ZMMUL,
9132c815 482 INSN_CLASS_ZCMP,
23ff54c2 483 INSN_CLASS_SVINVAL,
41d6ac5d 484 INSN_CLASS_ZICBOM,
3b374308 485 INSN_CLASS_ZICBOP,
41d6ac5d 486 INSN_CLASS_ZICBOZ,
dac0b8a4 487 INSN_CLASS_ZABHA,
c625f4ed 488 INSN_CLASS_H,
ccb388ca 489 INSN_CLASS_XCVMAC,
d1bd9787 490 INSN_CLASS_XCVALU,
8254c3d2
CM		 491 INSN_CLASS_XTHEADBA,
492 INSN_CLASS_XTHEADBB,
493 INSN_CLASS_XTHEADBS,
a9ba8bc2 494 INSN_CLASS_XTHEADCMO,
73442230 495 INSN_CLASS_XTHEADCONDMOV,
f511f80f 496 INSN_CLASS_XTHEADFMEMIDX,
4a3bc79b 497 INSN_CLASS_XTHEADFMV,
01804a09 498 INSN_CLASS_XTHEADINT,
4041e11d 499 INSN_CLASS_XTHEADMAC,
27cfd142 500 INSN_CLASS_XTHEADMEMIDX,
6e17ae62 501 INSN_CLASS_XTHEADMEMPAIR,
547c18d9 502 INSN_CLASS_XTHEADSYNC,
86fbfedd 503 INSN_CLASS_XTHEADVECTOR,
4d8f1ff3 504 INSN_CLASS_XTHEADZVAMO,
1656d3f8 505 INSN_CLASS_XVENTANACONDOPS,
248bf6de 506 INSN_CLASS_XSFVCP,
1942a048 507};
7e9ad3a3 508
e23eba97 509/* This structure holds information for a particular instruction. */
e23eba97
NC		 510struct riscv_opcode
511{
512 /* The name of the instruction. */
513 const char *name;
1942a048 514
43135d3b 515 /* The requirement of xlen for the instruction, 0 if no requirement. */
1080bf78 516 unsigned xlen_requirement;
1942a048 517
7e9ad3a3
JW		 518 /* Class to which this instruction belongs. Used to decide whether or
519 not this instruction is legal in the current -march context. */
520 enum riscv_insn_class insn_class;
1942a048 521
e23eba97
NC		 522 /* A string describing the arguments for this instruction. */
523 const char *args;
1942a048 524
e23eba97
NC		 525 /* The basic opcode for the instruction. When assembling, this
526 opcode is modified by the arguments to produce the actual opcode
527 that is used. If pinfo is INSN_MACRO, then this is 0. */
528 insn_t match;
1942a048 529
e23eba97
NC		 530 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
531 relevant portions of the opcode when disassembling. If the
532 actual opcode anded with the match field equals the opcode field,
533 then we have found the correct instruction. If pinfo is
534 INSN_MACRO, then this field is the macro identifier. */
535 insn_t mask;
1942a048 536
e23eba97
NC		 537 /* A function to determine if a word corresponds to this instruction.
538 Usually, this computes ((word & mask) == match). */
539 int (*match_func) (const struct riscv_opcode *op, insn_t word);
1942a048 540
e23eba97
NC		 541 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
542 of bits describing the instruction, notably any relevant hazard
543 information. */
544 unsigned long pinfo;
545};
546
547/* Instruction is a simple alias (e.g. "mv" for "addi"). */
548#define INSN_ALIAS 0x00000001
eb41b248
JW		 549
550/* These are for setting insn_info fields.
551
552 Nonbranch is the default. Noninsn is used only if there is no match.
553 There are no condjsr or dref2 instructions. So that leaves condbranch,
554 branch, jsr, and dref that we need to handle here, encoded in 3 bits. */
555#define INSN_TYPE 0x0000000e
556
557/* Instruction is an unconditional branch. */
558#define INSN_BRANCH 0x00000002
559/* Instruction is a conditional branch. */
560#define INSN_CONDBRANCH 0x00000004
561/* Instruction is a jump to subroutine. */
562#define INSN_JSR 0x00000006
563/* Instruction is a data reference. */
564#define INSN_DREF 0x00000008
65e4a99a
NC		 565/* Instruction is allowed when eew >= 64. */
566#define INSN_V_EEW64 0x10000000
eb41b248
JW		 567
568/* We have 5 data reference sizes, which we can encode in 3 bits. */
569#define INSN_DATA_SIZE 0x00000070
570#define INSN_DATA_SIZE_SHIFT 4
571#define INSN_1_BYTE 0x00000010
572#define INSN_2_BYTE 0x00000020
573#define INSN_4_BYTE 0x00000030
574#define INSN_8_BYTE 0x00000040
575#define INSN_16_BYTE 0x00000050
576
e23eba97
NC		 577/* Instruction is actually a macro. It should be ignored by the
578 disassembler, and requires special treatment by the assembler. */
579#define INSN_MACRO 0xffffffff
580
dcd709e0 581/* This is a list of macro expanded instructions. */
e23eba97
NC		 582enum
583{
584 M_LA,
585 M_LLA,
ec2260af 586 M_LGA,
e23eba97
NC		 587 M_LA_TLS_GD,
588 M_LA_TLS_IE,
c76820a0
JB		 589 M_Lx,
590 M_FLx,
591 M_Sx_FSx,
e23eba97
NC		 592 M_CALL,
593 M_J,
594 M_LI,
eb5e952f 595 M_EXTH,
c2137f55
NC		 596 M_ZEXTW,
597 M_SEXTB,
65e4a99a 598 M_VMSGE,
e23eba97
NC		 599 M_NUM_MACROS
600};
601
9b9b1092
NC		 602/* The mapping symbol states. */
603enum riscv_seg_mstate
604{
605 MAP_NONE = 0, /* Must be zero, for seginfo in new sections. */
606 MAP_DATA, /* Data. */
607 MAP_INSN, /* Instructions. */
608};
e23eba97 609
02a63525
JB		 610#define NRC (4 + 1) /* Max characters in register names, incl nul. */
611
612extern const char riscv_gpr_names_numeric[NGPR][NRC];
613extern const char riscv_gpr_names_abi[NGPR][NRC];
614extern const char riscv_fpr_names_numeric[NFPR][NRC];
615extern const char riscv_fpr_names_abi[NFPR][NRC];
3d9d92c2
TO		 616extern const char * const riscv_rm[8];
617extern const char * const riscv_pred_succ[16];
02a63525
JB		 618extern const char riscv_vecr_names_numeric[NVECR][NRC];
619extern const char riscv_vecm_names_numeric[NVECM][NRC];
65e4a99a
NC		 620extern const char * const riscv_vsew[8];
621extern const char * const riscv_vlmul[8];
622extern const char * const riscv_vta[2];
623extern const char * const riscv_vma[2];
6a95962e
JM		 624extern const char * const riscv_th_vlen[4];
625extern const char * const riscv_th_vediv[4];
1f3fc45b
CM		 626extern const char * const riscv_fli_symval[32];
627extern const float riscv_fli_numval[32];
e23eba97
NC		 628
629extern const struct riscv_opcode riscv_opcodes[];
0e35537d 630extern const struct riscv_opcode riscv_insn_types[];
e23eba97 631
9132c815
J		 632extern unsigned int riscv_get_sp_base (insn_t, unsigned int);
633
e23eba97 634#endif /* _RISCV_H_ */
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