[thirdparty/binutils-gdb.git] / include / opcode / score-inst.h

/* score-inst.h -- Score Instructions Table
   Copyright 2006 Free Software Foundation, Inc.
   Contributed by: 
   Mei Ligang (ligang@sunnorth.com.cn)
   Pei-Lin Tsai (pltsai@sunplus.com)

   This file is part of GAS, the GNU Assembler.

   GAS is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2, or (at your option)
   any later version.

   GAS is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS; see the file COPYING.  If not, write to the Free
   Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
   02110-1301, USA.  */

#ifndef SCORE_INST_H
#define SCORE_INST_H

#define LDST_UNALIGN_MASK 0x0000007f
#define UA_LCB		  0x00000060
#define UA_LCW		  0x00000062
#define UA_LCE		  0x00000066
#define UA_SCB		  0x00000068
#define UA_SCW		  0x0000006a
#define UA_SCE		  0x0000006e
#define UA_LL		  0x0000000c
#define UA_SC		  0x0000000e
#define LDST16_RR_MASK   0x0000000f
#define N16_LW           8
#define N16_LH           9
#define N16_POP          10
#define N16_LBU          11
#define N16_SW           12
#define N16_SH           13
#define N16_PUSH         14
#define N16_SB           15
#define LDST16_RI_MASK   0x7007
#define N16_LWP          0x7000
#define N16_LHP          0x7001
#define N16_LBUP         0x7003
#define N16_SWP          0x7004
#define N16_SHP          0x7005
#define N16_SBP          0x7007
#define N16_LIU          0x5000

#define OPC_PSEUDOLDST_MASK	0x00000007

enum
{
  INSN_LW = 0,
  INSN_LH = 1,
  INSN_LHU = 2,
  INSN_LB = 3,
  INSN_SW = 4,
  INSN_SH = 5,
  INSN_LBU = 6,
  INSN_SB = 7,
};

/* Sub opcdoe opcode.  */
enum
{
  INSN16_LBU = 11,
  INSN16_LH = 9,
  INSN16_LW = 8,
  INSN16_SB = 15,
  INSN16_SH = 13,
  INSN16_SW = 12,
};

enum
{
  LDST_NOUPDATE = 0,
  LDST_PRE = 1,
  LDST_POST = 2,
};

enum score_insn_type
{
  Rd_I4,
  Rd_I5,
  Rd_rvalueBP_I5,
  Rd_lvalueBP_I5,
  Rd_Rs_I5,
  x_Rs_I5,
  x_I5_x,
  Rd_I8,
  Rd_Rs_I14,
  I15,
  Rd_I16,
  Rd_rvalueRs_SI10,
  Rd_lvalueRs_SI10,
  Rd_rvalueRs_preSI12,
  Rd_rvalueRs_postSI12,
  Rd_lvalueRs_preSI12,
  Rd_lvalueRs_postSI12,
  Rd_Rs_SI14,
  Rd_rvalueRs_SI15,
  Rd_lvalueRs_SI15,
  Rd_SI16,
  PC_DISP8div2,
  PC_DISP11div2,
  PC_DISP19div2,
  PC_DISP24div2,
  Rd_Rs_Rs,
  x_Rs_x,
  x_Rs_Rs,
  Rd_Rs_x,
  Rd_x_Rs,
  Rd_x_x,
  Rd_Rs,
  Rd_HighRs,
  Rd_lvalueRs,
  Rd_rvalueRs,
  Rd_lvalue32Rs,
  Rd_rvalue32Rs,
  x_Rs,
  NO_OPD,
  NO16_OPD,
  OP5_rvalueRs_SI15,
  I5_Rs_Rs_I5_OP5,
  x_rvalueRs_post4,
  Rd_rvalueRs_post4,
  Rd_x_I5,
  Rd_lvalueRs_post4,
  x_lvalueRs_post4,
  Rd_LowRs,
  Rd_Rs_Rs_imm,
  Insn_Type_PCE,
  Insn_Type_SYN,
  Insn_GP,
  Insn_PIC,
};

enum score_data_type
{
  _IMM4 = 0,
  _IMM5,
  _IMM8,
  _IMM14,
  _IMM15,
  _IMM16,
  _SIMM10 = 6,
  _SIMM12,
  _SIMM14,
  _SIMM15,
  _SIMM16,
  _SIMM14_NEG = 11,
  _IMM16_NEG,
  _SIMM16_NEG,
  _IMM20,
  _IMM25,
  _DISP8div2 = 16,
  _DISP11div2,
  _DISP19div2,
  _DISP24div2,
  _VALUE,
  _VALUE_HI16,
  _VALUE_LO16,
  _VALUE_LDST_LO16 = 23,
  _SIMM16_LA,
  _IMM5_RSHIFT_1,
  _IMM5_RSHIFT_2,
  _SIMM16_LA_POS,
  _IMM5_RANGE_8_31,
  _IMM10_RSHIFT_2,
  _GP_IMM15 = 30,
  _GP_IMM14 = 31,
  _SIMM16_pic = 42,   /* Index in score_df_range.  */
  _IMM16_LO16_pic = 43,
  _IMM16_pic = 44,
};

#define REG_TMP			  1

#define OP_REG_TYPE             (1 << 6)
#define OP_IMM_TYPE             (1 << 7)
#define OP_SH_REGD              (OP_REG_TYPE |20)
#define	OP_SH_REGS1             (OP_REG_TYPE |15)
#define OP_SH_REGS2             (OP_REG_TYPE |10)
#define OP_SH_I                 (OP_IMM_TYPE | 1)
#define OP_SH_RI15              (OP_IMM_TYPE | 0)
#define OP_SH_I12               (OP_IMM_TYPE | 3)
#define OP_SH_DISP24            (OP_IMM_TYPE | 1)
#define OP_SH_DISP19_p1         (OP_IMM_TYPE |15)
#define OP_SH_DISP19_p2         (OP_IMM_TYPE | 1)
#define OP_SH_I5                (OP_IMM_TYPE |10)
#define OP_SH_I10               (OP_IMM_TYPE | 5)
#define OP_SH_COPID             (OP_IMM_TYPE | 5)
#define OP_SH_TRAPI5            (OP_IMM_TYPE |15)
#define OP_SH_I15               (OP_IMM_TYPE |10)

#define OP16_SH_REGD            (OP_REG_TYPE | 8)
#define	OP16_SH_REGS1           (OP_REG_TYPE | 4)
#define	OP16_SH_I45             (OP_IMM_TYPE | 3)
#define	OP16_SH_I8              (OP_IMM_TYPE | 0)
#define OP16_SH_DISP8           (OP_IMM_TYPE | 0)
#define OP16_SH_DISP11          (OP_IMM_TYPE | 1)

struct datafield_range
{
  int data_type;
  int bits;
  int range[2];
};

struct datafield_range score_df_range[] =
{
  {_IMM4,             4,  {0, (1 << 4) - 1}},	        /* (     0 ~ 15   ) */
  {_IMM5,             5,  {0, (1 << 5) - 1}},	        /* (     0 ~ 31   ) */
  {_IMM8,             8,  {0, (1 << 8) - 1}},	        /* (     0 ~ 255  ) */
  {_IMM14,            14, {0, (1 << 14) - 1}},	        /* (     0 ~ 16383) */
  {_IMM15,            15, {0, (1 << 15) - 1}},	        /* (     0 ~ 32767) */
  {_IMM16,            16, {0, (1 << 16) - 1}},	        /* (     0 ~ 65535) */
  {_SIMM10,           10, {-(1 << 9), (1 << 9) - 1}},	/* (  -512 ~ 511  ) */
  {_SIMM12,           12, {-(1 << 11), (1 << 11) - 1}},	/* ( -2048 ~ 2047 ) */
  {_SIMM14,           14, {-(1 << 13), (1 << 13) - 1}},	/* ( -8192 ~ 8191 ) */
  {_SIMM15,           15, {-(1 << 14), (1 << 14) - 1}},	/* (-16384 ~ 16383) */
  {_SIMM16,           16, {-(1 << 15), (1 << 15) - 1}},	/* (-32768 ~ 32767) */
  {_SIMM14_NEG,       14, {-(1 << 13), (1 << 13) - 1}},	/* ( -8191 ~ 8192 ) */
  {_IMM16_NEG,        16, {0, (1 << 16) - 1}},	        /* (-65535 ~ 0    ) */
  {_SIMM16_NEG,       16, {-(1 << 15), (1 << 15) - 1}},	/* (-32768 ~ 32767) */
  {_IMM20,            20, {0, (1 << 20) - 1}},
  {_IMM25,            25, {0, (1 << 25) - 1}},
  {_DISP8div2,        8,  {-(1 << 8), (1 << 8) - 1}},	/* (  -256 ~ 255  ) */
  {_DISP11div2,       11, {0, 0}},
  {_DISP19div2,       19, {-(1 << 19), (1 << 19) - 1}},	/* (-524288 ~ 524287) */
  {_DISP24div2,       24, {0, 0}},
  {_VALUE,            32, {0, ((unsigned int)1 << 31) - 1}},
  {_VALUE_HI16,       16, {0, (1 << 16) - 1}},
  {_VALUE_LO16,       16, {0, (1 << 16) - 1}},
  {_VALUE_LDST_LO16,  16, {0, (1 << 16) - 1}},
  {_SIMM16_LA,        16, {-(1 << 15), (1 << 15) - 1}},	/* (-32768 ~ 32767) */
  {_IMM5_RSHIFT_1,    5,  {0, (1 << 6) - 1}},	        /* (     0 ~ 63   ) */
  {_IMM5_RSHIFT_2,    5,  {0, (1 << 7) - 1}},	        /* (     0 ~ 127  ) */
  {_SIMM16_LA_POS,    16, {0, (1 << 15) - 1}},	        /* (     0 ~ 32767) */
  {_IMM5_RANGE_8_31,  5,  {8, 31}},	                /* But for cop0 the valid data : (8 ~ 31). */
  {_IMM10_RSHIFT_2,   10, {-(1 << 11), (1 << 11) - 1}},	/* For ldc#, stc#. */
  {_SIMM10,           10, {0, (1 << 10) - 1}},	        /* ( -1024 ~ 1023 ) */
  {_SIMM12,           12, {0, (1 << 12) - 1}},	        /* ( -2048 ~ 2047 ) */
  {_SIMM14,           14, {0, (1 << 14) - 1}},          /* ( -8192 ~ 8191 ) */
  {_SIMM15,           15, {0, (1 << 15) - 1}},	        /* (-16384 ~ 16383) */
  {_SIMM16,           16, {0, (1 << 16) - 1}},	        /* (-65536 ~ 65536) */
  {_SIMM14_NEG,       14, {0, (1 << 16) - 1}},          /* ( -8191 ~ 8192 ) */
  {_IMM16_NEG,        16, {0, (1 << 16) - 1}},	        /* ( 65535 ~ 0    ) */
  {_SIMM16_NEG,       16, {0, (1 << 16) - 1}},	        /* ( 65535 ~ 0    ) */
  {_IMM20,            20, {0, (1 << 20) - 1}},	        /* (-32768 ~ 32767) */
  {_IMM25,            25, {0, (1 << 25) - 1}},	        /* (-32768 ~ 32767) */
  {_GP_IMM15,         15, {0, (1 << 15) - 1}},	        /* (     0 ~ 65535) */
  {_GP_IMM14,         14, {0, (1 << 14) - 1}},	        /* (     0 ~ 65535) */
  {_SIMM16_pic,       16, {-(1 << 15), (1 << 15) - 1}},	/* (-32768 ~ 32767) */
  {_IMM16_LO16_pic,   16, {0, (1 << 16) - 1}},	        /* ( 65535 ~ 0    ) */
  {_IMM16_pic,        16, {0, (1 << 16) - 1}},	        /* (     0 ~ 65535) */
};

struct shift_bitmask
{
  int opd_type;
  int opd_num;
  struct datafield_range *df_range;
  int sh[4];
  long fieldbits[4];
};

struct shift_bitmask score_sh_bits_map[] =
{
  {
   Rd_I4, 2, &score_df_range[_IMM4],
   {OP16_SH_REGD, OP16_SH_I45, 0, 0},
   {0xf, 0xf, 0, 0},
   },
  {
   Rd_I5, 2, &score_df_range[_IMM5],
   {OP16_SH_REGD, OP16_SH_I45, 0, 0},
   {0xf, 0x1f, 0, 0},
   },
  {
   Rd_rvalueBP_I5, 2, &score_df_range[_IMM5],
   {OP16_SH_REGD, OP16_SH_I45, 0, 0},
   {0xf, 0x1f, 0, 0},
   },
  {
   Rd_lvalueBP_I5, 2, &score_df_range[_IMM5],
   {OP16_SH_REGD, OP16_SH_I45, 0, 0},
   {0xf, 0x1f, 0, 0},
   },
  {
   Rd_Rs_I5, 3, &score_df_range[_IMM5],
   {OP_SH_REGD, OP_SH_REGS1, OP_SH_I5, 0},
   {0x1f, 0x1f, 0x1f, 0},
   },
  {
   x_Rs_I5, 2, &score_df_range[_IMM5],
   {OP_SH_REGS1, OP_SH_I5, 0, 0},
   {0x1f, 0x1f, 0, 0},
   },
  {
   x_I5_x, 1, &score_df_range[_IMM5],
   {OP_SH_TRAPI5, 0, 0, 0},
   {0x1f, 0, 0, 0},
   },
  {
   Rd_I8, 2, &score_df_range[_IMM8],
   {OP16_SH_REGD, OP16_SH_I8, 0, 0},
   {0xf, 0xff, 0, 0},
   },
  {
   Rd_Rs_I14, 3, &score_df_range[_IMM14],
   {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
   {0x1f, 0x1f, 0x3fff, 0},
   },
  {
   I15, 1, &score_df_range[_IMM15],
   {OP_SH_I15, 0, 0, 0},
   {0x7fff, 0, 0, 0},
   },
  {
   Rd_I16, 2, &score_df_range[_IMM16],
   {OP_SH_REGD, OP_SH_I, 0, 0},
   {0x1f, 0xffff, 0, 0},
   },
  {
   Rd_rvalueRs_SI10, 3, &score_df_range[_SIMM10],
   {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
   {0x1f, 0x1f, 0x3ff, 0},
   },
  {
   Rd_lvalueRs_SI10, 3, &score_df_range[_SIMM10],
   {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
   {0x1f, 0x1f, 0x3ff, 0},
   },
  {
   Rd_rvalueRs_preSI12, 3, &score_df_range[_SIMM12],
   {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
   {0xf, 0xf, 0xfff, 0},
   },
  {
   Rd_rvalueRs_postSI12, 3, &score_df_range[_SIMM12],
   {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
   {0xf, 0xf, 0xfff, 0},
   },
  {
   Rd_lvalueRs_preSI12, 3, &score_df_range[_SIMM12],
   {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
   {0xf, 0xf, 0xfff, 0},
   },
  {
   Rd_lvalueRs_postSI12, 3, &score_df_range[_SIMM12],
   {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
   {0xf, 0xf, 0xfff, 0},
   },
  {
   Rd_Rs_SI14, 3, &score_df_range[_SIMM14],
   {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
   {0x1f, 0x1f, 0x3fff, 0},
   },
  {
   Rd_rvalueRs_SI15, 3, &score_df_range[_SIMM15],
   {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
   {0x1f, 0x1f, 0x7fff, 0},
   },
  {
   Rd_lvalueRs_SI15, 3, &score_df_range[_SIMM15],
   {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
   {0x1f, 0x1f, 0x7fff, 0},
   },
  {
   Rd_SI16, 2, &score_df_range[_SIMM16],
   {OP_SH_REGD, OP_SH_I, 0, 0},
   {0x1f, 0xffff, 0, 0},
   },
  {
   PC_DISP8div2, 1, &score_df_range[_DISP8div2],
   {OP16_SH_DISP8, 0, 0, 0},
   {0xff, 0, 0, 0},
   },
  {
   PC_DISP11div2, 1, &score_df_range[_DISP11div2],
   {OP16_SH_DISP11, 0, 0, 0},
   {0x7ff, 0, 0, 0},
   },
  {
   PC_DISP19div2, 2, &score_df_range[_DISP19div2],
   {OP_SH_DISP19_p1, OP_SH_DISP19_p2, 0, 0},
   {0x3ff, 0x1ff, 0, 0},
   },
  {
   PC_DISP24div2, 1, &score_df_range[_DISP24div2],
   {OP_SH_DISP24, 0, 0, 0},
   {0xffffff, 0, 0, 0},
   },
  {
   Rd_Rs_Rs, 3, NULL,
   {OP_SH_REGD, OP_SH_REGS1, OP_SH_REGS2, 0},
   {0x1f, 0x1f, 0x1f, 0}
   },
  {
   Rd_Rs_x, 2, NULL,
   {OP_SH_REGD, OP_SH_REGS1, 0, 0},
   {0x1f, 0x1f, 0, 0},
   },
  {
   Rd_x_Rs, 2, NULL,
   {OP_SH_REGD, OP_SH_REGS2, 0, 0},
   {0x1f, 0x1f, 0, 0},
   },
  {
   Rd_x_x, 1, NULL,
   {OP_SH_REGD, 0, 0, 0},
   {0x1f, 0, 0, 0},
   },
  {
   x_Rs_Rs, 2, NULL,
   {OP_SH_REGS1, OP_SH_REGS2, 0, 0},
   {0x1f, 0x1f, 0, 0},
   },
  {
   x_Rs_x, 1, NULL,
   {OP_SH_REGS1, 0, 0, 0},
   {0x1f, 0, 0, 0},
   },
  {
   Rd_Rs, 2, NULL,
   {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
   {0xf, 0xf, 0, 0},
   },
  {
   Rd_HighRs, 2, NULL,
   {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
   {0xf, 0xf, 0x1f, 0},
   },
  {
   Rd_rvalueRs, 2, NULL,
   {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
   {0xf, 0xf, 0, 0},
   },
  {
   Rd_lvalueRs, 2, NULL,
   {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
   {0xf, 0xf, 0, 0}
   },
   {
   Rd_lvalue32Rs, 2, NULL,
   {OP_SH_REGD, OP_SH_REGS1, 0, 0},
   {0x1f, 0x1f, 0, 0},
   },
   {
   Rd_rvalue32Rs, 2, NULL,
   {OP_SH_REGD, OP_SH_REGS1, 0, 0},
   {0x1f, 0x1f, 0, 0},
   },
  {
   x_Rs, 1, NULL,
   {OP16_SH_REGS1, 0, 0, 0},
   {0xf, 0, 0, 0},
   },
  {
   NO_OPD, 0, NULL,
   {0, 0, 0, 0},
   {0, 0, 0, 0},
   },
  {
   NO16_OPD, 0, NULL,
   {0, 0, 0, 0},
   {0, 0, 0, 0},
   },
};

struct asm_opcode
{
  /* Instruction name.  */
  const char *template;

  /* Instruction Opcode.  */
  unsigned long value;

  /* Instruction bit mask.  */
  unsigned long bitmask;

  /* Relax instruction opcode.  0x8000 imply no relaxation.  */
  unsigned long relax_value;

  /* Instruction type.  */
  enum score_insn_type type;

  /* Function to call to parse args.  */
  void (*parms) (char *);
};

enum insn_class
{
  INSN_CLASS_16,
  INSN_CLASS_32,
  INSN_CLASS_PCE,
  INSN_CLASS_SYN
};

#endif
Commit	Line	Data
1c0d3aa6 NC	1	/* score-inst.h -- Score Instructions Table
	2	Copyright 2006 Free Software Foundation, Inc.
	3	Contributed by:
	4	Mei Ligang (ligang@sunnorth.com.cn)
	5	Pei-Lin Tsai (pltsai@sunplus.com)
	6
	7	This file is part of GAS, the GNU Assembler.
	8
	9	GAS is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation; either version 2, or (at your option)
	12	any later version.
	13
	14	GAS is distributed in the hope that it will be useful,
	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License
	20	along with GAS; see the file COPYING. If not, write to the Free
	21	Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
	22	02110-1301, USA. */
	23
	24	#ifndef SCORE_INST_H
	25	#define SCORE_INST_H
	26
	27	#define LDST_UNALIGN_MASK 0x0000007f
	28	#define UA_LCB 0x00000060
	29	#define UA_LCW 0x00000062
	30	#define UA_LCE 0x00000066
	31	#define UA_SCB 0x00000068
	32	#define UA_SCW 0x0000006a
	33	#define UA_SCE 0x0000006e
	34	#define UA_LL 0x0000000c
	35	#define UA_SC 0x0000000e
	36	#define LDST16_RR_MASK 0x0000000f
	37	#define N16_LW 8
	38	#define N16_LH 9
	39	#define N16_POP 10
	40	#define N16_LBU 11
	41	#define N16_SW 12
	42	#define N16_SH 13
	43	#define N16_PUSH 14
	44	#define N16_SB 15
	45	#define LDST16_RI_MASK 0x7007
	46	#define N16_LWP 0x7000
	47	#define N16_LHP 0x7001
	48	#define N16_LBUP 0x7003
	49	#define N16_SWP 0x7004
	50	#define N16_SHP 0x7005
	51	#define N16_SBP 0x7007
	52	#define N16_LIU 0x5000
	53
	54	#define OPC_PSEUDOLDST_MASK 0x00000007
	55
	56	enum
	57	{
	58	INSN_LW = 0,
	59	INSN_LH = 1,
	60	INSN_LHU = 2,
	61	INSN_LB = 3,
	62	INSN_SW = 4,
	63	INSN_SH = 5,
	64	INSN_LBU = 6,
65	INSN_SB = 7,
66	};
67
68	/* Sub opcdoe opcode. */
69	enum
70	{
71	INSN16_LBU = 11,
72	INSN16_LH = 9,
73	INSN16_LW = 8,
74	INSN16_SB = 15,
75	INSN16_SH = 13,
76	INSN16_SW = 12,
77	};
78
79	enum
80	{
81	LDST_NOUPDATE = 0,
82	LDST_PRE = 1,
83	LDST_POST = 2,
84	};
85
86	enum score_insn_type
87	{
88	Rd_I4,
89	Rd_I5,
90	Rd_rvalueBP_I5,
91	Rd_lvalueBP_I5,
92	Rd_Rs_I5,
93	x_Rs_I5,
94	x_I5_x,
95	Rd_I8,
96	Rd_Rs_I14,
97	I15,
98	Rd_I16,
99	Rd_rvalueRs_SI10,
100	Rd_lvalueRs_SI10,
101	Rd_rvalueRs_preSI12,
102	Rd_rvalueRs_postSI12,
103	Rd_lvalueRs_preSI12,
104	Rd_lvalueRs_postSI12,
105	Rd_Rs_SI14,
106	Rd_rvalueRs_SI15,
107	Rd_lvalueRs_SI15,
108	Rd_SI16,
109	PC_DISP8div2,
110	PC_DISP11div2,
111	PC_DISP19div2,
112	PC_DISP24div2,
113	Rd_Rs_Rs,
114	x_Rs_x,
115	x_Rs_Rs,
116	Rd_Rs_x,
117	Rd_x_Rs,
118	Rd_x_x,
119	Rd_Rs,
120	Rd_HighRs,
121	Rd_lvalueRs,
122	Rd_rvalueRs,
123	Rd_lvalue32Rs,
124	Rd_rvalue32Rs,
125	x_Rs,
126	NO_OPD,
127	NO16_OPD,
128	OP5_rvalueRs_SI15,
129	I5_Rs_Rs_I5_OP5,
130	x_rvalueRs_post4,
131	Rd_rvalueRs_post4,
132	Rd_x_I5,
133	Rd_lvalueRs_post4,
134	x_lvalueRs_post4,
135	Rd_LowRs,
136	Rd_Rs_Rs_imm,
137	Insn_Type_PCE,
138	Insn_Type_SYN,
139	Insn_GP,
140	Insn_PIC,
141	};
142
143	enum score_data_type
144	{
145	_IMM4 = 0,
146	_IMM5,
147	_IMM8,
148	_IMM14,
149	_IMM15,
150	_IMM16,
151	_SIMM10 = 6,
152	_SIMM12,
153	_SIMM14,
154	_SIMM15,
155	_SIMM16,
156	_SIMM14_NEG = 11,
157	_IMM16_NEG,
158	_SIMM16_NEG,
159	_IMM20,
160	_IMM25,
161	_DISP8div2 = 16,
162	_DISP11div2,
163	_DISP19div2,
164	_DISP24div2,
165	_VALUE,
166	_VALUE_HI16,
167	_VALUE_LO16,
168	_VALUE_LDST_LO16 = 23,
169	_SIMM16_LA,
170	_IMM5_RSHIFT_1,
171	_IMM5_RSHIFT_2,
172	_SIMM16_LA_POS,
173	_IMM5_RANGE_8_31,
174	_IMM10_RSHIFT_2,
175	_GP_IMM15 = 30,
176	_GP_IMM14 = 31,
177	_SIMM16_pic = 42, /* Index in score_df_range. */
178	_IMM16_LO16_pic = 43,
179	_IMM16_pic = 44,
180	};
181
182	#define REG_TMP 1
183
184	#define OP_REG_TYPE (1 << 6)
185	#define OP_IMM_TYPE (1 << 7)
186	#define OP_SH_REGD (OP_REG_TYPE \|20)
187	#define OP_SH_REGS1 (OP_REG_TYPE \|15)
188	#define OP_SH_REGS2 (OP_REG_TYPE \|10)
189	#define OP_SH_I (OP_IMM_TYPE \| 1)
190	#define OP_SH_RI15 (OP_IMM_TYPE \| 0)
191	#define OP_SH_I12 (OP_IMM_TYPE \| 3)
192	#define OP_SH_DISP24 (OP_IMM_TYPE \| 1)
193	#define OP_SH_DISP19_p1 (OP_IMM_TYPE \|15)
194	#define OP_SH_DISP19_p2 (OP_IMM_TYPE \| 1)
195	#define OP_SH_I5 (OP_IMM_TYPE \|10)
196	#define OP_SH_I10 (OP_IMM_TYPE \| 5)
197	#define OP_SH_COPID (OP_IMM_TYPE \| 5)
198	#define OP_SH_TRAPI5 (OP_IMM_TYPE \|15)
199	#define OP_SH_I15 (OP_IMM_TYPE \|10)
200
201	#define OP16_SH_REGD (OP_REG_TYPE \| 8)
202	#define OP16_SH_REGS1 (OP_REG_TYPE \| 4)
203	#define OP16_SH_I45 (OP_IMM_TYPE \| 3)
204	#define OP16_SH_I8 (OP_IMM_TYPE \| 0)
205	#define OP16_SH_DISP8 (OP_IMM_TYPE \| 0)
206	#define OP16_SH_DISP11 (OP_IMM_TYPE \| 1)
207
208	struct datafield_range
209	{
210	int data_type;
211	int bits;
212	int range[2];
213	};
214
215	struct datafield_range score_df_range[] =
216	{
217	{_IMM4, 4, {0, (1 << 4) - 1}}, /* ( 0 ~ 15 ) */
218	{_IMM5, 5, {0, (1 << 5) - 1}}, /* ( 0 ~ 31 ) */
219	{_IMM8, 8, {0, (1 << 8) - 1}}, /* ( 0 ~ 255 ) */
220	{_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 16383) */
221	{_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */
222	{_IMM16, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */
223	{_SIMM10, 10, {-(1 << 9), (1 << 9) - 1}}, /* ( -512 ~ 511 ) */
224	{_SIMM12, 12, {-(1 << 11), (1 << 11) - 1}}, /* ( -2048 ~ 2047 ) */
225	{_SIMM14, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8192 ~ 8191 ) */
226	{_SIMM15, 15, {-(1 << 14), (1 << 14) - 1}}, /* (-16384 ~ 16383) */
227	{_SIMM16, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
228	{_SIMM14_NEG, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8191 ~ 8192 ) */
229	{_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* (-65535 ~ 0 ) */
230	{_SIMM16_NEG, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
231	{_IMM20, 20, {0, (1 << 20) - 1}},
232	{_IMM25, 25, {0, (1 << 25) - 1}},
233	{_DISP8div2, 8, {-(1 << 8), (1 << 8) - 1}}, /* ( -256 ~ 255 ) */
234	{_DISP11div2, 11, {0, 0}},
235	{_DISP19div2, 19, {-(1 << 19), (1 << 19) - 1}}, /* (-524288 ~ 524287) */
236	{_DISP24div2, 24, {0, 0}},
237	{_VALUE, 32, {0, ((unsigned int)1 << 31) - 1}},
238	{_VALUE_HI16, 16, {0, (1 << 16) - 1}},
239	{_VALUE_LO16, 16, {0, (1 << 16) - 1}},
240	{_VALUE_LDST_LO16, 16, {0, (1 << 16) - 1}},
241	{_SIMM16_LA, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
242	{_IMM5_RSHIFT_1, 5, {0, (1 << 6) - 1}}, /* ( 0 ~ 63 ) */
243	{_IMM5_RSHIFT_2, 5, {0, (1 << 7) - 1}}, /* ( 0 ~ 127 ) */
244	{_SIMM16_LA_POS, 16, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */
245	{_IMM5_RANGE_8_31, 5, {8, 31}}, /* But for cop0 the valid data : (8 ~ 31). */
246	{_IMM10_RSHIFT_2, 10, {-(1 << 11), (1 << 11) - 1}}, /* For ldc#, stc#. */
247	{_SIMM10, 10, {0, (1 << 10) - 1}}, /* ( -1024 ~ 1023 ) */
248	{_SIMM12, 12, {0, (1 << 12) - 1}}, /* ( -2048 ~ 2047 ) */
249	{_SIMM14, 14, {0, (1 << 14) - 1}}, /* ( -8192 ~ 8191 ) */
250	{_SIMM15, 15, {0, (1 << 15) - 1}}, /* (-16384 ~ 16383) */
251	{_SIMM16, 16, {0, (1 << 16) - 1}}, /* (-65536 ~ 65536) */
252	{_SIMM14_NEG, 14, {0, (1 << 16) - 1}}, /* ( -8191 ~ 8192 ) */
253	{_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
254	{_SIMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
255	{_IMM20, 20, {0, (1 << 20) - 1}}, /* (-32768 ~ 32767) */
256	{_IMM25, 25, {0, (1 << 25) - 1}}, /* (-32768 ~ 32767) */
257	{_GP_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 65535) */
258	{_GP_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 65535) */
259	{_SIMM16_pic, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
260	{_IMM16_LO16_pic, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
261	{_IMM16_pic, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */
262	};
263
264	struct shift_bitmask
265	{
266	int opd_type;
267	int opd_num;
268	struct datafield_range *df_range;
269	int sh[4];
270	long fieldbits[4];
271	};
272
273	struct shift_bitmask score_sh_bits_map[] =
274	{
275	{
276	Rd_I4, 2, &score_df_range[_IMM4],
277	{OP16_SH_REGD, OP16_SH_I45, 0, 0},
278	{0xf, 0xf, 0, 0},
279	},
280	{
281	Rd_I5, 2, &score_df_range[_IMM5],
282	{OP16_SH_REGD, OP16_SH_I45, 0, 0},
283	{0xf, 0x1f, 0, 0},
284	},
285	{
286	Rd_rvalueBP_I5, 2, &score_df_range[_IMM5],
287	{OP16_SH_REGD, OP16_SH_I45, 0, 0},
288	{0xf, 0x1f, 0, 0},
289	},
290	{
291	Rd_lvalueBP_I5, 2, &score_df_range[_IMM5],
292	{OP16_SH_REGD, OP16_SH_I45, 0, 0},
293	{0xf, 0x1f, 0, 0},
294	},
295	{
296	Rd_Rs_I5, 3, &score_df_range[_IMM5],
297	{OP_SH_REGD, OP_SH_REGS1, OP_SH_I5, 0},
298	{0x1f, 0x1f, 0x1f, 0},
299	},
300	{
301	x_Rs_I5, 2, &score_df_range[_IMM5],
302	{OP_SH_REGS1, OP_SH_I5, 0, 0},
303	{0x1f, 0x1f, 0, 0},
304	},
305	{
306	x_I5_x, 1, &score_df_range[_IMM5],
307	{OP_SH_TRAPI5, 0, 0, 0},
308	{0x1f, 0, 0, 0},
309	},
310	{
311	Rd_I8, 2, &score_df_range[_IMM8],
312	{OP16_SH_REGD, OP16_SH_I8, 0, 0},
313	{0xf, 0xff, 0, 0},
314	},
315	{
316	Rd_Rs_I14, 3, &score_df_range[_IMM14],
317	{OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
318	{0x1f, 0x1f, 0x3fff, 0},
319	},
320	{
321	I15, 1, &score_df_range[_IMM15],
322	{OP_SH_I15, 0, 0, 0},
323	{0x7fff, 0, 0, 0},
324	},
325	{
326	Rd_I16, 2, &score_df_range[_IMM16],
327	{OP_SH_REGD, OP_SH_I, 0, 0},
328	{0x1f, 0xffff, 0, 0},
329	},
330	{
331	Rd_rvalueRs_SI10, 3, &score_df_range[_SIMM10],
332	{OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
333	{0x1f, 0x1f, 0x3ff, 0},
334	},
335	{
336	Rd_lvalueRs_SI10, 3, &score_df_range[_SIMM10],
337	{OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
338	{0x1f, 0x1f, 0x3ff, 0},
339	},
340	{
341	Rd_rvalueRs_preSI12, 3, &score_df_range[_SIMM12],
342	{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
343	{0xf, 0xf, 0xfff, 0},
344	},
345	{
346	Rd_rvalueRs_postSI12, 3, &score_df_range[_SIMM12],
347	{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
348	{0xf, 0xf, 0xfff, 0},
349	},
350	{
351	Rd_lvalueRs_preSI12, 3, &score_df_range[_SIMM12],
352	{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
353	{0xf, 0xf, 0xfff, 0},
354	},
355	{
356	Rd_lvalueRs_postSI12, 3, &score_df_range[_SIMM12],
357	{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
358	{0xf, 0xf, 0xfff, 0},
359	},
360	{
361	Rd_Rs_SI14, 3, &score_df_range[_SIMM14],
362	{OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
363	{0x1f, 0x1f, 0x3fff, 0},
364	},
365	{
366	Rd_rvalueRs_SI15, 3, &score_df_range[_SIMM15],
367	{OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
368	{0x1f, 0x1f, 0x7fff, 0},
369	},
370	{
371	Rd_lvalueRs_SI15, 3, &score_df_range[_SIMM15],
372	{OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
373	{0x1f, 0x1f, 0x7fff, 0},
374	},
375	{
376	Rd_SI16, 2, &score_df_range[_SIMM16],
377	{OP_SH_REGD, OP_SH_I, 0, 0},
378	{0x1f, 0xffff, 0, 0},
379	},
380	{
381	PC_DISP8div2, 1, &score_df_range[_DISP8div2],
382	{OP16_SH_DISP8, 0, 0, 0},
383	{0xff, 0, 0, 0},
384	},
385	{
386	PC_DISP11div2, 1, &score_df_range[_DISP11div2],
387	{OP16_SH_DISP11, 0, 0, 0},
388	{0x7ff, 0, 0, 0},
389	},
390	{
391	PC_DISP19div2, 2, &score_df_range[_DISP19div2],
392	{OP_SH_DISP19_p1, OP_SH_DISP19_p2, 0, 0},
393	{0x3ff, 0x1ff, 0, 0},
394	},
395	{
396	PC_DISP24div2, 1, &score_df_range[_DISP24div2],
397	{OP_SH_DISP24, 0, 0, 0},
398	{0xffffff, 0, 0, 0},
399	},
400	{
401	Rd_Rs_Rs, 3, NULL,
402	{OP_SH_REGD, OP_SH_REGS1, OP_SH_REGS2, 0},
403	{0x1f, 0x1f, 0x1f, 0}
404	},
405	{
406	Rd_Rs_x, 2, NULL,
407	{OP_SH_REGD, OP_SH_REGS1, 0, 0},
408	{0x1f, 0x1f, 0, 0},
409	},
410	{
411	Rd_x_Rs, 2, NULL,
412	{OP_SH_REGD, OP_SH_REGS2, 0, 0},
413	{0x1f, 0x1f, 0, 0},
414	},
415	{
416	Rd_x_x, 1, NULL,
417	{OP_SH_REGD, 0, 0, 0},
418	{0x1f, 0, 0, 0},
419	},
420	{
421	x_Rs_Rs, 2, NULL,
422	{OP_SH_REGS1, OP_SH_REGS2, 0, 0},
423	{0x1f, 0x1f, 0, 0},
424	},
425	{
426	x_Rs_x, 1, NULL,
427	{OP_SH_REGS1, 0, 0, 0},
428	{0x1f, 0, 0, 0},
429	},
430	{
431	Rd_Rs, 2, NULL,
432	{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
433	{0xf, 0xf, 0, 0},
434	},
435	{
436	Rd_HighRs, 2, NULL,
437	{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
438	{0xf, 0xf, 0x1f, 0},
439	},
440	{
441	Rd_rvalueRs, 2, NULL,
442	{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
443	{0xf, 0xf, 0, 0},
444	},
445	{
446	Rd_lvalueRs, 2, NULL,
447	{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
448	{0xf, 0xf, 0, 0}
449	},
450	{
451	Rd_lvalue32Rs, 2, NULL,
452	{OP_SH_REGD, OP_SH_REGS1, 0, 0},
453	{0x1f, 0x1f, 0, 0},
454	},
455	{
456	Rd_rvalue32Rs, 2, NULL,
457	{OP_SH_REGD, OP_SH_REGS1, 0, 0},
458	{0x1f, 0x1f, 0, 0},
459	},
460	{
461	x_Rs, 1, NULL,
462	{OP16_SH_REGS1, 0, 0, 0},
463	{0xf, 0, 0, 0},
464	},
465	{
466	NO_OPD, 0, NULL,
467	{0, 0, 0, 0},
468	{0, 0, 0, 0},
469	},
470	{
471	NO16_OPD, 0, NULL,
472	{0, 0, 0, 0},
473	{0, 0, 0, 0},
474	},
475	};
476
477	struct asm_opcode
478	{
479	/* Instruction name. */
480	const char *template;
481
482	/* Instruction Opcode. */
483	unsigned long value;
484
485	/* Instruction bit mask. */
486	unsigned long bitmask;
487
488	/* Relax instruction opcode. 0x8000 imply no relaxation. */
489	unsigned long relax_value;
490
491	/* Instruction type. */
492	enum score_insn_type type;
493
494	/* Function to call to parse args. */
495	void (parms) (char );
496	};
497
498	enum insn_class
499	{
500	INSN_CLASS_16,
501	INSN_CLASS_32,
502	INSN_CLASS_PCE,
503	INSN_CLASS_SYN
504	};
505
506	#endif