[thirdparty/binutils-gdb.git] / include / opcode / sparc.h

/* Definitions for opcode table for the sparc.
   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002
   Free Software Foundation, Inc.

This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
the GNU Binutils.

GAS/GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GAS/GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GAS or GDB; see the file COPYING.	If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.  */

#include "ansidecl.h"

/* The SPARC opcode table (and other related data) is defined in
   the opcodes library in sparc-opc.c.  If you change anything here, make
   sure you fix up that file, and vice versa.  */

 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
    instruction's name rather than the args.  This would make gas faster, pinsn
    slower, but would mess up some macros a bit.  xoxorich. */

/* List of instruction sets variations.
   These values are such that each element is either a superset of a
   preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
   returns non-zero.
   The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
   Don't change this without updating sparc-opc.c.  */

enum sparc_opcode_arch_val {
  SPARC_OPCODE_ARCH_V6 = 0,
  SPARC_OPCODE_ARCH_V7,
  SPARC_OPCODE_ARCH_V8,
  SPARC_OPCODE_ARCH_SPARCLET,
  SPARC_OPCODE_ARCH_SPARCLITE,
  /* v9 variants must appear last */
  SPARC_OPCODE_ARCH_V9,
  SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */
  SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */
  SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */
};

/* The highest architecture in the table.  */
#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)

/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
   insn encoding/decoding.  */
#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))

/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9.  */
#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)

/* Table of cpu variants.  */

struct sparc_opcode_arch {
  const char *name;
  /* Mask of sparc_opcode_arch_val's supported.
     EG: For v7 this would be
     (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
     These are short's because sparc_opcode.architecture is.  */
  short supported;
};

extern const struct sparc_opcode_arch sparc_opcode_archs[];

/* Given architecture name, look up it's sparc_opcode_arch_val value.  */
extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch
  PARAMS ((const char *));

/* Return the bitmask of supported architectures for ARCH.  */
#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)

/* Non-zero if ARCH1 conflicts with ARCH2.
   IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa.  */
#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
  != SPARC_OPCODE_SUPPORTED (ARCH1)) \
 && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
     != SPARC_OPCODE_SUPPORTED (ARCH2)))

/* Structure of an opcode table entry.  */

struct sparc_opcode {
  const char *name;
  unsigned long match;	/* Bits that must be set. */
  unsigned long lose;	/* Bits that must not be set. */
  const char *args;
  /* This was called "delayed" in versions before the flags. */
  char flags;
  short architecture;	/* Bitmask of sparc_opcode_arch_val's.  */
};

#define	F_DELAYED	1	/* Delayed branch */
#define	F_ALIAS		2	/* Alias for a "real" instruction */
#define	F_UNBR		4	/* Unconditional branch */
#define	F_CONDBR	8	/* Conditional branch */
#define	F_JSR		16	/* Subroutine call */
#define F_FLOAT		32	/* Floating point instruction (not a branch) */
#define F_FBR		64	/* Floating point branch */
/* FIXME: Add F_ANACHRONISTIC flag for v9.  */

/*

All sparc opcodes are 32 bits, except for the `set' instruction (really a
macro), which is 64 bits. It is handled as a special case.

The match component is a mask saying which bits must match a particular
opcode in order for an instruction to be an instance of that opcode.

The args component is a string containing one character for each operand of the
instruction.

Kinds of operands:
	#	Number used by optimizer.	It is ignored.
	1	rs1 register.
	2	rs2 register.
	d	rd register.
	e	frs1 floating point register.
	v	frs1 floating point register (double/even).
	V	frs1 floating point register (quad/multiple of 4).
	f	frs2 floating point register.
	B	frs2 floating point register (double/even).
	R	frs2 floating point register (quad/multiple of 4).
	g	frsd floating point register.
	H	frsd floating point register (double/even).
	J	frsd floating point register (quad/multiple of 4).
	b	crs1 coprocessor register
	c	crs2 coprocessor register
	D	crsd coprocessor register
	m	alternate space register (asr) in rd
	M	alternate space register (asr) in rs1
	h	22 high bits.
	X	5 bit unsigned immediate
	Y	6 bit unsigned immediate
	3	SIAM mode (3 bits). (v9b)
	K	MEMBAR mask (7 bits). (v9)
	j	10 bit Immediate. (v9)
	I	11 bit Immediate. (v9)
	i	13 bit Immediate.
	n	22 bit immediate.
	k	2+14 bit PC relative immediate. (v9)
	G	19 bit PC relative immediate. (v9)
	l	22 bit PC relative immediate.
	L	30 bit PC relative immediate.
	a	Annul.	The annul bit is set.
	A	Alternate address space. Stored as 8 bits.
	C	Coprocessor state register.
	F	floating point state register.
	p	Processor state register.
	N	Branch predict clear ",pn" (v9)
	T	Branch predict set ",pt" (v9)
	z	%icc. (v9)
	Z	%xcc. (v9)
	q	Floating point queue.
	r	Single register that is both rs1 and rd.
	O	Single register that is both rs2 and rd.
	Q	Coprocessor queue.
	S	Special case.
	t	Trap base register.
	w	Window invalid mask register.
	y	Y register.
	u	sparclet coprocessor registers in rd position
	U	sparclet coprocessor registers in rs1 position
	E	%ccr. (v9)
	s	%fprs. (v9)
	P	%pc.  (v9)
	W	%tick.	(v9)
	o	%asi. (v9)
	6	%fcc0. (v9)
	7	%fcc1. (v9)
	8	%fcc2. (v9)
	9	%fcc3. (v9)
	!	Privileged Register in rd (v9)
	?	Privileged Register in rs1 (v9)
	*	Prefetch function constant. (v9)
	x	OPF field (v9 impdep).
	0	32/64 bit immediate for set or setx (v9) insns
	_	Ancillary state register in rd (v9a)
	/	Ancillary state register in rs1 (v9a)

The following chars are unused: (note: ,[] are used as punctuation)
[45]

*/

#define OP2(x)		(((x)&0x7) << 22) /* op2 field of format2 insns */
#define OP3(x)		(((x)&0x3f) << 19) /* op3 field of format3 insns */
#define OP(x)		((unsigned)((x)&0x3) << 30) /* op field of all insns */
#define OPF(x)		(((x)&0x1ff) << 5) /* opf field of float insns */
#define OPF_LOW5(x)	OPF((x)&0x1f) /* v9 */
#define F3F(x, y, z)	(OP(x) | OP3(y) | OPF(z)) /* format3 float insns */
#define F3I(x)		(((x)&0x1) << 13) /* immediate field of format 3 insns */
#define F2(x, y)	(OP(x) | OP2(y)) /* format 2 insns */
#define F3(x, y, z)	(OP(x) | OP3(y) | F3I(z)) /* format3 insns */
#define F1(x)		(OP(x))
#define DISP30(x)	((x)&0x3fffffff)
#define ASI(x)		(((x)&0xff) << 5) /* asi field of format3 insns */
#define RS2(x)		((x)&0x1f) /* rs2 field */
#define SIMM13(x)	((x)&0x1fff) /* simm13 field */
#define RD(x)		(((x)&0x1f) << 25) /* destination register field */
#define RS1(x)		(((x)&0x1f) << 14) /* rs1 field */
#define ASI_RS2(x)	(SIMM13(x))
#define MEMBAR(x)	((x)&0x7f)
#define SLCPOP(x)	(((x)&0x7f) << 6) /* sparclet cpop */

#define ANNUL	(1<<29)
#define BPRED	(1<<19)	/* v9 */
#define	IMMED	F3I(1)
#define RD_G0	RD(~0)
#define	RS1_G0	RS1(~0)
#define	RS2_G0	RS2(~0)

extern const struct sparc_opcode sparc_opcodes[];
extern const int sparc_num_opcodes;

extern int sparc_encode_asi PARAMS ((const char *));
extern const char *sparc_decode_asi PARAMS ((int));
extern int sparc_encode_membar PARAMS ((const char *));
extern const char *sparc_decode_membar PARAMS ((int));
extern int sparc_encode_prefetch PARAMS ((const char *));
extern const char *sparc_decode_prefetch PARAMS ((int));
extern int sparc_encode_sparclet_cpreg PARAMS ((const char *));
extern const char *sparc_decode_sparclet_cpreg PARAMS ((int));

/*
 * Local Variables:
 * fill-column: 131
 * comment-column: 0
 * End:
 */

/* end of sparc.h */
Commit	Line	Data
252b5132	1	/* Definitions for opcode table for the sparc.
b3f7d5fd	2	Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002
252b5132 RH	3	Free Software Foundation, Inc.
	4
	5	This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
	6	the GNU Binutils.
	7
	8	GAS/GDB is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2, or (at your option)
	11	any later version.
	12
	13	GAS/GDB is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with GAS or GDB; see the file COPYING. If not, write to
	20	the Free Software Foundation, 59 Temple Place - Suite 330,
	21	Boston, MA 02111-1307, USA. */
	22
b3f7d5fd	23	#include "ansidecl.h"
252b5132 RH	24
	25	/* The SPARC opcode table (and other related data) is defined in
	26	the opcodes library in sparc-opc.c. If you change anything here, make
	27	sure you fix up that file, and vice versa. */
	28
	29	/* FIXME-someday: perhaps the ,a's and such should be embedded in the
	30	instruction's name rather than the args. This would make gas faster, pinsn
	31	slower, but would mess up some macros a bit. xoxorich. */
	32
	33	/* List of instruction sets variations.
	34	These values are such that each element is either a superset of a
	35	preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
	36	returns non-zero.
	37	The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
	38	Don't change this without updating sparc-opc.c. */
	39
	40	enum sparc_opcode_arch_val {
	41	SPARC_OPCODE_ARCH_V6 = 0,
	42	SPARC_OPCODE_ARCH_V7,
	43	SPARC_OPCODE_ARCH_V8,
	44	SPARC_OPCODE_ARCH_SPARCLET,
	45	SPARC_OPCODE_ARCH_SPARCLITE,
	46	/* v9 variants must appear last */
	47	SPARC_OPCODE_ARCH_V9,
	48	SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */
19f7b010	49	SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */
252b5132 RH	50	SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */
	51	};
	52
	53	/* The highest architecture in the table. */
	54	#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
	55
	56	/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
	57	insn encoding/decoding. */
	58	#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
	59
	60	/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
	61	#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
	62
	63	/* Table of cpu variants. */
	64
	65	struct sparc_opcode_arch {
	66	const char *name;
	67	/* Mask of sparc_opcode_arch_val's supported.
	68	EG: For v7 this would be
	69	(SPARC_OPCODE_ARCH_MASK (..._V6) \| SPARC_OPCODE_ARCH_MASK (..._V7)).
	70	These are short's because sparc_opcode.architecture is. */
	71	short supported;
	72	};
	73
	74	extern const struct sparc_opcode_arch sparc_opcode_archs[];
	75
	76	/* Given architecture name, look up it's sparc_opcode_arch_val value. */
	77	extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch
	78	PARAMS ((const char *));
	79
	80	/* Return the bitmask of supported architectures for ARCH. */
	81	#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
	82
	83	/* Non-zero if ARCH1 conflicts with ARCH2.
	84	IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
	85	#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
	86	(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
	87	!= SPARC_OPCODE_SUPPORTED (ARCH1)) \
	88	&& ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
	89	!= SPARC_OPCODE_SUPPORTED (ARCH2)))
	90
	91	/* Structure of an opcode table entry. */
	92
	93	struct sparc_opcode {
	94	const char *name;
	95	unsigned long match; /* Bits that must be set. */
	96	unsigned long lose; /* Bits that must not be set. */
	97	const char *args;
	98	/* This was called "delayed" in versions before the flags. */
	99	char flags;
	100	short architecture; /* Bitmask of sparc_opcode_arch_val's. */
	101	};
	102
	103	#define F_DELAYED 1 /* Delayed branch */
	104	#define F_ALIAS 2 /* Alias for a "real" instruction */
	105	#define F_UNBR 4 /* Unconditional branch */
	106	#define F_CONDBR 8 /* Conditional branch */
	107	#define F_JSR 16 /* Subroutine call */
	108	#define F_FLOAT 32 /* Floating point instruction (not a branch) */
	109	#define F_FBR 64 /* Floating point branch */
	110	/* FIXME: Add F_ANACHRONISTIC flag for v9. */
	111
	112	/*
	113
114	All sparc opcodes are 32 bits, except for the `set' instruction (really a
115	macro), which is 64 bits. It is handled as a special case.
116
117	The match component is a mask saying which bits must match a particular
118	opcode in order for an instruction to be an instance of that opcode.
119
120	The args component is a string containing one character for each operand of the
121	instruction.
122
123	Kinds of operands:
124	# Number used by optimizer. It is ignored.
125	1 rs1 register.
126	2 rs2 register.
127	d rd register.
128	e frs1 floating point register.
129	v frs1 floating point register (double/even).
130	V frs1 floating point register (quad/multiple of 4).
131	f frs2 floating point register.
132	B frs2 floating point register (double/even).
133	R frs2 floating point register (quad/multiple of 4).
134	g frsd floating point register.
135	H frsd floating point register (double/even).
136	J frsd floating point register (quad/multiple of 4).
137	b crs1 coprocessor register
138	c crs2 coprocessor register
139	D crsd coprocessor register
140	m alternate space register (asr) in rd
141	M alternate space register (asr) in rs1
142	h 22 high bits.
143	X 5 bit unsigned immediate
144	Y 6 bit unsigned immediate
19f7b010	145	3 SIAM mode (3 bits). (v9b)
252b5132 RH	146	K MEMBAR mask (7 bits). (v9)
	147	j 10 bit Immediate. (v9)
	148	I 11 bit Immediate. (v9)
	149	i 13 bit Immediate.
	150	n 22 bit immediate.
	151	k 2+14 bit PC relative immediate. (v9)
	152	G 19 bit PC relative immediate. (v9)
	153	l 22 bit PC relative immediate.
	154	L 30 bit PC relative immediate.
	155	a Annul. The annul bit is set.
	156	A Alternate address space. Stored as 8 bits.
	157	C Coprocessor state register.
	158	F floating point state register.
	159	p Processor state register.
	160	N Branch predict clear ",pn" (v9)
	161	T Branch predict set ",pt" (v9)
	162	z %icc. (v9)
	163	Z %xcc. (v9)
	164	q Floating point queue.
	165	r Single register that is both rs1 and rd.
	166	O Single register that is both rs2 and rd.
	167	Q Coprocessor queue.
	168	S Special case.
	169	t Trap base register.
	170	w Window invalid mask register.
	171	y Y register.
	172	u sparclet coprocessor registers in rd position
	173	U sparclet coprocessor registers in rs1 position
	174	E %ccr. (v9)
	175	s %fprs. (v9)
	176	P %pc. (v9)
	177	W %tick. (v9)
	178	o %asi. (v9)
	179	6 %fcc0. (v9)
	180	7 %fcc1. (v9)
	181	8 %fcc2. (v9)
	182	9 %fcc3. (v9)
	183	! Privileged Register in rd (v9)
	184	? Privileged Register in rs1 (v9)
	185	* Prefetch function constant. (v9)
	186	x OPF field (v9 impdep).
	187	0 32/64 bit immediate for set or setx (v9) insns
	188	_ Ancillary state register in rd (v9a)
	189	/ Ancillary state register in rs1 (v9a)
	190
	191	The following chars are unused: (note: ,[] are used as punctuation)
19f7b010	192	[45]
252b5132 RH	193
	194	*/
	195
	196	#define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */
	197	#define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */
	198	#define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */
	199	#define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */
	200	#define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */
	201	#define F3F(x, y, z) (OP(x) \| OP3(y) \| OPF(z)) /* format3 float insns */
	202	#define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */
	203	#define F2(x, y) (OP(x) \| OP2(y)) /* format 2 insns */
	204	#define F3(x, y, z) (OP(x) \| OP3(y) \| F3I(z)) /* format3 insns */
	205	#define F1(x) (OP(x))
	206	#define DISP30(x) ((x)&0x3fffffff)
	207	#define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */
	208	#define RS2(x) ((x)&0x1f) /* rs2 field */
	209	#define SIMM13(x) ((x)&0x1fff) /* simm13 field */
	210	#define RD(x) (((x)&0x1f) << 25) /* destination register field */
	211	#define RS1(x) (((x)&0x1f) << 14) /* rs1 field */
	212	#define ASI_RS2(x) (SIMM13(x))
	213	#define MEMBAR(x) ((x)&0x7f)
	214	#define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */
	215
	216	#define ANNUL (1<<29)
	217	#define BPRED (1<<19) /* v9 */
	218	#define IMMED F3I(1)
	219	#define RD_G0 RD(~0)
	220	#define RS1_G0 RS1(~0)
	221	#define RS2_G0 RS2(~0)
	222
	223	extern const struct sparc_opcode sparc_opcodes[];
	224	extern const int sparc_num_opcodes;
	225
	226	extern int sparc_encode_asi PARAMS ((const char *));
	227	extern const char *sparc_decode_asi PARAMS ((int));
	228	extern int sparc_encode_membar PARAMS ((const char *));
	229	extern const char *sparc_decode_membar PARAMS ((int));
	230	extern int sparc_encode_prefetch PARAMS ((const char *));
	231	extern const char *sparc_decode_prefetch PARAMS ((int));
	232	extern int sparc_encode_sparclet_cpreg PARAMS ((const char *));
	233	extern const char *sparc_decode_sparclet_cpreg PARAMS ((int));
	234
	235	/*
	236	* Local Variables:
	237	* fill-column: 131
	238	* comment-column: 0
	239	* End:
	240	*/
	241
	242	/* end of sparc.h */