[thirdparty/binutils-gdb.git] / include / opcode / v850.h

/* v850.h -- Header file for NEC V850 opcode table
   Copyright 1996, 1997, 2001, 2003, 2010 Free Software Foundation, Inc.
   Written by J.T. Conklin, Cygnus Support

   This file is part of GDB, GAS, and the GNU binutils.

   GDB, GAS, and the GNU binutils are free software; you can redistribute
   them and/or modify them under the terms of the GNU General Public
   License as published by the Free Software Foundation; either version 3,
   or (at your option) any later version.

   GDB, GAS, and the GNU binutils are distributed in the hope that they
   will be useful, but WITHOUT ANY WARRANTY; without even the implied
   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
   the GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this file; see the file COPYING3.  If not, write to the Free
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#ifndef V850_H
#define V850_H

/* The opcode table is an array of struct v850_opcode.  */

struct v850_opcode
{
  /* The opcode name.  */
  const char *name;

  /* The opcode itself.  Those bits which will be filled in with
     operands are zeroes.  */
  unsigned long opcode;

  /* The opcode mask.  This is used by the disassembler.  This is a
     mask containing ones indicating those bits which must match the
     opcode field, and zeroes indicating those bits which need not
     match (and are presumably filled in by operands).  */
  unsigned long mask;

  /* An array of operand codes.  Each code is an index into the
     operand table.  They appear in the order which the operands must
     appear in assembly code, and are terminated by a zero.  */
  unsigned char operands[8];

  /* Which (if any) operand is a memory operand.  */
  unsigned int memop;

  /* Target processor(s).  A bit field of processors which support
     this instruction.  Note a bit field is used as some instructions
     are available on multiple, different processor types, whereas
     other instructions are only available on one specific type.  */
  unsigned int processors;
};

/* Values for the processors field in the v850_opcode structure.  */
#define PROCESSOR_V850		(1 << 0)		/* Just the V850.  */
#define PROCESSOR_ALL		-1			/* Any processor.  */
#define PROCESSOR_V850E		(1 << 1)		/* Just the V850E. */
#define PROCESSOR_NOT_V850	(~ PROCESSOR_V850)	/* Any processor except the V850.  */
#define PROCESSOR_V850EA	(1 << 2)		/* Just the V850EA. */
#define PROCESSOR_V850E1	(1 << 3)		/* Just the V850E1. */

/* The table itself is sorted by major opcode number, and is otherwise
   in the order in which the disassembler should consider
   instructions.  */
extern const struct v850_opcode v850_opcodes[];
extern const int v850_num_opcodes;

\f
/* The operands table is an array of struct v850_operand.  */

struct v850_operand
{
  /* The number of bits in the operand.  */
  /* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */
  int bits;

  /* (bits >= 0):  How far the operand is left shifted in the instruction.  */
  /* (bits == -1): Bit mask of the bits in the operand.  */
  int shift;

  /* Insertion function.  This is used by the assembler.  To insert an
     operand value into an instruction, check this field.

     If it is NULL, execute
         i |= (op & ((1 << o->bits) - 1)) << o->shift;
     (i is the instruction which we are filling in, o is a pointer to
     this structure, and op is the opcode value; this assumes twos
     complement arithmetic).

     If this field is not NULL, then simply call it with the
     instruction and the operand value.  It will return the new value
     of the instruction.  If the ERRMSG argument is not NULL, then if
     the operand value is illegal, *ERRMSG will be set to a warning
     string (the operand will be inserted in any case).  If the
     operand value is legal, *ERRMSG will be unchanged (most operands
     can accept any value).  */
  unsigned long (* insert)
    (unsigned long instruction, long op, const char ** errmsg);

  /* Extraction function.  This is used by the disassembler.  To
     extract this operand type from an instruction, check this field.

     If it is NULL, compute
         op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1);
	 if (o->flags & V850_OPERAND_SIGNED)
	     op = (op << (32 - o->bits)) >> (32 - o->bits);
     (i is the instruction, o is a pointer to this structure, and op
     is the result; this assumes twos complement arithmetic).

     If this field is not NULL, then simply call it with the
     instruction value.  It will return the value of the operand.  If
     the INVALID argument is not NULL, *INVALID will be set to
     non-zero if this operand type can not actually be extracted from
     this operand (i.e., the instruction does not match).  If the
     operand is valid, *INVALID will not be changed.  */
  unsigned long (* extract) (unsigned long instruction, int * invalid);

  /* One bit syntax flags.  */
  int flags;
};

/* Elements in the table are retrieved by indexing with values from
   the operands field of the v850_opcodes table.  */

extern const struct v850_operand v850_operands[];

/* Values defined for the flags field of a struct v850_operand.  */

/* This operand names a general purpose register */
#define V850_OPERAND_REG	0x01

/* This operand names a system register */
#define V850_OPERAND_SRG	0x02

/* This operand names a condition code used in the setf instruction */
#define V850_OPERAND_CC		0x04

/* This operand takes signed values */
#define V850_OPERAND_SIGNED	0x08

/* This operand is the ep register.  */
#define V850_OPERAND_EP		0x10

/* This operand is a PC displacement */
#define V850_OPERAND_DISP	0x20

/* This is a relaxable operand.   Only used for D9->D22 branch relaxing
   right now.  We may need others in the future (or maybe handle them like
   promoted operands on the mn10300?)  */
#define V850_OPERAND_RELAX	0x40

/* The register specified must not be r0 */
#define V850_NOT_R0	        0x80

/* push/pop type instruction, V850E specific.  */
#define V850E_PUSH_POP		0x100

/* 16 bit immediate follows instruction, V850E specific.  */
#define V850E_IMMEDIATE16	0x200

/* 32 bit immediate follows instruction, V850E specific.  */
#define V850E_IMMEDIATE32	0x400

#endif /* V850_H */
Commit	Line	Data
252b5132	1	/* v850.h -- Header file for NEC V850 opcode table
e4e42b45	2	Copyright 1996, 1997, 2001, 2003, 2010 Free Software Foundation, Inc.
252b5132 RH	3	Written by J.T. Conklin, Cygnus Support
252b5132 RH	4
e4e42b45	5	This file is part of GDB, GAS, and the GNU binutils.
252b5132	6
e4e42b45 NC	7	GDB, GAS, and the GNU binutils are free software; you can redistribute
	8	them and/or modify them under the terms of the GNU General Public
	9	License as published by the Free Software Foundation; either version 3,
	10	or (at your option) any later version.
252b5132	11
e4e42b45 NC	12	GDB, GAS, and the GNU binutils are distributed in the hope that they
	13	will be useful, but WITHOUT ANY WARRANTY; without even the implied
	14	warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
	15	the GNU General Public License for more details.
252b5132	16
e4e42b45 NC	17	You should have received a copy of the GNU General Public License
	18	along with this file; see the file COPYING3. If not, write to the Free
	19	Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
	20	MA 02110-1301, USA. */
252b5132 RH	21
	22	#ifndef V850_H
	23	#define V850_H
	24
	25	/* The opcode table is an array of struct v850_opcode. */
	26
	27	struct v850_opcode
	28	{
	29	/* The opcode name. */
	30	const char *name;
	31
	32	/* The opcode itself. Those bits which will be filled in with
	33	operands are zeroes. */
	34	unsigned long opcode;
	35
	36	/* The opcode mask. This is used by the disassembler. This is a
	37	mask containing ones indicating those bits which must match the
	38	opcode field, and zeroes indicating those bits which need not
	39	match (and are presumably filled in by operands). */
	40	unsigned long mask;
	41
	42	/* An array of operand codes. Each code is an index into the
	43	operand table. They appear in the order which the operands must
	44	appear in assembly code, and are terminated by a zero. */
	45	unsigned char operands[8];
	46
	47	/* Which (if any) operand is a memory operand. */
	48	unsigned int memop;
	49
	50	/* Target processor(s). A bit field of processors which support
	51	this instruction. Note a bit field is used as some instructions
	52	are available on multiple, different processor types, whereas
	53	other instructions are only available on one specific type. */
	54	unsigned int processors;
	55	};
	56
	57	/* Values for the processors field in the v850_opcode structure. */
	58	#define PROCESSOR_V850 (1 << 0) /* Just the V850. */
	59	#define PROCESSOR_ALL -1 /* Any processor. */
	60	#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */
	61	#define PROCESSOR_NOT_V850 (~ PROCESSOR_V850) /* Any processor except the V850. */
	62	#define PROCESSOR_V850EA (1 << 2) /* Just the V850EA. */
8ad30312	63	#define PROCESSOR_V850E1 (1 << 3) /* Just the V850E1. */
252b5132 RH	64
	65	/* The table itself is sorted by major opcode number, and is otherwise
	66	in the order in which the disassembler should consider
	67	instructions. */
	68	extern const struct v850_opcode v850_opcodes[];
	69	extern const int v850_num_opcodes;
	70
	71	\f
	72	/* The operands table is an array of struct v850_operand. */
	73
	74	struct v850_operand
	75	{
	76	/* The number of bits in the operand. */
	77	/* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */
	78	int bits;
	79
	80	/* (bits >= 0): How far the operand is left shifted in the instruction. */
	81	/* (bits == -1): Bit mask of the bits in the operand. */
	82	int shift;
	83
	84	/* Insertion function. This is used by the assembler. To insert an
	85	operand value into an instruction, check this field.
	86
	87	If it is NULL, execute
	88	i \|= (op & ((1 << o->bits) - 1)) << o->shift;
	89	(i is the instruction which we are filling in, o is a pointer to
	90	this structure, and op is the opcode value; this assumes twos
	91	complement arithmetic).
	92
	93	If this field is not NULL, then simply call it with the
	94	instruction and the operand value. It will return the new value
	95	of the instruction. If the ERRMSG argument is not NULL, then if
	96	the operand value is illegal, *ERRMSG will be set to a warning
	97	string (the operand will be inserted in any case). If the
	98	operand value is legal, *ERRMSG will be unchanged (most operands
	99	can accept any value). */
8cf3f354 AM	100	unsigned long (* insert)
8cf3f354 AM	101	(unsigned long instruction, long op, const char ** errmsg);
252b5132 RH	102
	103	/* Extraction function. This is used by the disassembler. To
	104	extract this operand type from an instruction, check this field.
	105
	106	If it is NULL, compute
	107	op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1);
	108	if (o->flags & V850_OPERAND_SIGNED)
	109	op = (op << (32 - o->bits)) >> (32 - o->bits);
	110	(i is the instruction, o is a pointer to this structure, and op
	111	is the result; this assumes twos complement arithmetic).
	112
	113	If this field is not NULL, then simply call it with the
	114	instruction value. It will return the value of the operand. If
	115	the INVALID argument is not NULL, *INVALID will be set to
	116	non-zero if this operand type can not actually be extracted from
	117	this operand (i.e., the instruction does not match). If the
	118	operand is valid, INVALID will not be changed. /
8cf3f354	119	unsigned long (* extract) (unsigned long instruction, int * invalid);
252b5132 RH	120
	121	/* One bit syntax flags. */
	122	int flags;
	123	};
	124
	125	/* Elements in the table are retrieved by indexing with values from
	126	the operands field of the v850_opcodes table. */
	127
	128	extern const struct v850_operand v850_operands[];
	129
	130	/* Values defined for the flags field of a struct v850_operand. */
	131
	132	/* This operand names a general purpose register */
	133	#define V850_OPERAND_REG 0x01
	134
	135	/* This operand names a system register */
	136	#define V850_OPERAND_SRG 0x02
	137
	138	/* This operand names a condition code used in the setf instruction */
	139	#define V850_OPERAND_CC 0x04
	140
	141	/* This operand takes signed values */
	142	#define V850_OPERAND_SIGNED 0x08
	143
	144	/* This operand is the ep register. */
	145	#define V850_OPERAND_EP 0x10
	146
	147	/* This operand is a PC displacement */
	148	#define V850_OPERAND_DISP 0x20
	149
	150	/* This is a relaxable operand. Only used for D9->D22 branch relaxing
	151	right now. We may need others in the future (or maybe handle them like
	152	promoted operands on the mn10300?) */
	153	#define V850_OPERAND_RELAX 0x40
	154
	155	/* The register specified must not be r0 */
	156	#define V850_NOT_R0 0x80
	157
252b5132 RH	158	/* push/pop type instruction, V850E specific. */
	159	#define V850E_PUSH_POP 0x100
	160
	161	/* 16 bit immediate follows instruction, V850E specific. */
	162	#define V850E_IMMEDIATE16 0x200
	163
	164	/* 32 bit immediate follows instruction, V850E specific. */
	165	#define V850E_IMMEDIATE32 0x400
	166
	167	#endif /* V850_H */