[people/ms/u-boot.git] / include / spartan3.h

/*
 * (C) Copyright 2002
 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#ifndef _SPARTAN3_H_
#define _SPARTAN3_H_

#include <xilinx.h>

extern int Spartan3_load(Xilinx_desc *desc, const void *image, size_t size);
extern int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
extern int Spartan3_info(Xilinx_desc *desc);

/* Slave Parallel Implementation function table */
typedef struct {
	Xilinx_pre_fn	pre;
	Xilinx_pgm_fn	pgm;
	Xilinx_init_fn	init;
	Xilinx_err_fn	err;
	Xilinx_done_fn	done;
	Xilinx_clk_fn	clk;
	Xilinx_cs_fn	cs;
	Xilinx_wr_fn	wr;
	Xilinx_rdata_fn	rdata;
	Xilinx_wdata_fn	wdata;
	Xilinx_busy_fn	busy;
	Xilinx_abort_fn	abort;
	Xilinx_post_fn	post;
} Xilinx_Spartan3_Slave_Parallel_fns;

/* Slave Serial Implementation function table */
typedef struct {
	Xilinx_pre_fn	pre;
	Xilinx_pgm_fn	pgm;
	Xilinx_clk_fn	clk;
	Xilinx_init_fn	init;
	Xilinx_done_fn	done;
	Xilinx_wr_fn	wr;
	Xilinx_post_fn	post;
	Xilinx_bwr_fn	bwr; /* block write function */
	Xilinx_abort_fn abort;
} Xilinx_Spartan3_Slave_Serial_fns;

/* Device Image Sizes
 *********************************************************************/
/* Spartan-III (1.2V) */
#define XILINX_XC3S50_SIZE	439264/8
#define XILINX_XC3S200_SIZE	1047616/8
#define XILINX_XC3S400_SIZE	1699136/8
#define XILINX_XC3S1000_SIZE	3223488/8
#define XILINX_XC3S1500_SIZE	5214784/8
#define XILINX_XC3S2000_SIZE	7673024/8
#define XILINX_XC3S4000_SIZE	11316864/8
#define XILINX_XC3S5000_SIZE	13271936/8

/* Spartan-3E (v3.4) */
#define	XILINX_XC3S100E_SIZE	581344/8
#define	XILINX_XC3S250E_SIZE	1353728/8
#define	XILINX_XC3S500E_SIZE	2270208/8
#define	XILINX_XC3S1200E_SIZE	3841184/8
#define	XILINX_XC3S1600E_SIZE	5969696/8

/*
 * Spartan-6 : the Spartan-6 family can be programmed
 * exactly as the Spartan-3
 */
#define XILINK_XC6SLX4_SIZE	(3713568/8)

/* Descriptor Macros
 *********************************************************************/
/* Spartan-III devices */
#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie }

#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie }

#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie }

#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie }

#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie }

#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie }

#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie }

#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie }

/* Spartan-3E devices */
#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie }

#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie }

#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie }

#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie }

#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie }

#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie }

#endif /* _SPARTAN3_H_ */
Commit	Line	Data
875c7893 WD	1	/*
	2	* (C) Copyright 2002
	3	* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*
	23	*/
	24
	25	#ifndef _SPARTAN3_H_
	26	#define _SPARTAN3_H_
	27
	28	#include <xilinx.h>
	29
e6a857da WD	30	extern int Spartan3_load(Xilinx_desc desc, const void image, size_t size);
	31	extern int Spartan3_dump(Xilinx_desc desc, const void buf, size_t bsize);
	32	extern int Spartan3_info(Xilinx_desc *desc);
875c7893 WD	33
	34	/* Slave Parallel Implementation function table */
	35	typedef struct {
	36	Xilinx_pre_fn pre;
	37	Xilinx_pgm_fn pgm;
	38	Xilinx_init_fn init;
	39	Xilinx_err_fn err;
	40	Xilinx_done_fn done;
	41	Xilinx_clk_fn clk;
	42	Xilinx_cs_fn cs;
	43	Xilinx_wr_fn wr;
	44	Xilinx_rdata_fn rdata;
	45	Xilinx_wdata_fn wdata;
	46	Xilinx_busy_fn busy;
	47	Xilinx_abort_fn abort;
	48	Xilinx_post_fn post;
875c7893 WD	49	} Xilinx_Spartan3_Slave_Parallel_fns;
	50
	51	/* Slave Serial Implementation function table */
	52	typedef struct {
	53	Xilinx_pre_fn pre;
	54	Xilinx_pgm_fn pgm;
	55	Xilinx_clk_fn clk;
	56	Xilinx_init_fn init;
	57	Xilinx_done_fn done;
	58	Xilinx_wr_fn wr;
21d39d59	59	Xilinx_post_fn post;
89083346	60	Xilinx_bwr_fn bwr; /* block write function */
b0bc8b70	61	Xilinx_abort_fn abort;
875c7893 WD	62	} Xilinx_Spartan3_Slave_Serial_fns;
	63
	64	/* Device Image Sizes
	65	*********************************************************************/
	66	/* Spartan-III (1.2V) */
53677ef1 WD	67	#define XILINX_XC3S50_SIZE 439264/8
	68	#define XILINX_XC3S200_SIZE 1047616/8
	69	#define XILINX_XC3S400_SIZE 1699136/8
	70	#define XILINX_XC3S1000_SIZE 3223488/8
	71	#define XILINX_XC3S1500_SIZE 5214784/8
	72	#define XILINX_XC3S2000_SIZE 7673024/8
	73	#define XILINX_XC3S4000_SIZE 11316864/8
	74	#define XILINX_XC3S5000_SIZE 13271936/8
875c7893	75
923efd28 BA	76	/* Spartan-3E (v3.4) */
	77	#define XILINX_XC3S100E_SIZE 581344/8
	78	#define XILINX_XC3S250E_SIZE 1353728/8
	79	#define XILINX_XC3S500E_SIZE 2270208/8
	80	#define XILINX_XC3S1200E_SIZE 3841184/8
	81	#define XILINX_XC3S1600E_SIZE 5969696/8
	82
28cdc1c8 SB	83	/*
	84	* Spartan-6 : the Spartan-6 family can be programmed
	85	* exactly as the Spartan-3
	86	*/
	87	#define XILINK_XC6SLX4_SIZE (3713568/8)
	88
875c7893 WD	89	/* Descriptor Macros
875c7893 WD	90	*********************************************************************/
3bff4ffa	91	/* Spartan-III devices */
875c7893 WD	92	#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
	93	{ Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie }
	94
	95	#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
	96	{ Xilinx_Spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie }
	97
	98	#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
	99	{ Xilinx_Spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie }
	100
	101	#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
	102	{ Xilinx_Spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie }
	103
	104	#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
	105	{ Xilinx_Spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie }
	106
	107	#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
a07faf7b	108	{ Xilinx_Spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie }
875c7893 WD	109
875c7893 WD	110	#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
a07faf7b	111	{ Xilinx_Spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie }
875c7893 WD	112
875c7893 WD	113	#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
a07faf7b	114	{ Xilinx_Spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie }
875c7893	115
923efd28 BA	116	/* Spartan-3E devices */
	117	#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
	118	{ Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie }
	119
	120	#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
	121	{ Xilinx_Spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie }
	122
	123	#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
	124	{ Xilinx_Spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie }
	125
	126	#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
	127	{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie }
	128
	129	#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
	130	{ Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie }
	131
28cdc1c8 SB	132	#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
	133	{ Xilinx_Spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie }
	134
875c7893	135	#endif /* _SPARTAN3_H_ */