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1/*
2 * (C) Copyright 2012-2013, Xilinx, Michal Simek
3 *
4 * (C) Copyright 2012
5 * Joe Hershberger <joe.hershberger@ni.com>
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
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8 */
9
10#ifndef _ZYNQPL_H_
11#define _ZYNQPL_H_
12
13#include <xilinx.h>
14
345f9e19 15#if defined(CONFIG_FPGA_ZYNQPL)
14cfc4f3 16extern struct xilinx_fpga_op zynq_op;
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17# define FPGA_ZYNQPL_OPS &zynq_op
18#else
19# define FPGA_ZYNQPL_OPS NULL
20#endif
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21
22#define XILINX_ZYNQ_7010 0x2
31993d6a 23#define XILINX_ZYNQ_7015 0x1b
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24#define XILINX_ZYNQ_7020 0x7
25#define XILINX_ZYNQ_7030 0xc
26#define XILINX_ZYNQ_7045 0x11
fd2b10b6 27#define XILINX_ZYNQ_7100 0x16
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28
29/* Device Image Sizes */
30#define XILINX_XC7Z010_SIZE 16669920/8
31993d6a 31#define XILINX_XC7Z015_SIZE 28085344/8
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32#define XILINX_XC7Z020_SIZE 32364512/8
33#define XILINX_XC7Z030_SIZE 47839328/8
34#define XILINX_XC7Z045_SIZE 106571232/8
fd2b10b6 35#define XILINX_XC7Z100_SIZE 139330784/8
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36
37/* Descriptor Macros */
38#define XILINX_XC7Z010_DESC(cookie) \
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39{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
40 "7z010" }
d5dae85f 41
31993d6a 42#define XILINX_XC7Z015_DESC(cookie) \
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43{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
44 "7z015" }
31993d6a 45
d5dae85f 46#define XILINX_XC7Z020_DESC(cookie) \
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47{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
48 "7z020" }
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49
50#define XILINX_XC7Z030_DESC(cookie) \
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51{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
52 "7z030" }
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53
54#define XILINX_XC7Z045_DESC(cookie) \
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55{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
56 "7z045" }
d5dae85f 57
fd2b10b6 58#define XILINX_XC7Z100_DESC(cookie) \
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59{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
60 "7z100" }
fd2b10b6 61
d5dae85f 62#endif /* _ZYNQPL_H_ */