[thirdparty/binutils-gdb.git] / ld / testsuite / ld-spu / ovl2.d

#source: ovl2.s
#ld: -N -T ovl2.lnk -T ovl.lnk --emit-relocs
#objdump: -D -r

.*elf32-spu

Disassembly of section \.text:

00000100 <_start>:
 100:	33 00 06 00 	brsl	\$0,130 <00000000\.ovl_call\.f1_a1>	# 130
			100: SPU_REL16	f1_a1
 104:	33 00 03 80 	brsl	\$0,120 <00000000\.ovl_call\.10:4>	# 120
			104: SPU_REL16	setjmp
 108:	32 7f ff 00 	br	100 <_start>	# 100
			108: SPU_REL16	_start

0000010c <setjmp>:
 10c:	35 00 00 00 	bi	\$0

00000110 <longjmp>:
 110:	35 00 00 00 	bi	\$0
	...

00000120 <00000000\.ovl_call.10:4>:
 120:	42 00 86 4f 	ila	\$79,268	# 10c
 124:	40 20 00 00 	nop	\$0
 128:	42 00 00 4e 	ila	\$78,0
 12c:	32 00 0a 80 	br	180 <__ovly_load>	# 180
			12c: SPU_REL16	__ovly_load

00000130 <00000000\.ovl_call.f1_a1>:
 130:	42 02 00 4f 	ila	\$79,1024	# 400
 134:	40 20 00 00 	nop	\$0
 138:	42 00 00 ce 	ila	\$78,1
 13c:	32 00 08 80 	br	180 <__ovly_load>	# 180
			13c: SPU_REL16	__ovly_load

00000140 <_SPUEAR_f1_a2>:
 140:	42 02 00 4f 	ila	\$79,1024	# 400
 144:	40 20 00 00 	nop	\$0
 148:	42 00 01 4e 	ila	\$78,2
 14c:	32 00 06 80 	br	180 <__ovly_load>	# 180
			14c: SPU_REL16	__ovly_load
#...
Disassembly of section \.ov_a1:

00000400 <f1_a1>:
 400:	35 00 00 00 	bi	\$0
	\.\.\.
Disassembly of section \.ov_a2:

00000400 <f1_a2>:
 400:	32 7f a2 00 	br	110 <longjmp>	# 110
			400: SPU_REL16	longjmp
	\.\.\.
Disassembly of section \.data:

00000410 <_ovly_table>:
 410:	00 00 04 00 	.*
 414:	00 00 00 10 	.*
 418:	00 00 02 d0 	.*
 41c:	00 00 00 01 	.*
 420:	00 00 04 00 	.*
 424:	00 00 00 10 	.*
 428:	00 00 02 e0 	.*
 42c:	00 00 00 01 	.*

00000430 <_ovly_buf_table>:
 430:	00 00 00 00 	.*
Disassembly of section \.toe:

00000440 <_EAR_>:
	\.\.\.
Disassembly of section \.note\.spu_name:

.* <\.note\.spu_name>:
.*:	00 00 00 08 .*
.*:	00 00 00 0c .*
.*:	00 00 00 01 .*
.*:	53 50 55 4e .*
.*:	41 4d 45 00 .*
.*:	74 6d 70 64 .*
.*:	69 72 2f 64 .*
.*:	75 6d 70 00 .*
Commit	Line	Data
0fd7d342	1	#source: ovl2.s
53d25da6	2	#ld: -N -T ovl2.lnk -T ovl.lnk --emit-relocs
0fd7d342 AM	3	#objdump: -D -r
	4
	5	.*elf32-spu
	6
	7	Disassembly of section \.text:
	8
	9	00000100 <_start>:
	10	100: 33 00 06 00 brsl \$0,130 <00000000\.ovl_call\.f1_a1> # 130
	11	100: SPU_REL16 f1_a1
	12	104: 33 00 03 80 brsl \$0,120 <00000000\.ovl_call\.10:4> # 120
	13	104: SPU_REL16 setjmp
	14	108: 32 7f ff 00 br 100 <_start> # 100
	15	108: SPU_REL16 _start
	16
	17	0000010c <setjmp>:
	18	10c: 35 00 00 00 bi \$0
	19
	20	00000110 <longjmp>:
	21	110: 35 00 00 00 bi \$0
	22	...
	23
	24	00000120 <00000000\.ovl_call.10:4>:
	25	120: 42 00 86 4f ila \$79,268 # 10c
	26	124: 40 20 00 00 nop \$0
	27	128: 42 00 00 4e ila \$78,0
	28	12c: 32 00 0a 80 br 180 <__ovly_load> # 180
2cb5950e	29	12c: SPU_REL16 __ovly_load
0fd7d342 AM	30
	31	00000130 <00000000\.ovl_call.f1_a1>:
	32	130: 42 02 00 4f ila \$79,1024 # 400
	33	134: 40 20 00 00 nop \$0
	34	138: 42 00 00 ce ila \$78,1
	35	13c: 32 00 08 80 br 180 <__ovly_load> # 180
2cb5950e	36	13c: SPU_REL16 __ovly_load
0fd7d342	37
c1b2796f	38	00000140 <_SPUEAR_f1_a2>:
0fd7d342 AM	39	140: 42 02 00 4f ila \$79,1024 # 400
	40	144: 40 20 00 00 nop \$0
	41	148: 42 00 01 4e ila \$78,2
	42	14c: 32 00 06 80 br 180 <__ovly_load> # 180
2cb5950e	43	14c: SPU_REL16 __ovly_load
0fd7d342 AM	44	#...
	45	Disassembly of section \.ov_a1:
	46
	47	00000400 <f1_a1>:
	48	400: 35 00 00 00 bi \$0
	49	\.\.\.
	50	Disassembly of section \.ov_a2:
	51
c1b2796f	52	00000400 <f1_a2>:
0fd7d342 AM	53	400: 32 7f a2 00 br 110 <longjmp> # 110
	54	400: SPU_REL16 longjmp
	55	\.\.\.
	56	Disassembly of section \.data:
	57
	58	00000410 <_ovly_table>:
	59	410: 00 00 04 00 .*
	60	414: 00 00 00 10 .*
b7b949f5	61	418: 00 00 02 d0 .*
0fd7d342 AM	62	41c: 00 00 00 01 .*
	63	420: 00 00 04 00 .*
	64	424: 00 00 00 10 .*
b7b949f5	65	428: 00 00 02 e0 .*
0fd7d342 AM	66	42c: 00 00 00 01 .*
	67
	68	00000430 <_ovly_buf_table>:
	69	430: 00 00 00 00 .*
	70	Disassembly of section \.toe:
	71
	72	00000440 <_EAR_>:
	73	\.\.\.
	74	Disassembly of section \.note\.spu_name:
	75
	76	.* <\.note\.spu_name>:
	77	.: 00 00 00 08 .
	78	.: 00 00 00 0c .
	79	.: 00 00 00 01 .
	80	.: 53 50 55 4e .
	81	.: 41 4d 45 00 .
	82	.: 74 6d 70 64 .
	83	.: 69 72 2f 64 .
	84	.: 75 6d 70 00 .