[people/ms/u-boot.git] / lib_m68k / time.c

/*
 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

#include <asm/mcftimer.h>

#ifdef	CONFIG_M5272
#include <asm/m5272.h>
#include <asm/immap_5272.h>
#endif

#ifdef	CONFIG_M5282
#include <asm/m5282.h>
#endif

#ifdef	CONFIG_M5249
#include <asm/m5249.h>
#include <asm/immap_5249.h>
#endif


static ulong timestamp;
#ifdef	CONFIG_M5282
static unsigned short lastinc;
#endif


#if defined(CONFIG_M5272)
/*
 * We use timer 3 which is running with a period of 1 us
 */
void udelay(unsigned long usec)
{
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE3);
	uint start, now, tmp;

	while (usec > 0) {
		if (usec > 65000)
			tmp = 65000;
		else
			tmp = usec;
		usec = usec - tmp;

		/* Set up TIMER 3 as timebase clock */
		timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
		timerp->timer_tcn = 0;
		/* set period to 1 us */
		timerp->timer_tmr = (((CFG_CLK / 1000000) - 1)	<< 8) | MCFTIMER_TMR_CLK1 |
				     MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE;

		start = now = timerp->timer_tcn;
		while (now < start + tmp)
			now = timerp->timer_tcn;
	}
}

void mcf_timer_interrupt (void * not_used){
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
	volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);

	/* check for timer 4 interrupts */
	if ((intp->int_isr & 0x01000000) != 0) {
		return;
	}

	/* reset timer */
	timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
	timestamp ++;
}

void timer_init (void) {
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
	volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);

	timestamp = 0;

	/* Set up TIMER 4 as clock */
	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;

	/* initialize and enable timer 4 interrupt */
	irq_install_handler (72, mcf_timer_interrupt, 0);
	intp->int_icr1 |= 0x0000000d;

	timerp->timer_tcn = 0;
	timerp->timer_trr = 1000;	/* Interrupt every ms */
	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
	timerp->timer_tmr = (((CFG_CLK / 1000000) - 1)	<< 8) | MCFTIMER_TMR_CLK1 |
		MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
}

void reset_timer (void)
{
	timestamp = 0;
}

ulong get_timer (ulong base)
{
	return (timestamp - base);
}

void set_timer (ulong t)
{
	timestamp = t;
}
#endif

#if defined(CONFIG_M5282)

void udelay(unsigned long usec)
{
	volatile unsigned short *timerp;
	uint tmp;

	timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE3);

	while (usec > 0) {
		if (usec > 65000)
			tmp = 65000;
		else
			tmp = usec;
		usec = usec - tmp;

		/* Set up TIMER 3 as timebase clock */
		timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
		timerp[MCFTIMER_PMR] = 0;
		/* set period to 1 us */
		timerp[MCFTIMER_PCSR] =
			(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;

		timerp[MCFTIMER_PMR] = tmp;
		while (timerp[MCFTIMER_PCNTR] > 0);
	}
}

void timer_init (void)
{
	volatile unsigned short *timerp;

	timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
	timestamp = 0;

	/* Set up TIMER 4 as poll clock */
	timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
	timerp[MCFTIMER_PMR] = lastinc = 0;
	timerp[MCFTIMER_PCSR] =
		(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
}

void set_timer (ulong t)
{
	volatile unsigned short *timerp;

	timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
	timestamp = 0;
	timerp[MCFTIMER_PMR] = lastinc = 0;
}

ulong get_timer (ulong base)
{
	unsigned short now, diff;
	volatile unsigned short *timerp;

	timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
	now = timerp[MCFTIMER_PCNTR];
	diff = -(now - lastinc);

	timestamp += diff;
	lastinc = now;
	return timestamp - base;
}

void wait_ticks (unsigned long ticks)
{
	set_timer (0);
	while (get_timer (0) < ticks);
}
#endif


#if defined(CONFIG_M5249)
/*
 * We use timer 1 which is running with a period of 1 us
 */
void udelay(unsigned long usec)
{
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE1);
	uint start, now, tmp;

	while (usec > 0) {
		if (usec > 65000)
			tmp = 65000;
		else
			tmp = usec;
		usec = usec - tmp;

		/* Set up TIMER 1 as timebase clock */
		timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
		timerp->timer_tcn = 0;
		/* set period to 1 us */
		/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
		timerp->timer_tmr = (((CFG_CLK / 2000000) - 1)	<< 8) | MCFTIMER_TMR_CLK1 |
				     MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE;

		start = now = timerp->timer_tcn;
		while (now < start + tmp)
			now = timerp->timer_tcn;
	}
}

void mcf_timer_interrupt (void * not_used){
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);

	/* check for timer 2 interrupts */
	if ((mbar_readLong(MCFSIM_IPR) & 0x00000400) == 0) {
		return;
	}

	/* reset timer */
	timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
	timestamp ++;
}

void timer_init (void) {
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);

	timestamp = 0;

	/* Set up TIMER 2 as clock */
	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;

	/* initialize and enable timer 2 interrupt */
	irq_install_handler (31, mcf_timer_interrupt, 0);
	mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
	mbar_writeByte(MCFSIM_TIMER2ICR, MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3);

	timerp->timer_tcn = 0;
	timerp->timer_trr = 1000;	/* Interrupt every ms */
	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
	/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
	timerp->timer_tmr = (((CFG_CLK / 2000000) - 1)	<< 8) | MCFTIMER_TMR_CLK1 |
		MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
}

void reset_timer (void)
{
	timestamp = 0;
}

ulong get_timer (ulong base)
{
	return (timestamp - base);
}

void set_timer (ulong t)
{
	timestamp = t;
}
#endif


/*
 * This function is derived from PowerPC code (read timebase as long long).
 * On M68K it just returns the timer value.
 */
unsigned long long get_ticks(void)
{
	return get_timer(0);
}

/*
 * This function is derived from PowerPC code (timebase clock frequency).
 * On M68K it returns the number of timer ticks per second.
 */
ulong get_tbclk (void)
{
	ulong tbclk;
	tbclk = CFG_HZ;
	return tbclk;
}
Commit	Line	Data
4e5ca3eb	1	/*
bf9e3b38 WD	2	* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
	3	*
	4	* (C) Copyright 2000
4e5ca3eb WD	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
bf9e3b38	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4e5ca3eb WD	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27
bf9e3b38 WD	28	#include <asm/mcftimer.h>
	29
	30	#ifdef CONFIG_M5272
	31	#include <asm/m5272.h>
	32	#include <asm/immap_5272.h>
	33	#endif
	34
	35	#ifdef CONFIG_M5282
	36	#include <asm/m5282.h>
	37	#endif
	38
cd42deeb SR	39	#ifdef CONFIG_M5249
	40	#include <asm/m5249.h>
	41	#include <asm/immap_5249.h>
	42	#endif
	43
bf9e3b38 WD	44
	45	static ulong timestamp;
	46	#ifdef CONFIG_M5282
	47	static unsigned short lastinc;
	48	#endif
4e5ca3eb	49
4e5ca3eb	50
bf9e3b38	51	#if defined(CONFIG_M5272)
4e5ca3eb	52	/*
bf9e3b38	53	* We use timer 3 which is running with a period of 1 us
4e5ca3eb	54	*/
bf9e3b38	55	void udelay(unsigned long usec)
4e5ca3eb	56	{
bf9e3b38 WD	57	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE3);
	58	uint start, now, tmp;
	59
	60	while (usec > 0) {
	61	if (usec > 65000)
	62	tmp = 65000;
	63	else
	64	tmp = usec;
	65	usec = usec - tmp;
	66
	67	/* Set up TIMER 3 as timebase clock */
	68	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
	69	timerp->timer_tcn = 0;
	70	/* set period to 1 us */
	71	timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) \| MCFTIMER_TMR_CLK1 \|
	72	MCFTIMER_TMR_FREERUN \| MCFTIMER_TMR_ENABLE;
	73
	74	start = now = timerp->timer_tcn;
	75	while (now < start + tmp)
	76	now = timerp->timer_tcn;
	77	}
	78	}
	79
	80	void mcf_timer_interrupt (void * not_used){
	81	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE4);
	82	volatile intctrl_t intp = (intctrl_t ) (CFG_MBAR + MCFSIM_ICR1);
4e5ca3eb	83
bf9e3b38 WD	84	/* check for timer 4 interrupts */
	85	if ((intp->int_isr & 0x01000000) != 0) {
	86	return;
4e5ca3eb WD	87	}
4e5ca3eb WD	88
bf9e3b38 WD	89	/* reset timer */
	90	timerp->timer_ter = MCFTIMER_TER_CAP \| MCFTIMER_TER_REF;
	91	timestamp ++;
4e5ca3eb WD	92	}
4e5ca3eb WD	93
bf9e3b38 WD	94	void timer_init (void) {
	95	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE4);
	96	volatile intctrl_t intp = (intctrl_t ) (CFG_MBAR + MCFSIM_ICR1);
4e5ca3eb	97
bf9e3b38 WD	98	timestamp = 0;
	99
	100	/* Set up TIMER 4 as clock */
	101	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
	102
	103	/* initialize and enable timer 4 interrupt */
	104	irq_install_handler (72, mcf_timer_interrupt, 0);
	105	intp->int_icr1 \|= 0x0000000d;
	106
	107	timerp->timer_tcn = 0;
	108	timerp->timer_trr = 1000; /* Interrupt every ms */
	109	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
	110	timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) \| MCFTIMER_TMR_CLK1 \|
	111	MCFTIMER_TMR_RESTART \| MCFTIMER_TMR_ENORI \| MCFTIMER_TMR_ENABLE;
	112	}
	113
	114	void reset_timer (void)
4e5ca3eb	115	{
bf9e3b38 WD	116	timestamp = 0;
bf9e3b38 WD	117	}
4e5ca3eb	118
bf9e3b38 WD	119	ulong get_timer (ulong base)
	120	{
	121	return (timestamp - base);
4e5ca3eb WD	122	}
4e5ca3eb WD	123
bf9e3b38 WD	124	void set_timer (ulong t)
	125	{
	126	timestamp = t;
	127	}
	128	#endif
4e5ca3eb	129
bf9e3b38 WD	130	#if defined(CONFIG_M5282)
	131
	132	void udelay(unsigned long usec)
4e5ca3eb	133	{
50712ba1 WD	134	volatile unsigned short *timerp;
	135	uint tmp;
	136
	137	timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE3);
3c2b3d45	138
50712ba1 WD	139	while (usec > 0) {
	140	if (usec > 65000)
	141	tmp = 65000;
	142	else
	143	tmp = usec;
	144	usec = usec - tmp;
	145
	146	/* Set up TIMER 3 as timebase clock */
	147	timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
	148	timerp[MCFTIMER_PMR] = 0;
	149	/* set period to 1 us */
	150	timerp[MCFTIMER_PCSR] =
	151	(5 << 8) \| MCFTIMER_PCSR_EN \| MCFTIMER_PCSR_OVW;
	152
3c2b3d45	153	timerp[MCFTIMER_PMR] = tmp;
50712ba1 WD	154	while (timerp[MCFTIMER_PCNTR] > 0);
50712ba1 WD	155	}
4e5ca3eb WD	156	}
4e5ca3eb WD	157
bf9e3b38 WD	158	void timer_init (void)
	159	{
	160	volatile unsigned short *timerp;
	161
	162	timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
	163	timestamp = 0;
	164
	165	/* Set up TIMER 4 as poll clock */
	166	timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
	167	timerp[MCFTIMER_PMR] = lastinc = 0;
	168	timerp[MCFTIMER_PCSR] =
	169	(5 << 8) \| MCFTIMER_PCSR_EN \| MCFTIMER_PCSR_OVW;
	170	}
4e5ca3eb	171
bf9e3b38	172	void set_timer (ulong t)
4e5ca3eb	173	{
bf9e3b38 WD	174	volatile unsigned short *timerp;
	175
	176	timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
	177	timestamp = 0;
	178	timerp[MCFTIMER_PMR] = lastinc = 0;
	179	}
	180
	181	ulong get_timer (ulong base)
	182	{
	183	unsigned short now, diff;
	184	volatile unsigned short *timerp;
	185
	186	timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
	187	now = timerp[MCFTIMER_PCNTR];
	188	diff = -(now - lastinc);
	189
	190	timestamp += diff;
	191	lastinc = now;
	192	return timestamp - base;
4e5ca3eb WD	193	}
4e5ca3eb WD	194
bf9e3b38 WD	195	void wait_ticks (unsigned long ticks)
	196	{
	197	set_timer (0);
	198	while (get_timer (0) < ticks);
	199	}
	200	#endif
70f05ac3 WD	201
70f05ac3 WD	202
cd42deeb SR	203	#if defined(CONFIG_M5249)
	204	/*
	205	* We use timer 1 which is running with a period of 1 us
	206	*/
	207	void udelay(unsigned long usec)
	208	{
	209	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE1);
	210	uint start, now, tmp;
	211
	212	while (usec > 0) {
	213	if (usec > 65000)
	214	tmp = 65000;
	215	else
	216	tmp = usec;
	217	usec = usec - tmp;
	218
	219	/* Set up TIMER 1 as timebase clock */
	220	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
	221	timerp->timer_tcn = 0;
	222	/* set period to 1 us */
	223	/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
	224	timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) \| MCFTIMER_TMR_CLK1 \|
	225	MCFTIMER_TMR_FREERUN \| MCFTIMER_TMR_ENABLE;
	226
	227	start = now = timerp->timer_tcn;
	228	while (now < start + tmp)
	229	now = timerp->timer_tcn;
	230	}
	231	}
	232
	233	void mcf_timer_interrupt (void * not_used){
	234	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE2);
	235
	236	/* check for timer 2 interrupts */
	237	if ((mbar_readLong(MCFSIM_IPR) & 0x00000400) == 0) {
	238	return;
	239	}
	240
	241	/* reset timer */
	242	timerp->timer_ter = MCFTIMER_TER_CAP \| MCFTIMER_TER_REF;
	243	timestamp ++;
	244	}
	245
	246	void timer_init (void) {
	247	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE2);
	248
	249	timestamp = 0;
	250
	251	/* Set up TIMER 2 as clock */
	252	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
	253
	254	/* initialize and enable timer 2 interrupt */
	255	irq_install_handler (31, mcf_timer_interrupt, 0);
	256	mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
	257	mbar_writeByte(MCFSIM_TIMER2ICR, MCFSIM_ICR_AUTOVEC \| MCFSIM_ICR_LEVEL7 \| MCFSIM_ICR_PRI3);
	258
	259	timerp->timer_tcn = 0;
	260	timerp->timer_trr = 1000; /* Interrupt every ms */
	261	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
	262	/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
	263	timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) \| MCFTIMER_TMR_CLK1 \|
	264	MCFTIMER_TMR_RESTART \| MCFTIMER_TMR_ENORI \| MCFTIMER_TMR_ENABLE;
	265	}
	266
267	void reset_timer (void)
268	{
269	timestamp = 0;
270	}
271
272	ulong get_timer (ulong base)
273	{
274	return (timestamp - base);
275	}
276
277	void set_timer (ulong t)
278	{
279	timestamp = t;
280	}
281	#endif
282
283
70f05ac3 WD	284	/*
	285	* This function is derived from PowerPC code (read timebase as long long).
	286	* On M68K it just returns the timer value.
	287	*/
	288	unsigned long long get_ticks(void)
	289	{
	290	return get_timer(0);
	291	}
	292
	293	/*
	294	* This function is derived from PowerPC code (timebase clock frequency).
	295	* On M68K it returns the number of timer ticks per second.
	296	*/
	297	ulong get_tbclk (void)
	298	{
	299	ulong tbclk;
	300	tbclk = CFG_HZ;
	301	return tbclk;
	302	}