[people/ms/u-boot.git] / lib_m68k / time.c

/*
 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

#include <asm/mcftimer.h>
#include <asm/timer.h>
#include <asm/immap.h>

#ifdef	CONFIG_M5271
#include <asm/m5271.h>
#include <asm/immap_5271.h>
#endif

#ifdef	CONFIG_M5272
#include <asm/m5272.h>
#include <asm/immap_5272.h>
#endif

#ifdef	CONFIG_M5282
#include <asm/m5282.h>
#endif

#ifdef	CONFIG_M5249
#include <asm/m5249.h>
#include <asm/immap_5249.h>
#endif

static ulong timestamp;
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
static unsigned short lastinc;
#endif

#if defined(CONFIG_M5272)
/*
 * We use timer 3 which is running with a period of 1 us
 */
void udelay(unsigned long usec)
{
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE3);
	uint start, now, tmp;

	while (usec > 0) {
		if (usec > 65000)
			tmp = 65000;
		else
			tmp = usec;
		usec = usec - tmp;

		/* Set up TIMER 3 as timebase clock */
		timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
		timerp->timer_tcn = 0;
		/* set period to 1 us */
		timerp->timer_tmr =
		    (((CFG_CLK / 1000000) -
		      1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_FREERUN |
		    MCFTIMER_TMR_ENABLE;

		start = now = timerp->timer_tcn;
		while (now < start + tmp)
			now = timerp->timer_tcn;
	}
}

void mcf_timer_interrupt(void *not_used)
{
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
	volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);

	/* check for timer 4 interrupts */
	if ((intp->int_isr & 0x01000000) != 0) {
		return;
	}

	/* reset timer */
	timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
	timestamp++;
}

void timer_init(void)
{
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
	volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);

	timestamp = 0;

	/* Set up TIMER 4 as clock */
	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;

	/* initialize and enable timer 4 interrupt */
	irq_install_handler(72, mcf_timer_interrupt, 0);
	intp->int_icr1 |= 0x0000000d;

	timerp->timer_tcn = 0;
	timerp->timer_trr = 1000;	/* Interrupt every ms */
	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
	timerp->timer_tmr =
	    (((CFG_CLK / 1000000) -
	      1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_RESTART |
	    MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
}

void reset_timer(void)
{
	timestamp = 0;
}

ulong get_timer(ulong base)
{
	return (timestamp - base);
}

void set_timer(ulong t)
{
	timestamp = t;
}
#endif

#if defined(CONFIG_M5282) || defined(CONFIG_M5271)

void udelay(unsigned long usec)
{
	volatile unsigned short *timerp;
	uint tmp;

	timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE3);

	while (usec > 0) {
		if (usec > 65000)
			tmp = 65000;
		else
			tmp = usec;
		usec = usec - tmp;

		/* Set up TIMER 3 as timebase clock */
		timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
		timerp[MCFTIMER_PMR] = 0;
		/* set period to 1 us */
		timerp[MCFTIMER_PCSR] =
#ifdef CONFIG_M5271
		    (6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
#else				/* !CONFIG_M5271 */
		    (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
#endif				/* CONFIG_M5271 */

		timerp[MCFTIMER_PMR] = tmp;
		while (timerp[MCFTIMER_PCNTR] > 0) ;
	}
}

void timer_init(void)
{
	volatile unsigned short *timerp;

	timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4);
	timestamp = 0;

	/* Set up TIMER 4 as poll clock */
	timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
	timerp[MCFTIMER_PMR] = lastinc = 0;
	timerp[MCFTIMER_PCSR] =
#ifdef CONFIG_M5271
	    (6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
#else				/* !CONFIG_M5271 */
	    (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
#endif				/* CONFIG_M5271 */
}

void set_timer(ulong t)
{
	volatile unsigned short *timerp;

	timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4);
	timestamp = 0;
	timerp[MCFTIMER_PMR] = lastinc = 0;
}

ulong get_timer(ulong base)
{
	unsigned short now, diff;
	volatile unsigned short *timerp;

	timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4);
	now = timerp[MCFTIMER_PCNTR];
	diff = -(now - lastinc);

	timestamp += diff;
	lastinc = now;
	return timestamp - base;
}

void wait_ticks(unsigned long ticks)
{
	set_timer(0);
	while (get_timer(0) < ticks) ;
}
#endif

#if defined(CONFIG_M5249)
/*
 * We use timer 1 which is running with a period of 1 us
 */
void udelay(unsigned long usec)
{
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE1);
	uint start, now, tmp;

	while (usec > 0) {
		if (usec > 65000)
			tmp = 65000;
		else
			tmp = usec;
		usec = usec - tmp;

		/* Set up TIMER 1 as timebase clock */
		timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
		timerp->timer_tcn = 0;
		/* set period to 1 us */
		/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
		timerp->timer_tmr =
		    (((CFG_CLK / 2000000) -
		      1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_FREERUN |
		    MCFTIMER_TMR_ENABLE;

		start = now = timerp->timer_tcn;
		while (now < start + tmp)
			now = timerp->timer_tcn;
	}
}

void mcf_timer_interrupt(void *not_used)
{
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);

	/* check for timer 2 interrupts */
	if ((mbar_readLong(MCFSIM_IPR) & 0x00000400) == 0) {
		return;
	}

	/* reset timer */
	timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
	timestamp++;
}

void timer_init(void)
{
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);

	timestamp = 0;

	/* Set up TIMER 2 as clock */
	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;

	/* initialize and enable timer 2 interrupt */
	irq_install_handler(31, mcf_timer_interrupt, 0);
	mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
	mbar_writeByte(MCFSIM_TIMER2ICR,
		       MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 |
		       MCFSIM_ICR_PRI3);

	timerp->timer_tcn = 0;
	timerp->timer_trr = 1000;	/* Interrupt every ms */
	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
	/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
	timerp->timer_tmr =
	    (((CFG_CLK / 2000000) -
	      1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_RESTART |
	    MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
}

void reset_timer(void)
{
	timestamp = 0;
}

ulong get_timer(ulong base)
{
	return (timestamp - base);
}

void set_timer(ulong t)
{
	timestamp = t;
}
#endif

#if defined(CONFIG_MCFTMR)
#ifndef CFG_UDELAY_BASE
#	error	"uDelay base not defined!"
#endif

#if !defined(CFG_TMR_BASE) || !defined(CFG_INTR_BASE) || !defined(CFG_TMRINTR_NO) || !defined(CFG_TMRINTR_MASK)
#	error	"TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
#endif
extern void dtimer_intr_setup(void);

void udelay(unsigned long usec)
{
	volatile dtmr_t *timerp = (dtmr_t *) (CFG_UDELAY_BASE);
	uint start, now, tmp;

	while (usec > 0) {
		if (usec > 65000)
			tmp = 65000;
		else
			tmp = usec;
		usec = usec - tmp;

		/* Set up TIMER 3 as timebase clock */
		timerp->tmr = DTIM_DTMR_RST_RST;
		timerp->tcn = 0;
		/* set period to 1 us */
		timerp->tmr =
		    CFG_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
		    DTIM_DTMR_RST_EN;

		start = now = timerp->tcn;
		while (now < start + tmp)
			now = timerp->tcn;
	}
}

void dtimer_interrupt(void *not_used)
{
	volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE);
	volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);

	/* check for timer interrupt asserted */
	if ((intp->iprh0 & CFG_TMRINTR_MASK) == CFG_TMRINTR_MASK) {
		timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
		timestamp++;
		return;
	}
}

void timer_init(void)
{
	volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE);

	timestamp = 0;

	timerp->tcn = 0;
	timerp->trr = 0;

	/* Set up TIMER 4 as clock */
	timerp->tmr = DTIM_DTMR_RST_RST;

	/* initialize and enable timer interrupt */
	irq_install_handler(CFG_TMRINTR_NO, dtimer_interrupt, 0);

	timerp->tcn = 0;
	timerp->trr = 1000;	/* Interrupt every ms */

	dtimer_intr_setup();

	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
	timerp->tmr = CFG_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
	    DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
}

void reset_timer(void)
{
	timestamp = 0;
}

ulong get_timer(ulong base)
{
	return (timestamp - base);
}

void set_timer(ulong t)
{
	timestamp = t;
}
#endif				/* CONFIG_MCFTMR */

#if defined(CONFIG_MCFPIT)
#if !defined(CFG_PIT_BASE)
#	error	"CFG_PIT_BASE not defined!"
#endif

static unsigned short lastinc;

void udelay(unsigned long usec)
{
	volatile pit_t *timerp = (pit_t *) (CFG_UDELAY_BASE);
	uint tmp;

	while (usec > 0) {
		if (usec > 65000)
			tmp = 65000;
		else
			tmp = usec;
		usec = usec - tmp;

		/* Set up TIMER 3 as timebase clock */
		timerp->pcsr = PIT_PCSR_OVW;
		timerp->pmr = 0;
		/* set period to 1 us */
		timerp->pcsr |= PIT_PCSR_PRE(CFG_PIT_PRESCALE) | PIT_PCSR_EN;

		timerp->pmr = tmp;
		while (timerp->pcntr > 0) ;
	}
}

void timer_init(void)
{
	volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE);
	timestamp = 0;

	/* Set up TIMER 4 as poll clock */
	timerp->pcsr = PIT_PCSR_OVW;
	timerp->pmr = lastinc = 0;
	timerp->pcsr |= PIT_PCSR_PRE(CFG_PIT_PRESCALE) | PIT_PCSR_EN;
}

void set_timer(ulong t)
{
	volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE);

	timestamp = 0;
	timerp->pmr = lastinc = 0;
}

ulong get_timer(ulong base)
{
	unsigned short now, diff;
	volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE);

	now = timerp->pcntr;
	diff = -(now - lastinc);

	timestamp += diff;
	lastinc = now;
	return timestamp - base;
}

void wait_ticks(unsigned long ticks)
{
	set_timer(0);
	while (get_timer(0) < ticks) ;
}
#endif				/* CONFIG_MCFPIT */

/*
 * This function is derived from PowerPC code (read timebase as long long).
 * On M68K it just returns the timer value.
 */
unsigned long long get_ticks(void)
{
	return get_timer(0);
}

/*
 * This function is derived from PowerPC code (timebase clock frequency).
 * On M68K it returns the number of timer ticks per second.
 */
ulong get_tbclk(void)
{
	ulong tbclk;
	tbclk = CFG_HZ;
	return tbclk;
}
Commit	Line	Data
4e5ca3eb	1	/*
bf9e3b38 WD	2	* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
	3	*
	4	* (C) Copyright 2000
4e5ca3eb WD	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
bf9e3b38	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4e5ca3eb WD	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27
bf9e3b38	28	#include <asm/mcftimer.h>
52b01760 TL	29	#include <asm/timer.h>
52b01760 TL	30	#include <asm/immap.h>
bf9e3b38	31
eacbd317 ZL	32	#ifdef CONFIG_M5271
	33	#include <asm/m5271.h>
	34	#include <asm/immap_5271.h>
	35	#endif
	36
bf9e3b38 WD	37	#ifdef CONFIG_M5272
	38	#include <asm/m5272.h>
	39	#include <asm/immap_5272.h>
	40	#endif
	41
	42	#ifdef CONFIG_M5282
	43	#include <asm/m5282.h>
	44	#endif
	45
cd42deeb SR	46	#ifdef CONFIG_M5249
	47	#include <asm/m5249.h>
	48	#include <asm/immap_5249.h>
	49	#endif
	50
bf9e3b38	51	static ulong timestamp;
eacbd317	52	#if defined(CONFIG_M5282) \|\| defined(CONFIG_M5271)
bf9e3b38 WD	53	static unsigned short lastinc;
bf9e3b38 WD	54	#endif
4e5ca3eb	55
bf9e3b38	56	#if defined(CONFIG_M5272)
4e5ca3eb	57	/*
bf9e3b38	58	* We use timer 3 which is running with a period of 1 us
4e5ca3eb	59	*/
bf9e3b38	60	void udelay(unsigned long usec)
4e5ca3eb	61	{
bf9e3b38 WD	62	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE3);
	63	uint start, now, tmp;
	64
	65	while (usec > 0) {
	66	if (usec > 65000)
	67	tmp = 65000;
	68	else
	69	tmp = usec;
	70	usec = usec - tmp;
	71
	72	/* Set up TIMER 3 as timebase clock */
	73	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
	74	timerp->timer_tcn = 0;
	75	/* set period to 1 us */
52b01760 TL	76	timerp->timer_tmr =
	77	(((CFG_CLK / 1000000) -
	78	1) << 8) \| MCFTIMER_TMR_CLK1 \| MCFTIMER_TMR_FREERUN \|
	79	MCFTIMER_TMR_ENABLE;
bf9e3b38 WD	80
	81	start = now = timerp->timer_tcn;
	82	while (now < start + tmp)
	83	now = timerp->timer_tcn;
	84	}
	85	}
	86
52b01760 TL	87	void mcf_timer_interrupt(void *not_used)
52b01760 TL	88	{
bf9e3b38 WD	89	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE4);
bf9e3b38 WD	90	volatile intctrl_t intp = (intctrl_t ) (CFG_MBAR + MCFSIM_ICR1);
4e5ca3eb	91
bf9e3b38 WD	92	/* check for timer 4 interrupts */
	93	if ((intp->int_isr & 0x01000000) != 0) {
	94	return;
4e5ca3eb WD	95	}
4e5ca3eb WD	96
bf9e3b38 WD	97	/* reset timer */
bf9e3b38 WD	98	timerp->timer_ter = MCFTIMER_TER_CAP \| MCFTIMER_TER_REF;
52b01760	99	timestamp++;
4e5ca3eb WD	100	}
4e5ca3eb WD	101
52b01760 TL	102	void timer_init(void)
52b01760 TL	103	{
bf9e3b38 WD	104	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE4);
bf9e3b38 WD	105	volatile intctrl_t intp = (intctrl_t ) (CFG_MBAR + MCFSIM_ICR1);
4e5ca3eb	106
bf9e3b38 WD	107	timestamp = 0;
	108
	109	/* Set up TIMER 4 as clock */
	110	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
	111
	112	/* initialize and enable timer 4 interrupt */
52b01760	113	irq_install_handler(72, mcf_timer_interrupt, 0);
bf9e3b38 WD	114	intp->int_icr1 \|= 0x0000000d;
	115
	116	timerp->timer_tcn = 0;
	117	timerp->timer_trr = 1000; /* Interrupt every ms */
	118	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
52b01760 TL	119	timerp->timer_tmr =
	120	(((CFG_CLK / 1000000) -
	121	1) << 8) \| MCFTIMER_TMR_CLK1 \| MCFTIMER_TMR_RESTART \|
	122	MCFTIMER_TMR_ENORI \| MCFTIMER_TMR_ENABLE;
bf9e3b38 WD	123	}
bf9e3b38 WD	124
52b01760	125	void reset_timer(void)
4e5ca3eb	126	{
bf9e3b38 WD	127	timestamp = 0;
bf9e3b38 WD	128	}
4e5ca3eb	129
52b01760	130	ulong get_timer(ulong base)
bf9e3b38 WD	131	{
bf9e3b38 WD	132	return (timestamp - base);
4e5ca3eb WD	133	}
4e5ca3eb WD	134
52b01760	135	void set_timer(ulong t)
bf9e3b38 WD	136	{
	137	timestamp = t;
	138	}
	139	#endif
4e5ca3eb	140
eacbd317	141	#if defined(CONFIG_M5282) \|\| defined(CONFIG_M5271)
bf9e3b38 WD	142
bf9e3b38 WD	143	void udelay(unsigned long usec)
4e5ca3eb	144	{
50712ba1 WD	145	volatile unsigned short *timerp;
	146	uint tmp;
	147
52b01760	148	timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE3);
3c2b3d45	149
50712ba1 WD	150	while (usec > 0) {
	151	if (usec > 65000)
	152	tmp = 65000;
	153	else
	154	tmp = usec;
	155	usec = usec - tmp;
	156
	157	/* Set up TIMER 3 as timebase clock */
	158	timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
	159	timerp[MCFTIMER_PMR] = 0;
	160	/* set period to 1 us */
	161	timerp[MCFTIMER_PCSR] =
daa6e418	162	#ifdef CONFIG_M5271
52b01760 TL	163	(6 << 8) \| MCFTIMER_PCSR_EN \| MCFTIMER_PCSR_OVW;
	164	#else /* !CONFIG_M5271 */
	165	(5 << 8) \| MCFTIMER_PCSR_EN \| MCFTIMER_PCSR_OVW;
	166	#endif /* CONFIG_M5271 */
50712ba1	167
3c2b3d45	168	timerp[MCFTIMER_PMR] = tmp;
52b01760	169	while (timerp[MCFTIMER_PCNTR] > 0) ;
50712ba1	170	}
4e5ca3eb WD	171	}
4e5ca3eb WD	172
52b01760	173	void timer_init(void)
bf9e3b38 WD	174	{
	175	volatile unsigned short *timerp;
	176
52b01760	177	timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4);
bf9e3b38 WD	178	timestamp = 0;
	179
	180	/* Set up TIMER 4 as poll clock */
	181	timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
	182	timerp[MCFTIMER_PMR] = lastinc = 0;
	183	timerp[MCFTIMER_PCSR] =
daa6e418	184	#ifdef CONFIG_M5271
52b01760 TL	185	(6 << 8) \| MCFTIMER_PCSR_EN \| MCFTIMER_PCSR_OVW;
	186	#else /* !CONFIG_M5271 */
	187	(5 << 8) \| MCFTIMER_PCSR_EN \| MCFTIMER_PCSR_OVW;
	188	#endif /* CONFIG_M5271 */
bf9e3b38	189	}
4e5ca3eb	190
52b01760	191	void set_timer(ulong t)
4e5ca3eb	192	{
bf9e3b38 WD	193	volatile unsigned short *timerp;
bf9e3b38 WD	194
52b01760	195	timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4);
bf9e3b38 WD	196	timestamp = 0;
	197	timerp[MCFTIMER_PMR] = lastinc = 0;
	198	}
	199
52b01760	200	ulong get_timer(ulong base)
bf9e3b38 WD	201	{
	202	unsigned short now, diff;
	203	volatile unsigned short *timerp;
	204
52b01760	205	timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4);
bf9e3b38 WD	206	now = timerp[MCFTIMER_PCNTR];
	207	diff = -(now - lastinc);
	208
	209	timestamp += diff;
	210	lastinc = now;
	211	return timestamp - base;
4e5ca3eb WD	212	}
4e5ca3eb WD	213
52b01760	214	void wait_ticks(unsigned long ticks)
bf9e3b38	215	{
52b01760 TL	216	set_timer(0);
52b01760 TL	217	while (get_timer(0) < ticks) ;
bf9e3b38 WD	218	}
bf9e3b38 WD	219	#endif
70f05ac3	220
cd42deeb SR	221	#if defined(CONFIG_M5249)
	222	/*
	223	* We use timer 1 which is running with a period of 1 us
	224	*/
	225	void udelay(unsigned long usec)
	226	{
	227	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE1);
	228	uint start, now, tmp;
	229
	230	while (usec > 0) {
	231	if (usec > 65000)
	232	tmp = 65000;
	233	else
	234	tmp = usec;
	235	usec = usec - tmp;
	236
	237	/* Set up TIMER 1 as timebase clock */
	238	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
	239	timerp->timer_tcn = 0;
	240	/* set period to 1 us */
	241	/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
52b01760 TL	242	timerp->timer_tmr =
	243	(((CFG_CLK / 2000000) -
	244	1) << 8) \| MCFTIMER_TMR_CLK1 \| MCFTIMER_TMR_FREERUN \|
	245	MCFTIMER_TMR_ENABLE;
cd42deeb SR	246
	247	start = now = timerp->timer_tcn;
	248	while (now < start + tmp)
	249	now = timerp->timer_tcn;
	250	}
	251	}
	252
52b01760 TL	253	void mcf_timer_interrupt(void *not_used)
52b01760 TL	254	{
cd42deeb SR	255	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE2);
	256
	257	/* check for timer 2 interrupts */
	258	if ((mbar_readLong(MCFSIM_IPR) & 0x00000400) == 0) {
	259	return;
	260	}
	261
	262	/* reset timer */
	263	timerp->timer_ter = MCFTIMER_TER_CAP \| MCFTIMER_TER_REF;
52b01760	264	timestamp++;
cd42deeb SR	265	}
cd42deeb SR	266
52b01760 TL	267	void timer_init(void)
52b01760 TL	268	{
cd42deeb SR	269	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE2);
	270
	271	timestamp = 0;
	272
	273	/* Set up TIMER 2 as clock */
	274	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
	275
	276	/* initialize and enable timer 2 interrupt */
52b01760	277	irq_install_handler(31, mcf_timer_interrupt, 0);
cd42deeb	278	mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
52b01760 TL	279	mbar_writeByte(MCFSIM_TIMER2ICR,
	280	MCFSIM_ICR_AUTOVEC \| MCFSIM_ICR_LEVEL7 \|
	281	MCFSIM_ICR_PRI3);
cd42deeb SR	282
	283	timerp->timer_tcn = 0;
	284	timerp->timer_trr = 1000; /* Interrupt every ms */
	285	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
	286	/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
52b01760 TL	287	timerp->timer_tmr =
	288	(((CFG_CLK / 2000000) -
	289	1) << 8) \| MCFTIMER_TMR_CLK1 \| MCFTIMER_TMR_RESTART \|
	290	MCFTIMER_TMR_ENORI \| MCFTIMER_TMR_ENABLE;
cd42deeb SR	291	}
cd42deeb SR	292
52b01760	293	void reset_timer(void)
cd42deeb SR	294	{
	295	timestamp = 0;
	296	}
	297
52b01760	298	ulong get_timer(ulong base)
cd42deeb SR	299	{
	300	return (timestamp - base);
	301	}
	302
52b01760	303	void set_timer(ulong t)
cd42deeb SR	304	{
	305	timestamp = t;
	306	}
	307	#endif
	308
8e585f02 TL	309	#if defined(CONFIG_MCFTMR)
	310	#ifndef CFG_UDELAY_BASE
	311	# error "uDelay base not defined!"
	312	#endif
	313
	314	#if !defined(CFG_TMR_BASE) \|\| !defined(CFG_INTR_BASE) \|\| !defined(CFG_TMRINTR_NO) \|\| !defined(CFG_TMRINTR_MASK)
	315	# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
	316	#endif
52b01760	317	extern void dtimer_intr_setup(void);
8e585f02 TL	318
	319	void udelay(unsigned long usec)
	320	{
	321	volatile dtmr_t timerp = (dtmr_t ) (CFG_UDELAY_BASE);
	322	uint start, now, tmp;
	323
	324	while (usec > 0) {
	325	if (usec > 65000)
	326	tmp = 65000;
	327	else
	328	tmp = usec;
	329	usec = usec - tmp;
	330
	331	/* Set up TIMER 3 as timebase clock */
	332	timerp->tmr = DTIM_DTMR_RST_RST;
	333	timerp->tcn = 0;
	334	/* set period to 1 us */
	335	timerp->tmr =
52b01760 TL	336	CFG_TIMER_PRESCALER \| DTIM_DTMR_CLK_DIV1 \| DTIM_DTMR_FRR \|
52b01760 TL	337	DTIM_DTMR_RST_EN;
8e585f02 TL	338
	339	start = now = timerp->tcn;
	340	while (now < start + tmp)
	341	now = timerp->tcn;
	342	}
	343	}
	344
	345	void dtimer_interrupt(void *not_used)
	346	{
	347	volatile dtmr_t timerp = (dtmr_t ) (CFG_TMR_BASE);
	348	volatile int0_t intp = (int0_t ) (CFG_INTR_BASE);
	349
	350	/* check for timer interrupt asserted */
	351	if ((intp->iprh0 & CFG_TMRINTR_MASK) == CFG_TMRINTR_MASK) {
	352	timerp->ter = (DTIM_DTER_CAP \| DTIM_DTER_REF);
	353	timestamp++;
	354	return;
	355	}
	356	}
	357
	358	void timer_init(void)
	359	{
	360	volatile dtmr_t timerp = (dtmr_t ) (CFG_TMR_BASE);
8e585f02 TL	361
	362	timestamp = 0;
	363
	364	timerp->tcn = 0;
	365	timerp->trr = 0;
	366
	367	/* Set up TIMER 4 as clock */
	368	timerp->tmr = DTIM_DTMR_RST_RST;
	369
52b01760	370	/* initialize and enable timer interrupt */
8e585f02	371	irq_install_handler(CFG_TMRINTR_NO, dtimer_interrupt, 0);
8e585f02 TL	372
	373	timerp->tcn = 0;
	374	timerp->trr = 1000; /* Interrupt every ms */
	375
52b01760	376	dtimer_intr_setup();
8e585f02 TL	377
	378	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
	379	timerp->tmr = CFG_TIMER_PRESCALER \| DTIM_DTMR_CLK_DIV1 \|
	380	DTIM_DTMR_FRR \| DTIM_DTMR_ORRI \| DTIM_DTMR_RST_EN;
	381	}
	382
	383	void reset_timer(void)
	384	{
	385	timestamp = 0;
	386	}
	387
	388	ulong get_timer(ulong base)
	389	{
	390	return (timestamp - base);
	391	}
	392
	393	void set_timer(ulong t)
	394	{
	395	timestamp = t;
	396	}
	397	#endif /* CONFIG_MCFTMR */
	398
	399	#if defined(CONFIG_MCFPIT)
	400	#if !defined(CFG_PIT_BASE)
	401	# error "CFG_PIT_BASE not defined!"
	402	#endif
	403
	404	static unsigned short lastinc;
	405
	406	void udelay(unsigned long usec)
	407	{
	408	volatile pit_t timerp = (pit_t ) (CFG_UDELAY_BASE);
	409	uint tmp;
	410
	411	while (usec > 0) {
	412	if (usec > 65000)
	413	tmp = 65000;
	414	else
	415	tmp = usec;
	416	usec = usec - tmp;
	417
	418	/* Set up TIMER 3 as timebase clock */
	419	timerp->pcsr = PIT_PCSR_OVW;
	420	timerp->pmr = 0;
	421	/* set period to 1 us */
	422	timerp->pcsr \|= PIT_PCSR_PRE(CFG_PIT_PRESCALE) \| PIT_PCSR_EN;
	423
	424	timerp->pmr = tmp;
	425	while (timerp->pcntr > 0) ;
	426	}
	427	}
	428
	429	void timer_init(void)
	430	{
	431	volatile pit_t timerp = (pit_t ) (CFG_PIT_BASE);
	432	timestamp = 0;
	433
	434	/* Set up TIMER 4 as poll clock */
	435	timerp->pcsr = PIT_PCSR_OVW;
	436	timerp->pmr = lastinc = 0;
	437	timerp->pcsr \|= PIT_PCSR_PRE(CFG_PIT_PRESCALE) \| PIT_PCSR_EN;
	438	}
	439
	440	void set_timer(ulong t)
441	{
442	volatile pit_t timerp = (pit_t ) (CFG_PIT_BASE);
443
444	timestamp = 0;
445	timerp->pmr = lastinc = 0;
446	}
447
448	ulong get_timer(ulong base)
449	{
450	unsigned short now, diff;
451	volatile pit_t timerp = (pit_t ) (CFG_PIT_BASE);
452
453	now = timerp->pcntr;
454	diff = -(now - lastinc);
455
456	timestamp += diff;
457	lastinc = now;
458	return timestamp - base;
459	}
460
461	void wait_ticks(unsigned long ticks)
462	{
463	set_timer(0);
464	while (get_timer(0) < ticks) ;
465	}
466	#endif /* CONFIG_MCFPIT */
cd42deeb	467
70f05ac3 WD	468	/*
	469	* This function is derived from PowerPC code (read timebase as long long).
	470	* On M68K it just returns the timer value.
	471	*/
	472	unsigned long long get_ticks(void)
	473	{
	474	return get_timer(0);
	475	}
	476
	477	/*
	478	* This function is derived from PowerPC code (timebase clock frequency).
	479	* On M68K it returns the number of timer ticks per second.
	480	*/
52b01760	481	ulong get_tbclk(void)
70f05ac3 WD	482	{
	483	ulong tbclk;
	484	tbclk = CFG_HZ;
	485	return tbclk;
	486	}