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feeeff5c 1/* Unsigned 32 bit division optimized for Epiphany.
a945c346 2 Copyright (C) 2009-2024 Free Software Foundation, Inc.
feeeff5c
JR
3 Contributed by Embecosm on behalf of Adapteva, Inc.
4
5This file is part of GCC.
6
7This file is free software; you can redistribute it and/or modify it
8under the terms of the GNU General Public License as published by the
9Free Software Foundation; either version 3, or (at your option) any
10later version.
11
12This file is distributed in the hope that it will be useful, but
13WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15General Public License for more details.
16
17Under Section 7 of GPL version 3, you are granted additional
18permissions described in the GCC Runtime Library Exception, version
193.1, as published by the Free Software Foundation.
20
21You should have received a copy of the GNU General Public License and
22a copy of the GCC Runtime Library Exception along with this program;
23see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
24<http://www.gnu.org/licenses/>. */
25
26#include "epiphany-asm.h"
27
28 FSTAB (__udivsi3,T_UINT)
29 .global SYM(__udivsi3)
30 .balign 4
31 HIDDEN_FUNC(__udivsi3)
32SYM(__udivsi3):
33 sub r3,r0,r1
34 bltu .Lret0
35 mov r3,0x95
36 lsl r12,r3,23 ; 0x4a800000
37 lsl r3,r3,30 ; 0x40000000
38 orr r16,r0,r3
39 orr r2,r1,r3
40 fsub r16,r16,r3
41 fsub r2,r2,r3
42 lsr r3,r1,21
43 lsr r17,r0,21
44 movt r17,0x4a80
45 fsub r17,r17,r12
46 movt r3,0x4a80
47 fsub r3,r3,r12
48 mov r12,%low(.L0step)
49 movt r12,%high(.L0step)
50 mov r21,1
51 movne r16,r17
52 lsr r17,r1,21
53 movne r2,r3
54 lsr r3,r16,23 ; must mask lower bits of r2 in case op0 was ..
55 lsr r2,r2,23 ; .. shifted and op1 was not.
56 sub r3,r3,r2 ; calculate bit number difference.
57 lsl r1,r1,r3
58 lsr r16,r1,1
59 lsl r2,r21,r3
60 lsl r3,r3,3
61 sub r12,r12,r3
62 sub r3,r0,r1
63 movltu r3,r0
64 mov r0,0
65 movgteu r0,r2
66 lsr r2,r2,1
67 add r17,r2,r0
68 sub r1,r3,r16
69 movgteu r3,r1
70 movgteu r0,r17
71 sub r16,r16,1
72 jr r12
73 .rep 30
74 lsl r3,r3,1
75 sub r1,r3,r16
76 movgteu r3,r1
77 .endr
78 sub r2,r2,1 ; mask result bits from steps ...
79 and r3,r3,r2
80 orr r0,r0,r3 ; ... and combine with first bits.
81 nop
82.L0step:rts
83.Lret0: mov r0,0
84 rts
85 ENDFUNC(__udivsi3)