[thirdparty/gcc.git] / libgcc / config / nds32 / isr-library / excp_isr.S

/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
   Copyright (C) 2012-2019 Free Software Foundation, Inc.
   Contributed by Andes Technology Corporation.

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published
   by the Free Software Foundation; either version 3, or (at your
   option) any later version.

   GCC is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   Under Section 7 of GPL version 3, you are granted additional
   permissions described in the GCC Runtime Library Exception, version
   3.1, as published by the Free Software Foundation.

   You should have received a copy of the GNU General Public License and
   a copy of the GCC Runtime Library Exception along with this program;
   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
   <http://www.gnu.org/licenses/>.  */

#include "save_usr_regs.inc"
#include "save_mac_regs.inc"
#include "save_fpu_regs.inc"
#include "save_fpu_regs_00.inc"
#include "save_fpu_regs_01.inc"
#include "save_fpu_regs_02.inc"
#include "save_fpu_regs_03.inc"
#include "save_all.inc"
#include "save_partial.inc"
#include "adj_intr_lvl.inc"
#include "restore_fpu_regs_00.inc"
#include "restore_fpu_regs_01.inc"
#include "restore_fpu_regs_02.inc"
#include "restore_fpu_regs_03.inc"
#include "restore_fpu_regs.inc"
#include "restore_mac_regs.inc"
#include "restore_usr_regs.inc"
#include "restore_all.inc"
#include "restore_partial.inc"

	.section .nds32_isr, "ax"       /* Put it in the section of 1st level handler. */
	.align	1

/* First Level Handlers
   1. First Level Handlers are invokded in vector section via jump instruction
      with specific names for different configurations.
   2. Naming Format: _nds32_e_SR_NT for exception handlers.
                     _nds32_i_SR_NT for interrupt handlers.
     2.1 All upper case letters are replaced with specific lower case letters encodings.
     2.2 SR -- Saved Registers
         sa: Save All regs (context)
         ps: Partial Save (all caller-saved regs)
     2.3 NT -- Nested Type
         ns: nested
         nn: not nested
         nr: nested ready */

#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
	.globl	_nds32_e_sa_ns
	.type	_nds32_e_sa_ns, @function
_nds32_e_sa_ns:
#elif defined(NDS32_NESTED_READY)
	.globl	_nds32_e_sa_nr
	.type	_nds32_e_sa_nr, @function
_nds32_e_sa_nr:
#else /* Not nested handler. */
	.globl	_nds32_e_sa_nn
	.type	_nds32_e_sa_nn, @function
_nds32_e_sa_nn:
#endif /* endif for Nest Type */
#else /* not NDS32_SAVE_ALL_REGS */
#if defined(NDS32_NESTED)
	.globl	_nds32_e_ps_ns
	.type	_nds32_e_ps_ns, @function
_nds32_e_ps_ns:
#elif defined(NDS32_NESTED_READY)
	.globl	_nds32_e_ps_nr
	.type	_nds32_e_ps_nr, @function
_nds32_e_ps_nr:
#else /* Not nested handler. */
	.globl	_nds32_e_ps_nn
	.type	_nds32_e_ps_nn, @function
_nds32_e_ps_nn:
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */


/* For 4-byte vector size version, the vector id is
   extracted from $ITYPE and is set into $r0 by library.
   For 16-byte vector size version, the vector id
   is set into $r0 in vector section by compiler.  */

/* Save used registers.  */
#ifdef NDS32_SAVE_ALL_REGS
        SAVE_ALL
#else
        SAVE_PARTIAL
#endif

	/* Prepare to call 2nd level handler. */
	la	$r2, _nds32_jmptbl_00
	lw	$r2, [$r2 + $r0 << #2]
	ADJ_INTR_LVL	/* Adjust INTR level. $r3 is clobbered.  */
	jral    $r2

/* Restore used registers.  */
#ifdef NDS32_SAVE_ALL_REGS
	RESTORE_ALL
#else
	RESTORE_PARTIAL
#endif
	iret


#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
	.size	_nds32_e_sa_ns, .-_nds32_e_sa_ns
#elif defined(NDS32_NESTED_READY)
	.size	_nds32_e_sa_nr, .-_nds32_e_sa_nr
#else /* Not nested handler. */
	.size	_nds32_e_sa_nn, .-_nds32_e_sa_nn
#endif /* endif for Nest Type */
#else /* not NDS32_SAVE_ALL_REGS */
#if defined(NDS32_NESTED)
	.size	_nds32_e_ps_ns, .-_nds32_e_ps_ns
#elif defined(NDS32_NESTED_READY)
	.size	_nds32_e_ps_nr, .-_nds32_e_ps_nr
#else /* Not nested handler. */
	.size	_nds32_e_ps_nn, .-_nds32_e_ps_nn
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */
Commit	Line	Data
9304f876	1	/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
a5544970	2	Copyright (C) 2012-2019 Free Software Foundation, Inc.
9304f876 CJW	3	Contributed by Andes Technology Corporation.
	4
	5	This file is part of GCC.
	6
	7	GCC is free software; you can redistribute it and/or modify it
	8	under the terms of the GNU General Public License as published
	9	by the Free Software Foundation; either version 3, or (at your
	10	option) any later version.
	11
	12	GCC is distributed in the hope that it will be useful, but WITHOUT
	13	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	License for more details.
	16
	17	Under Section 7 of GPL version 3, you are granted additional
	18	permissions described in the GCC Runtime Library Exception, version
	19	3.1, as published by the Free Software Foundation.
	20
	21	You should have received a copy of the GNU General Public License and
	22	a copy of the GCC Runtime Library Exception along with this program;
	23	see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
	24	<http://www.gnu.org/licenses/>. */
	25
a4931745	26	#include "save_usr_regs.inc"
9304f876 CJW	27	#include "save_mac_regs.inc"
	28	#include "save_fpu_regs.inc"
	29	#include "save_fpu_regs_00.inc"
	30	#include "save_fpu_regs_01.inc"
	31	#include "save_fpu_regs_02.inc"
	32	#include "save_fpu_regs_03.inc"
	33	#include "save_all.inc"
	34	#include "save_partial.inc"
	35	#include "adj_intr_lvl.inc"
9304f876 CJW	36	#include "restore_fpu_regs_00.inc"
	37	#include "restore_fpu_regs_01.inc"
	38	#include "restore_fpu_regs_02.inc"
	39	#include "restore_fpu_regs_03.inc"
	40	#include "restore_fpu_regs.inc"
a4931745 CJW	41	#include "restore_mac_regs.inc"
a4931745 CJW	42	#include "restore_usr_regs.inc"
9304f876 CJW	43	#include "restore_all.inc"
9304f876 CJW	44	#include "restore_partial.inc"
a4931745	45
9304f876 CJW	46	.section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
9304f876 CJW	47	.align 1
a4931745 CJW	48
	49	/* First Level Handlers
	50	1. First Level Handlers are invokded in vector section via jump instruction
	51	with specific names for different configurations.
	52	2. Naming Format: _nds32_e_SR_NT for exception handlers.
	53	_nds32_i_SR_NT for interrupt handlers.
	54	2.1 All upper case letters are replaced with specific lower case letters encodings.
	55	2.2 SR -- Saved Registers
	56	sa: Save All regs (context)
	57	ps: Partial Save (all caller-saved regs)
	58	2.3 NT -- Nested Type
	59	ns: nested
	60	nn: not nested
	61	nr: nested ready */
	62
9304f876 CJW	63	#ifdef NDS32_SAVE_ALL_REGS
	64	#if defined(NDS32_NESTED)
	65	.globl _nds32_e_sa_ns
	66	.type _nds32_e_sa_ns, @function
	67	_nds32_e_sa_ns:
	68	#elif defined(NDS32_NESTED_READY)
	69	.globl _nds32_e_sa_nr
	70	.type _nds32_e_sa_nr, @function
	71	_nds32_e_sa_nr:
	72	#else /* Not nested handler. */
	73	.globl _nds32_e_sa_nn
	74	.type _nds32_e_sa_nn, @function
	75	_nds32_e_sa_nn:
	76	#endif /* endif for Nest Type */
	77	#else /* not NDS32_SAVE_ALL_REGS */
	78	#if defined(NDS32_NESTED)
	79	.globl _nds32_e_ps_ns
	80	.type _nds32_e_ps_ns, @function
	81	_nds32_e_ps_ns:
	82	#elif defined(NDS32_NESTED_READY)
	83	.globl _nds32_e_ps_nr
	84	.type _nds32_e_ps_nr, @function
	85	_nds32_e_ps_nr:
	86	#else /* Not nested handler. */
	87	.globl _nds32_e_ps_nn
	88	.type _nds32_e_ps_nn, @function
	89	_nds32_e_ps_nn:
	90	#endif /* endif for Nest Type */
	91	#endif /* not NDS32_SAVE_ALL_REGS */
	92
a4931745 CJW	93
	94	/* For 4-byte vector size version, the vector id is
	95	extracted from $ITYPE and is set into $r0 by library.
	96	For 16-byte vector size version, the vector id
	97	is set into $r0 in vector section by compiler. */
	98
	99	/* Save used registers. */
9304f876 CJW	100	#ifdef NDS32_SAVE_ALL_REGS
	101	SAVE_ALL
	102	#else
	103	SAVE_PARTIAL
	104	#endif
a4931745	105
9304f876 CJW	106	/* Prepare to call 2nd level handler. */
	107	la $r2, _nds32_jmptbl_00
	108	lw $r2, [$r2 + $r0 << #2]
	109	ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
	110	jral $r2
a4931745 CJW	111
a4931745 CJW	112	/* Restore used registers. */
9304f876 CJW	113	#ifdef NDS32_SAVE_ALL_REGS
	114	RESTORE_ALL
	115	#else
	116	RESTORE_PARTIAL
	117	#endif
	118	iret
	119
a4931745	120
9304f876 CJW	121	#ifdef NDS32_SAVE_ALL_REGS
	122	#if defined(NDS32_NESTED)
	123	.size _nds32_e_sa_ns, .-_nds32_e_sa_ns
	124	#elif defined(NDS32_NESTED_READY)
	125	.size _nds32_e_sa_nr, .-_nds32_e_sa_nr
	126	#else /* Not nested handler. */
	127	.size _nds32_e_sa_nn, .-_nds32_e_sa_nn
	128	#endif /* endif for Nest Type */
	129	#else /* not NDS32_SAVE_ALL_REGS */
	130	#if defined(NDS32_NESTED)
	131	.size _nds32_e_ps_ns, .-_nds32_e_ps_ns
	132	#elif defined(NDS32_NESTED_READY)
	133	.size _nds32_e_ps_nr, .-_nds32_e_ps_nr
	134	#else /* Not nested handler. */
	135	.size _nds32_e_ps_nn, .-_nds32_e_ps_nn
	136	#endif /* endif for Nest Type */
	137	#endif /* not NDS32_SAVE_ALL_REGS */