[thirdparty/qemu.git] / linux-headers / asm-riscv / kvm.h

/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
 * Copyright (C) 2019 Western Digital Corporation or its affiliates.
 *
 * Authors:
 *     Anup Patel <anup.patel@wdc.com>
 */

#ifndef __LINUX_KVM_RISCV_H
#define __LINUX_KVM_RISCV_H

#ifndef __ASSEMBLY__

#include <linux/types.h>
#include <asm/ptrace.h>

#define __KVM_HAVE_READONLY_MEM

#define KVM_COALESCED_MMIO_PAGE_OFFSET 1

#define KVM_INTERRUPT_SET	-1U
#define KVM_INTERRUPT_UNSET	-2U

/* for KVM_GET_REGS and KVM_SET_REGS */
struct kvm_regs {
};

/* for KVM_GET_FPU and KVM_SET_FPU */
struct kvm_fpu {
};

/* KVM Debug exit structure */
struct kvm_debug_exit_arch {
};

/* for KVM_SET_GUEST_DEBUG */
struct kvm_guest_debug_arch {
};

/* definition of registers in kvm_run */
struct kvm_sync_regs {
};

/* for KVM_GET_SREGS and KVM_SET_SREGS */
struct kvm_sregs {
};

/* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
struct kvm_riscv_config {
	unsigned long isa;
};

/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
struct kvm_riscv_core {
	struct user_regs_struct regs;
	unsigned long mode;
};

/* Possible privilege modes for kvm_riscv_core */
#define KVM_RISCV_MODE_S	1
#define KVM_RISCV_MODE_U	0

/* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
struct kvm_riscv_csr {
	unsigned long sstatus;
	unsigned long sie;
	unsigned long stvec;
	unsigned long sscratch;
	unsigned long sepc;
	unsigned long scause;
	unsigned long stval;
	unsigned long sip;
	unsigned long satp;
	unsigned long scounteren;
};

/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
struct kvm_riscv_timer {
	__u64 frequency;
	__u64 time;
	__u64 compare;
	__u64 state;
};

/*
 * ISA extension IDs specific to KVM. This is not the same as the host ISA
 * extension IDs as that is internal to the host and should not be exposed
 * to the guest. This should always be contiguous to keep the mapping simple
 * in KVM implementation.
 */
enum KVM_RISCV_ISA_EXT_ID {
	KVM_RISCV_ISA_EXT_A = 0,
	KVM_RISCV_ISA_EXT_C,
	KVM_RISCV_ISA_EXT_D,
	KVM_RISCV_ISA_EXT_F,
	KVM_RISCV_ISA_EXT_H,
	KVM_RISCV_ISA_EXT_I,
	KVM_RISCV_ISA_EXT_M,
	KVM_RISCV_ISA_EXT_SVPBMT,
	KVM_RISCV_ISA_EXT_SSTC,
	KVM_RISCV_ISA_EXT_MAX,
};

/* Possible states for kvm_riscv_timer */
#define KVM_RISCV_TIMER_STATE_OFF	0
#define KVM_RISCV_TIMER_STATE_ON	1

#define KVM_REG_SIZE(id)		\
	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))

/* If you need to interpret the index values, here is the key: */
#define KVM_REG_RISCV_TYPE_MASK		0x00000000FF000000
#define KVM_REG_RISCV_TYPE_SHIFT	24

/* Config registers are mapped as type 1 */
#define KVM_REG_RISCV_CONFIG		(0x01 << KVM_REG_RISCV_TYPE_SHIFT)
#define KVM_REG_RISCV_CONFIG_REG(name)	\
	(offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))

/* Core registers are mapped as type 2 */
#define KVM_REG_RISCV_CORE		(0x02 << KVM_REG_RISCV_TYPE_SHIFT)
#define KVM_REG_RISCV_CORE_REG(name)	\
		(offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))

/* Control and status registers are mapped as type 3 */
#define KVM_REG_RISCV_CSR		(0x03 << KVM_REG_RISCV_TYPE_SHIFT)
#define KVM_REG_RISCV_CSR_REG(name)	\
		(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))

/* Timer registers are mapped as type 4 */
#define KVM_REG_RISCV_TIMER		(0x04 << KVM_REG_RISCV_TYPE_SHIFT)
#define KVM_REG_RISCV_TIMER_REG(name)	\
		(offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))

/* F extension registers are mapped as type 5 */
#define KVM_REG_RISCV_FP_F		(0x05 << KVM_REG_RISCV_TYPE_SHIFT)
#define KVM_REG_RISCV_FP_F_REG(name)	\
		(offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))

/* D extension registers are mapped as type 6 */
#define KVM_REG_RISCV_FP_D		(0x06 << KVM_REG_RISCV_TYPE_SHIFT)
#define KVM_REG_RISCV_FP_D_REG(name)	\
		(offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))

/* ISA Extension registers are mapped as type 7 */
#define KVM_REG_RISCV_ISA_EXT		(0x07 << KVM_REG_RISCV_TYPE_SHIFT)

#endif

#endif /* __LINUX_KVM_RISCV_H */
Commit	Line	Data
b91a0fa7 YJ	1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
	2	/*
	3	* Copyright (C) 2019 Western Digital Corporation or its affiliates.
	4	*
	5	* Authors:
	6	* Anup Patel <anup.patel@wdc.com>
	7	*/
	8
	9	#ifndef __LINUX_KVM_RISCV_H
	10	#define __LINUX_KVM_RISCV_H
	11
	12	#ifndef __ASSEMBLY__
	13
	14	#include <linux/types.h>
	15	#include <asm/ptrace.h>
	16
	17	#define __KVM_HAVE_READONLY_MEM
	18
	19	#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
	20
	21	#define KVM_INTERRUPT_SET -1U
	22	#define KVM_INTERRUPT_UNSET -2U
	23
	24	/* for KVM_GET_REGS and KVM_SET_REGS */
	25	struct kvm_regs {
	26	};
	27
	28	/* for KVM_GET_FPU and KVM_SET_FPU */
	29	struct kvm_fpu {
	30	};
	31
	32	/* KVM Debug exit structure */
	33	struct kvm_debug_exit_arch {
	34	};
	35
	36	/* for KVM_SET_GUEST_DEBUG */
	37	struct kvm_guest_debug_arch {
	38	};
	39
	40	/* definition of registers in kvm_run */
	41	struct kvm_sync_regs {
	42	};
	43
	44	/* for KVM_GET_SREGS and KVM_SET_SREGS */
	45	struct kvm_sregs {
	46	};
	47
	48	/* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
	49	struct kvm_riscv_config {
	50	unsigned long isa;
	51	};
	52
	53	/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
	54	struct kvm_riscv_core {
	55	struct user_regs_struct regs;
	56	unsigned long mode;
	57	};
	58
	59	/* Possible privilege modes for kvm_riscv_core */
	60	#define KVM_RISCV_MODE_S 1
	61	#define KVM_RISCV_MODE_U 0
	62
	63	/* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
	64	struct kvm_riscv_csr {
65	unsigned long sstatus;
66	unsigned long sie;
67	unsigned long stvec;
68	unsigned long sscratch;
69	unsigned long sepc;
70	unsigned long scause;
71	unsigned long stval;
72	unsigned long sip;
73	unsigned long satp;
74	unsigned long scounteren;
75	};
76
77	/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
78	struct kvm_riscv_timer {
79	__u64 frequency;
80	__u64 time;
81	__u64 compare;
82	__u64 state;
83	};
84
d525f73f CQ	85	/*
	86	* ISA extension IDs specific to KVM. This is not the same as the host ISA
	87	* extension IDs as that is internal to the host and should not be exposed
	88	* to the guest. This should always be contiguous to keep the mapping simple
	89	* in KVM implementation.
	90	*/
	91	enum KVM_RISCV_ISA_EXT_ID {
	92	KVM_RISCV_ISA_EXT_A = 0,
	93	KVM_RISCV_ISA_EXT_C,
	94	KVM_RISCV_ISA_EXT_D,
	95	KVM_RISCV_ISA_EXT_F,
	96	KVM_RISCV_ISA_EXT_H,
	97	KVM_RISCV_ISA_EXT_I,
	98	KVM_RISCV_ISA_EXT_M,
	99	KVM_RISCV_ISA_EXT_SVPBMT,
	100	KVM_RISCV_ISA_EXT_SSTC,
	101	KVM_RISCV_ISA_EXT_MAX,
	102	};
	103
b91a0fa7 YJ	104	/* Possible states for kvm_riscv_timer */
	105	#define KVM_RISCV_TIMER_STATE_OFF 0
	106	#define KVM_RISCV_TIMER_STATE_ON 1
	107
	108	#define KVM_REG_SIZE(id) \
	109	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
	110
	111	/* If you need to interpret the index values, here is the key: */
	112	#define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000
	113	#define KVM_REG_RISCV_TYPE_SHIFT 24
	114
	115	/* Config registers are mapped as type 1 */
	116	#define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT)
	117	#define KVM_REG_RISCV_CONFIG_REG(name) \
	118	(offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
	119
	120	/* Core registers are mapped as type 2 */
	121	#define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT)
	122	#define KVM_REG_RISCV_CORE_REG(name) \
	123	(offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
	124
	125	/* Control and status registers are mapped as type 3 */
	126	#define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
	127	#define KVM_REG_RISCV_CSR_REG(name) \
	128	(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
	129
	130	/* Timer registers are mapped as type 4 */
	131	#define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
	132	#define KVM_REG_RISCV_TIMER_REG(name) \
	133	(offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
	134
	135	/* F extension registers are mapped as type 5 */
	136	#define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT)
	137	#define KVM_REG_RISCV_FP_F_REG(name) \
	138	(offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
	139
	140	/* D extension registers are mapped as type 6 */
	141	#define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT)
	142	#define KVM_REG_RISCV_FP_D_REG(name) \
	143	(offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
	144
d525f73f CQ	145	/* ISA Extension registers are mapped as type 7 */
	146	#define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT)
	147
b91a0fa7 YJ	148	#endif
	149
	150	#endif /* __LINUX_KVM_RISCV_H */