[thirdparty/qemu.git] / linux-headers / asm-x86 / kvm.h

/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef _ASM_X86_KVM_H
#define _ASM_X86_KVM_H

/*
 * KVM x86 specific structures and definitions
 *
 */

#include <linux/types.h>
#include <linux/ioctl.h>

#define KVM_PIO_PAGE_OFFSET 1
#define KVM_COALESCED_MMIO_PAGE_OFFSET 2
#define KVM_DIRTY_LOG_PAGE_OFFSET 64

#define DE_VECTOR 0
#define DB_VECTOR 1
#define BP_VECTOR 3
#define OF_VECTOR 4
#define BR_VECTOR 5
#define UD_VECTOR 6
#define NM_VECTOR 7
#define DF_VECTOR 8
#define TS_VECTOR 10
#define NP_VECTOR 11
#define SS_VECTOR 12
#define GP_VECTOR 13
#define PF_VECTOR 14
#define MF_VECTOR 16
#define AC_VECTOR 17
#define MC_VECTOR 18
#define XM_VECTOR 19
#define VE_VECTOR 20

/* Select x86 specific features in <linux/kvm.h> */
#define __KVM_HAVE_PIT
#define __KVM_HAVE_IOAPIC
#define __KVM_HAVE_IRQ_LINE
#define __KVM_HAVE_MSI
#define __KVM_HAVE_USER_NMI
#define __KVM_HAVE_GUEST_DEBUG
#define __KVM_HAVE_MSIX
#define __KVM_HAVE_MCE
#define __KVM_HAVE_PIT_STATE2
#define __KVM_HAVE_XEN_HVM
#define __KVM_HAVE_VCPU_EVENTS
#define __KVM_HAVE_DEBUGREGS
#define __KVM_HAVE_XSAVE
#define __KVM_HAVE_XCRS
#define __KVM_HAVE_READONLY_MEM

/* Architectural interrupt line count. */
#define KVM_NR_INTERRUPTS 256

/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
struct kvm_pic_state {
	__u8 last_irr;	/* edge detection */
	__u8 irr;		/* interrupt request register */
	__u8 imr;		/* interrupt mask register */
	__u8 isr;		/* interrupt service register */
	__u8 priority_add;	/* highest irq priority */
	__u8 irq_base;
	__u8 read_reg_select;
	__u8 poll;
	__u8 special_mask;
	__u8 init_state;
	__u8 auto_eoi;
	__u8 rotate_on_auto_eoi;
	__u8 special_fully_nested_mode;
	__u8 init4;		/* true if 4 byte init */
	__u8 elcr;		/* PIIX edge/trigger selection */
	__u8 elcr_mask;
};

#define KVM_IOAPIC_NUM_PINS  24
struct kvm_ioapic_state {
	__u64 base_address;
	__u32 ioregsel;
	__u32 id;
	__u32 irr;
	__u32 pad;
	union {
		__u64 bits;
		struct {
			__u8 vector;
			__u8 delivery_mode:3;
			__u8 dest_mode:1;
			__u8 delivery_status:1;
			__u8 polarity:1;
			__u8 remote_irr:1;
			__u8 trig_mode:1;
			__u8 mask:1;
			__u8 reserve:7;
			__u8 reserved[4];
			__u8 dest_id;
		} fields;
	} redirtbl[KVM_IOAPIC_NUM_PINS];
};

#define KVM_IRQCHIP_PIC_MASTER   0
#define KVM_IRQCHIP_PIC_SLAVE    1
#define KVM_IRQCHIP_IOAPIC       2
#define KVM_NR_IRQCHIPS          3

#define KVM_RUN_X86_SMM		 (1 << 0)
#define KVM_RUN_X86_BUS_LOCK     (1 << 1)

/* for KVM_GET_REGS and KVM_SET_REGS */
struct kvm_regs {
	/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
	__u64 rax, rbx, rcx, rdx;
	__u64 rsi, rdi, rsp, rbp;
	__u64 r8,  r9,  r10, r11;
	__u64 r12, r13, r14, r15;
	__u64 rip, rflags;
};

/* for KVM_GET_LAPIC and KVM_SET_LAPIC */
#define KVM_APIC_REG_SIZE 0x400
struct kvm_lapic_state {
	char regs[KVM_APIC_REG_SIZE];
};

struct kvm_segment {
	__u64 base;
	__u32 limit;
	__u16 selector;
	__u8  type;
	__u8  present, dpl, db, s, l, g, avl;
	__u8  unusable;
	__u8  padding;
};

struct kvm_dtable {
	__u64 base;
	__u16 limit;
	__u16 padding[3];
};


/* for KVM_GET_SREGS and KVM_SET_SREGS */
struct kvm_sregs {
	/* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
	struct kvm_segment cs, ds, es, fs, gs, ss;
	struct kvm_segment tr, ldt;
	struct kvm_dtable gdt, idt;
	__u64 cr0, cr2, cr3, cr4, cr8;
	__u64 efer;
	__u64 apic_base;
	__u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
};

struct kvm_sregs2 {
	/* out (KVM_GET_SREGS2) / in (KVM_SET_SREGS2) */
	struct kvm_segment cs, ds, es, fs, gs, ss;
	struct kvm_segment tr, ldt;
	struct kvm_dtable gdt, idt;
	__u64 cr0, cr2, cr3, cr4, cr8;
	__u64 efer;
	__u64 apic_base;
	__u64 flags;
	__u64 pdptrs[4];
};
#define KVM_SREGS2_FLAGS_PDPTRS_VALID 1

/* for KVM_GET_FPU and KVM_SET_FPU */
struct kvm_fpu {
	__u8  fpr[8][16];
	__u16 fcw;
	__u16 fsw;
	__u8  ftwx;  /* in fxsave format */
	__u8  pad1;
	__u16 last_opcode;
	__u64 last_ip;
	__u64 last_dp;
	__u8  xmm[16][16];
	__u32 mxcsr;
	__u32 pad2;
};

struct kvm_msr_entry {
	__u32 index;
	__u32 reserved;
	__u64 data;
};

/* for KVM_GET_MSRS and KVM_SET_MSRS */
struct kvm_msrs {
	__u32 nmsrs; /* number of msrs in entries */
	__u32 pad;

	struct kvm_msr_entry entries[];
};

/* for KVM_GET_MSR_INDEX_LIST */
struct kvm_msr_list {
	__u32 nmsrs; /* number of msrs in entries */
	__u32 indices[];
};

/* Maximum size of any access bitmap in bytes */
#define KVM_MSR_FILTER_MAX_BITMAP_SIZE 0x600

/* for KVM_X86_SET_MSR_FILTER */
struct kvm_msr_filter_range {
#define KVM_MSR_FILTER_READ  (1 << 0)
#define KVM_MSR_FILTER_WRITE (1 << 1)
#define KVM_MSR_FILTER_RANGE_VALID_MASK (KVM_MSR_FILTER_READ | \
					 KVM_MSR_FILTER_WRITE)
	__u32 flags;
	__u32 nmsrs; /* number of msrs in bitmap */
	__u32 base;  /* MSR index the bitmap starts at */
	__u8 *bitmap; /* a 1 bit allows the operations in flags, 0 denies */
};

#define KVM_MSR_FILTER_MAX_RANGES 16
struct kvm_msr_filter {
#define KVM_MSR_FILTER_DEFAULT_ALLOW (0 << 0)
#define KVM_MSR_FILTER_DEFAULT_DENY  (1 << 0)
#define KVM_MSR_FILTER_VALID_MASK (KVM_MSR_FILTER_DEFAULT_DENY)
	__u32 flags;
	struct kvm_msr_filter_range ranges[KVM_MSR_FILTER_MAX_RANGES];
};

struct kvm_cpuid_entry {
	__u32 function;
	__u32 eax;
	__u32 ebx;
	__u32 ecx;
	__u32 edx;
	__u32 padding;
};

/* for KVM_SET_CPUID */
struct kvm_cpuid {
	__u32 nent;
	__u32 padding;
	struct kvm_cpuid_entry entries[];
};

struct kvm_cpuid_entry2 {
	__u32 function;
	__u32 index;
	__u32 flags;
	__u32 eax;
	__u32 ebx;
	__u32 ecx;
	__u32 edx;
	__u32 padding[3];
};

#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX		(1 << 0)
#define KVM_CPUID_FLAG_STATEFUL_FUNC		(1 << 1)
#define KVM_CPUID_FLAG_STATE_READ_NEXT		(1 << 2)

/* for KVM_SET_CPUID2 */
struct kvm_cpuid2 {
	__u32 nent;
	__u32 padding;
	struct kvm_cpuid_entry2 entries[];
};

/* for KVM_GET_PIT and KVM_SET_PIT */
struct kvm_pit_channel_state {
	__u32 count; /* can be 65536 */
	__u16 latched_count;
	__u8 count_latched;
	__u8 status_latched;
	__u8 status;
	__u8 read_state;
	__u8 write_state;
	__u8 write_latch;
	__u8 rw_mode;
	__u8 mode;
	__u8 bcd;
	__u8 gate;
	__s64 count_load_time;
};

struct kvm_debug_exit_arch {
	__u32 exception;
	__u32 pad;
	__u64 pc;
	__u64 dr6;
	__u64 dr7;
};

#define KVM_GUESTDBG_USE_SW_BP		0x00010000
#define KVM_GUESTDBG_USE_HW_BP		0x00020000
#define KVM_GUESTDBG_INJECT_DB		0x00040000
#define KVM_GUESTDBG_INJECT_BP		0x00080000
#define KVM_GUESTDBG_BLOCKIRQ		0x00100000

/* for KVM_SET_GUEST_DEBUG */
struct kvm_guest_debug_arch {
	__u64 debugreg[8];
};

struct kvm_pit_state {
	struct kvm_pit_channel_state channels[3];
};

#define KVM_PIT_FLAGS_HPET_LEGACY     0x00000001
#define KVM_PIT_FLAGS_SPEAKER_DATA_ON 0x00000002

struct kvm_pit_state2 {
	struct kvm_pit_channel_state channels[3];
	__u32 flags;
	__u32 reserved[9];
};

struct kvm_reinject_control {
	__u8 pit_reinject;
	__u8 reserved[31];
};

/* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
#define KVM_VCPUEVENT_VALID_NMI_PENDING	0x00000001
#define KVM_VCPUEVENT_VALID_SIPI_VECTOR	0x00000002
#define KVM_VCPUEVENT_VALID_SHADOW	0x00000004
#define KVM_VCPUEVENT_VALID_SMM		0x00000008
#define KVM_VCPUEVENT_VALID_PAYLOAD	0x00000010
#define KVM_VCPUEVENT_VALID_TRIPLE_FAULT	0x00000020

/* Interrupt shadow states */
#define KVM_X86_SHADOW_INT_MOV_SS	0x01
#define KVM_X86_SHADOW_INT_STI		0x02

/* for KVM_GET/SET_VCPU_EVENTS */
struct kvm_vcpu_events {
	struct {
		__u8 injected;
		__u8 nr;
		__u8 has_error_code;
		__u8 pending;
		__u32 error_code;
	} exception;
	struct {
		__u8 injected;
		__u8 nr;
		__u8 soft;
		__u8 shadow;
	} interrupt;
	struct {
		__u8 injected;
		__u8 pending;
		__u8 masked;
		__u8 pad;
	} nmi;
	__u32 sipi_vector;
	__u32 flags;
	struct {
		__u8 smm;
		__u8 pending;
		__u8 smm_inside_nmi;
		__u8 latched_init;
	} smi;
	struct {
		__u8 pending;
	} triple_fault;
	__u8 reserved[26];
	__u8 exception_has_payload;
	__u64 exception_payload;
};

/* for KVM_GET/SET_DEBUGREGS */
struct kvm_debugregs {
	__u64 db[4];
	__u64 dr6;
	__u64 dr7;
	__u64 flags;
	__u64 reserved[9];
};

/* for KVM_CAP_XSAVE and KVM_CAP_XSAVE2 */
struct kvm_xsave {
	/*
	 * KVM_GET_XSAVE2 and KVM_SET_XSAVE write and read as many bytes
	 * as are returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2)
	 * respectively, when invoked on the vm file descriptor.
	 *
	 * The size value returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2)
	 * will always be at least 4096. Currently, it is only greater
	 * than 4096 if a dynamic feature has been enabled with
	 * ``arch_prctl()``, but this may change in the future.
	 *
	 * The offsets of the state save areas in struct kvm_xsave follow
	 * the contents of CPUID leaf 0xD on the host.
	 */
	__u32 region[1024];
	__u32 extra[];
};

#define KVM_MAX_XCRS	16

struct kvm_xcr {
	__u32 xcr;
	__u32 reserved;
	__u64 value;
};

struct kvm_xcrs {
	__u32 nr_xcrs;
	__u32 flags;
	struct kvm_xcr xcrs[KVM_MAX_XCRS];
	__u64 padding[16];
};

#define KVM_SYNC_X86_REGS      (1UL << 0)
#define KVM_SYNC_X86_SREGS     (1UL << 1)
#define KVM_SYNC_X86_EVENTS    (1UL << 2)

#define KVM_SYNC_X86_VALID_FIELDS \
	(KVM_SYNC_X86_REGS| \
	 KVM_SYNC_X86_SREGS| \
	 KVM_SYNC_X86_EVENTS)

/* kvm_sync_regs struct included by kvm_run struct */
struct kvm_sync_regs {
	/* Members of this structure are potentially malicious.
	 * Care must be taken by code reading, esp. interpreting,
	 * data fields from them inside KVM to prevent TOCTOU and
	 * double-fetch types of vulnerabilities.
	 */
	struct kvm_regs regs;
	struct kvm_sregs sregs;
	struct kvm_vcpu_events events;
};

#define KVM_X86_QUIRK_LINT0_REENABLED		(1 << 0)
#define KVM_X86_QUIRK_CD_NW_CLEARED		(1 << 1)
#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE		(1 << 2)
#define KVM_X86_QUIRK_OUT_7E_INC_RIP		(1 << 3)
#define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT	(1 << 4)
#define KVM_X86_QUIRK_FIX_HYPERCALL_INSN	(1 << 5)
#define KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS	(1 << 6)

#define KVM_STATE_NESTED_FORMAT_VMX	0
#define KVM_STATE_NESTED_FORMAT_SVM	1

#define KVM_STATE_NESTED_GUEST_MODE	0x00000001
#define KVM_STATE_NESTED_RUN_PENDING	0x00000002
#define KVM_STATE_NESTED_EVMCS		0x00000004
#define KVM_STATE_NESTED_MTF_PENDING	0x00000008
#define KVM_STATE_NESTED_GIF_SET	0x00000100

#define KVM_STATE_NESTED_SMM_GUEST_MODE	0x00000001
#define KVM_STATE_NESTED_SMM_VMXON	0x00000002

#define KVM_STATE_NESTED_VMX_VMCS_SIZE	0x1000

#define KVM_STATE_NESTED_SVM_VMCB_SIZE	0x1000

#define KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE	0x00000001

/* attributes for system fd (group 0) */
#define KVM_X86_XCOMP_GUEST_SUPP	0

struct kvm_vmx_nested_state_data {
	__u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE];
	__u8 shadow_vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE];
};

struct kvm_vmx_nested_state_hdr {
	__u64 vmxon_pa;
	__u64 vmcs12_pa;

	struct {
		__u16 flags;
	} smm;

	__u16 pad;

	__u32 flags;
	__u64 preemption_timer_deadline;
};

struct kvm_svm_nested_state_data {
	/* Save area only used if KVM_STATE_NESTED_RUN_PENDING.  */
	__u8 vmcb12[KVM_STATE_NESTED_SVM_VMCB_SIZE];
};

struct kvm_svm_nested_state_hdr {
	__u64 vmcb_pa;
};

/* for KVM_CAP_NESTED_STATE */
struct kvm_nested_state {
	__u16 flags;
	__u16 format;
	__u32 size;

	union {
		struct kvm_vmx_nested_state_hdr vmx;
		struct kvm_svm_nested_state_hdr svm;

		/* Pad the header to 128 bytes.  */
		__u8 pad[120];
	} hdr;

	/*
	 * Define data region as 0 bytes to preserve backwards-compatability
	 * to old definition of kvm_nested_state in order to avoid changing
	 * KVM_{GET,PUT}_NESTED_STATE ioctl values.
	 */
	union {
		struct kvm_vmx_nested_state_data vmx[0];
		struct kvm_svm_nested_state_data svm[0];
	} data;
};

/* for KVM_CAP_PMU_EVENT_FILTER */
struct kvm_pmu_event_filter {
	__u32 action;
	__u32 nevents;
	__u32 fixed_counter_bitmap;
	__u32 flags;
	__u32 pad[4];
	__u64 events[];
};

#define KVM_PMU_EVENT_ALLOW 0
#define KVM_PMU_EVENT_DENY 1

/* for KVM_{GET,SET,HAS}_DEVICE_ATTR */
#define KVM_VCPU_TSC_CTRL 0 /* control group for the timestamp counter (TSC) */
#define   KVM_VCPU_TSC_OFFSET 0 /* attribute for the TSC offset */

#endif /* _ASM_X86_KVM_H */
Commit	Line	Data
dd873966	1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
51b24e34 JK	2	#ifndef _ASM_X86_KVM_H
	3	#define _ASM_X86_KVM_H
	4
	5	/*
	6	* KVM x86 specific structures and definitions
	7	*
	8	*/
	9
	10	#include <linux/types.h>
	11	#include <linux/ioctl.h>
	12
74c98e20 CH	13	#define KVM_PIO_PAGE_OFFSET 1
74c98e20 CH	14	#define KVM_COALESCED_MMIO_PAGE_OFFSET 2
b3c818a4	15	#define KVM_DIRTY_LOG_PAGE_OFFSET 64
74c98e20	16
716b8e4d AW	17	#define DE_VECTOR 0
	18	#define DB_VECTOR 1
	19	#define BP_VECTOR 3
	20	#define OF_VECTOR 4
	21	#define BR_VECTOR 5
	22	#define UD_VECTOR 6
	23	#define NM_VECTOR 7
	24	#define DF_VECTOR 8
	25	#define TS_VECTOR 10
	26	#define NP_VECTOR 11
	27	#define SS_VECTOR 12
	28	#define GP_VECTOR 13
	29	#define PF_VECTOR 14
	30	#define MF_VECTOR 16
a9fd1654	31	#define AC_VECTOR 17
716b8e4d	32	#define MC_VECTOR 18
a9fd1654 JF	33	#define XM_VECTOR 19
a9fd1654 JF	34	#define VE_VECTOR 20
716b8e4d	35
51b24e34 JK	36	/* Select x86 specific features in <linux/kvm.h> */
	37	#define __KVM_HAVE_PIT
	38	#define __KVM_HAVE_IOAPIC
651682dc	39	#define __KVM_HAVE_IRQ_LINE
51b24e34 JK	40	#define __KVM_HAVE_MSI
	41	#define __KVM_HAVE_USER_NMI
	42	#define __KVM_HAVE_GUEST_DEBUG
	43	#define __KVM_HAVE_MSIX
	44	#define __KVM_HAVE_MCE
	45	#define __KVM_HAVE_PIT_STATE2
	46	#define __KVM_HAVE_XEN_HVM
	47	#define __KVM_HAVE_VCPU_EVENTS
	48	#define __KVM_HAVE_DEBUGREGS
	49	#define __KVM_HAVE_XSAVE
	50	#define __KVM_HAVE_XCRS
716b8e4d	51	#define __KVM_HAVE_READONLY_MEM
51b24e34 JK	52
	53	/* Architectural interrupt line count. */
	54	#define KVM_NR_INTERRUPTS 256
	55
51b24e34 JK	56	/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
	57	struct kvm_pic_state {
	58	__u8 last_irr; /* edge detection */
	59	__u8 irr; /* interrupt request register */
	60	__u8 imr; /* interrupt mask register */
	61	__u8 isr; /* interrupt service register */
	62	__u8 priority_add; /* highest irq priority */
	63	__u8 irq_base;
	64	__u8 read_reg_select;
	65	__u8 poll;
	66	__u8 special_mask;
	67	__u8 init_state;
	68	__u8 auto_eoi;
	69	__u8 rotate_on_auto_eoi;
	70	__u8 special_fully_nested_mode;
	71	__u8 init4; /* true if 4 byte init */
	72	__u8 elcr; /* PIIX edge/trigger selection */
	73	__u8 elcr_mask;
	74	};
	75
	76	#define KVM_IOAPIC_NUM_PINS 24
	77	struct kvm_ioapic_state {
	78	__u64 base_address;
	79	__u32 ioregsel;
	80	__u32 id;
	81	__u32 irr;
	82	__u32 pad;
	83	union {
	84	__u64 bits;
	85	struct {
	86	__u8 vector;
	87	__u8 delivery_mode:3;
	88	__u8 dest_mode:1;
	89	__u8 delivery_status:1;
	90	__u8 polarity:1;
	91	__u8 remote_irr:1;
	92	__u8 trig_mode:1;
	93	__u8 mask:1;
	94	__u8 reserve:7;
	95	__u8 reserved[4];
	96	__u8 dest_id;
	97	} fields;
	98	} redirtbl[KVM_IOAPIC_NUM_PINS];
	99	};
	100
	101	#define KVM_IRQCHIP_PIC_MASTER 0
	102	#define KVM_IRQCHIP_PIC_SLAVE 1
	103	#define KVM_IRQCHIP_IOAPIC 2
	104	#define KVM_NR_IRQCHIPS 3
	105
24a31426	106	#define KVM_RUN_X86_SMM (1 << 0)
278f064e	107	#define KVM_RUN_X86_BUS_LOCK (1 << 1)
24a31426	108
51b24e34 JK	109	/* for KVM_GET_REGS and KVM_SET_REGS */
	110	struct kvm_regs {
	111	/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
	112	__u64 rax, rbx, rcx, rdx;
	113	__u64 rsi, rdi, rsp, rbp;
	114	__u64 r8, r9, r10, r11;
	115	__u64 r12, r13, r14, r15;
	116	__u64 rip, rflags;
	117	};
	118
	119	/* for KVM_GET_LAPIC and KVM_SET_LAPIC */
	120	#define KVM_APIC_REG_SIZE 0x400
	121	struct kvm_lapic_state {
	122	char regs[KVM_APIC_REG_SIZE];
	123	};
	124
	125	struct kvm_segment {
	126	__u64 base;
	127	__u32 limit;
	128	__u16 selector;
	129	__u8 type;
	130	__u8 present, dpl, db, s, l, g, avl;
	131	__u8 unusable;
	132	__u8 padding;
	133	};
	134
	135	struct kvm_dtable {
	136	__u64 base;
	137	__u16 limit;
	138	__u16 padding[3];
	139	};
	140
	141
	142	/* for KVM_GET_SREGS and KVM_SET_SREGS */
	143	struct kvm_sregs {
	144	/* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
	145	struct kvm_segment cs, ds, es, fs, gs, ss;
	146	struct kvm_segment tr, ldt;
	147	struct kvm_dtable gdt, idt;
	148	__u64 cr0, cr2, cr3, cr4, cr8;
	149	__u64 efer;
	150	__u64 apic_base;
b07d1c2f	151	__u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
51b24e34 JK	152	};
51b24e34 JK	153
327d4b7f BR	154	struct kvm_sregs2 {
	155	/* out (KVM_GET_SREGS2) / in (KVM_SET_SREGS2) */
	156	struct kvm_segment cs, ds, es, fs, gs, ss;
	157	struct kvm_segment tr, ldt;
	158	struct kvm_dtable gdt, idt;
	159	__u64 cr0, cr2, cr3, cr4, cr8;
	160	__u64 efer;
	161	__u64 apic_base;
	162	__u64 flags;
	163	__u64 pdptrs[4];
	164	};
	165	#define KVM_SREGS2_FLAGS_PDPTRS_VALID 1
	166
51b24e34 JK	167	/* for KVM_GET_FPU and KVM_SET_FPU */
	168	struct kvm_fpu {
	169	__u8 fpr[8][16];
	170	__u16 fcw;
	171	__u16 fsw;
	172	__u8 ftwx; /* in fxsave format */
	173	__u8 pad1;
	174	__u16 last_opcode;
	175	__u64 last_ip;
	176	__u64 last_dp;
	177	__u8 xmm[16][16];
	178	__u32 mxcsr;
	179	__u32 pad2;
	180	};
	181
	182	struct kvm_msr_entry {
	183	__u32 index;
	184	__u32 reserved;
	185	__u64 data;
	186	};
	187
	188	/* for KVM_GET_MSRS and KVM_SET_MSRS */
	189	struct kvm_msrs {
	190	__u32 nmsrs; /* number of msrs in entries */
	191	__u32 pad;
	192
d525f73f	193	struct kvm_msr_entry entries[];
51b24e34 JK	194	};
	195
	196	/* for KVM_GET_MSR_INDEX_LIST */
	197	struct kvm_msr_list {
	198	__u32 nmsrs; /* number of msrs in entries */
d525f73f	199	__u32 indices[];
51b24e34 JK	200	};
51b24e34 JK	201
53ba2eee MR	202	/* Maximum size of any access bitmap in bytes */
	203	#define KVM_MSR_FILTER_MAX_BITMAP_SIZE 0x600
	204
	205	/* for KVM_X86_SET_MSR_FILTER */
	206	struct kvm_msr_filter_range {
	207	#define KVM_MSR_FILTER_READ (1 << 0)
	208	#define KVM_MSR_FILTER_WRITE (1 << 1)
93d7620c AH	209	#define KVM_MSR_FILTER_RANGE_VALID_MASK (KVM_MSR_FILTER_READ \| \
93d7620c AH	210	KVM_MSR_FILTER_WRITE)
53ba2eee MR	211	__u32 flags;
	212	__u32 nmsrs; /* number of msrs in bitmap */
	213	__u32 base; /* MSR index the bitmap starts at */
	214	__u8 bitmap; / a 1 bit allows the operations in flags, 0 denies */
	215	};
	216
	217	#define KVM_MSR_FILTER_MAX_RANGES 16
	218	struct kvm_msr_filter {
	219	#define KVM_MSR_FILTER_DEFAULT_ALLOW (0 << 0)
	220	#define KVM_MSR_FILTER_DEFAULT_DENY (1 << 0)
93d7620c	221	#define KVM_MSR_FILTER_VALID_MASK (KVM_MSR_FILTER_DEFAULT_DENY)
53ba2eee MR	222	__u32 flags;
	223	struct kvm_msr_filter_range ranges[KVM_MSR_FILTER_MAX_RANGES];
	224	};
51b24e34 JK	225
	226	struct kvm_cpuid_entry {
	227	__u32 function;
	228	__u32 eax;
	229	__u32 ebx;
	230	__u32 ecx;
	231	__u32 edx;
	232	__u32 padding;
	233	};
	234
	235	/* for KVM_SET_CPUID */
	236	struct kvm_cpuid {
	237	__u32 nent;
	238	__u32 padding;
d525f73f	239	struct kvm_cpuid_entry entries[];
51b24e34 JK	240	};
	241
	242	struct kvm_cpuid_entry2 {
	243	__u32 function;
	244	__u32 index;
	245	__u32 flags;
	246	__u32 eax;
	247	__u32 ebx;
	248	__u32 ecx;
	249	__u32 edx;
	250	__u32 padding[3];
	251	};
	252
ff804f15 CH	253	#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX (1 << 0)
	254	#define KVM_CPUID_FLAG_STATEFUL_FUNC (1 << 1)
	255	#define KVM_CPUID_FLAG_STATE_READ_NEXT (1 << 2)
51b24e34 JK	256
	257	/* for KVM_SET_CPUID2 */
	258	struct kvm_cpuid2 {
	259	__u32 nent;
	260	__u32 padding;
d525f73f	261	struct kvm_cpuid_entry2 entries[];
51b24e34 JK	262	};
	263
	264	/* for KVM_GET_PIT and KVM_SET_PIT */
	265	struct kvm_pit_channel_state {
	266	__u32 count; /* can be 65536 */
	267	__u16 latched_count;
	268	__u8 count_latched;
	269	__u8 status_latched;
	270	__u8 status;
	271	__u8 read_state;
	272	__u8 write_state;
	273	__u8 write_latch;
	274	__u8 rw_mode;
	275	__u8 mode;
	276	__u8 bcd;
	277	__u8 gate;
	278	__s64 count_load_time;
	279	};
	280
	281	struct kvm_debug_exit_arch {
	282	__u32 exception;
	283	__u32 pad;
	284	__u64 pc;
	285	__u64 dr6;
	286	__u64 dr7;
	287	};
	288
	289	#define KVM_GUESTDBG_USE_SW_BP 0x00010000
	290	#define KVM_GUESTDBG_USE_HW_BP 0x00020000
	291	#define KVM_GUESTDBG_INJECT_DB 0x00040000
	292	#define KVM_GUESTDBG_INJECT_BP 0x00080000
43709a0c	293	#define KVM_GUESTDBG_BLOCKIRQ 0x00100000
51b24e34 JK	294
	295	/* for KVM_SET_GUEST_DEBUG */
	296	struct kvm_guest_debug_arch {
	297	__u64 debugreg[8];
	298	};
	299
	300	struct kvm_pit_state {
	301	struct kvm_pit_channel_state channels[3];
	302	};
	303
d525f73f CQ	304	#define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001
d525f73f CQ	305	#define KVM_PIT_FLAGS_SPEAKER_DATA_ON 0x00000002
51b24e34 JK	306
	307	struct kvm_pit_state2 {
	308	struct kvm_pit_channel_state channels[3];
	309	__u32 flags;
	310	__u32 reserved[9];
	311	};
	312
	313	struct kvm_reinject_control {
	314	__u8 pit_reinject;
	315	__u8 reserved[31];
	316	};
	317
	318	/* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
	319	#define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
	320	#define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
	321	#define KVM_VCPUEVENT_VALID_SHADOW 0x00000004
24a31426	322	#define KVM_VCPUEVENT_VALID_SMM 0x00000008
966f2ec3	323	#define KVM_VCPUEVENT_VALID_PAYLOAD 0x00000010
d525f73f	324	#define KVM_VCPUEVENT_VALID_TRIPLE_FAULT 0x00000020
51b24e34 JK	325
	326	/* Interrupt shadow states */
	327	#define KVM_X86_SHADOW_INT_MOV_SS 0x01
	328	#define KVM_X86_SHADOW_INT_STI 0x02
	329
	330	/* for KVM_GET/SET_VCPU_EVENTS */
	331	struct kvm_vcpu_events {
	332	struct {
	333	__u8 injected;
	334	__u8 nr;
	335	__u8 has_error_code;
966f2ec3	336	__u8 pending;
51b24e34 JK	337	__u32 error_code;
	338	} exception;
	339	struct {
	340	__u8 injected;
	341	__u8 nr;
	342	__u8 soft;
	343	__u8 shadow;
	344	} interrupt;
	345	struct {
	346	__u8 injected;
	347	__u8 pending;
	348	__u8 masked;
	349	__u8 pad;
	350	} nmi;
	351	__u32 sipi_vector;
	352	__u32 flags;
24a31426 PB	353	struct {
	354	__u8 smm;
	355	__u8 pending;
	356	__u8 smm_inside_nmi;
	357	__u8 latched_init;
	358	} smi;
d525f73f CQ	359	struct {
	360	__u8 pending;
	361	} triple_fault;
	362	__u8 reserved[26];
966f2ec3 PB	363	__u8 exception_has_payload;
966f2ec3 PB	364	__u64 exception_payload;
51b24e34 JK	365	};
	366
	367	/* for KVM_GET/SET_DEBUGREGS */
	368	struct kvm_debugregs {
	369	__u64 db[4];
	370	__u64 dr6;
	371	__u64 dr7;
	372	__u64 flags;
	373	__u64 reserved[9];
	374	};
	375
ef17dd6a	376	/* for KVM_CAP_XSAVE and KVM_CAP_XSAVE2 */
51b24e34	377	struct kvm_xsave {
ef17dd6a VG	378	/*
	379	* KVM_GET_XSAVE2 and KVM_SET_XSAVE write and read as many bytes
	380	* as are returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2)
	381	* respectively, when invoked on the vm file descriptor.
	382	*
	383	* The size value returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2)
	384	* will always be at least 4096. Currently, it is only greater
	385	* than 4096 if a dynamic feature has been enabled with
	386	* ``arch_prctl()``, but this may change in the future.
	387	*
	388	* The offsets of the state save areas in struct kvm_xsave follow
	389	* the contents of CPUID leaf 0xD on the host.
	390	*/
51b24e34	391	__u32 region[1024];
d525f73f	392	__u32 extra[];
51b24e34 JK	393	};
	394
	395	#define KVM_MAX_XCRS 16
	396
	397	struct kvm_xcr {
	398	__u32 xcr;
	399	__u32 reserved;
	400	__u64 value;
	401	};
	402
	403	struct kvm_xcrs {
	404	__u32 nr_xcrs;
	405	__u32 flags;
	406	struct kvm_xcr xcrs[KVM_MAX_XCRS];
	407	__u64 padding[16];
	408	};
	409
65a6d8dd PM	410	#define KVM_SYNC_X86_REGS (1UL << 0)
	411	#define KVM_SYNC_X86_SREGS (1UL << 1)
	412	#define KVM_SYNC_X86_EVENTS (1UL << 2)
	413
	414	#define KVM_SYNC_X86_VALID_FIELDS \
	415	(KVM_SYNC_X86_REGS\| \
	416	KVM_SYNC_X86_SREGS\| \
	417	KVM_SYNC_X86_EVENTS)
	418
	419	/* kvm_sync_regs struct included by kvm_run struct */
1529ae1b	420	struct kvm_sync_regs {
65a6d8dd PM	421	/* Members of this structure are potentially malicious.
	422	* Care must be taken by code reading, esp. interpreting,
	423	* data fields from them inside KVM to prevent TOCTOU and
	424	* double-fetch types of vulnerabilities.
	425	*/
	426	struct kvm_regs regs;
	427	struct kvm_sregs sregs;
	428	struct kvm_vcpu_events events;
1529ae1b AG	429	};
1529ae1b AG	430
d525f73f CQ	431	#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0)
	432	#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1)
	433	#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2)
	434	#define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3)
	435	#define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4)
	436	#define KVM_X86_QUIRK_FIX_HYPERCALL_INSN (1 << 5)
	437	#define KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS (1 << 6)
24a31426	438
1d33bea4	439	#define KVM_STATE_NESTED_FORMAT_VMX 0
f76b348e	440	#define KVM_STATE_NESTED_FORMAT_SVM 1
1d33bea4	441
d36f7de8 CH	442	#define KVM_STATE_NESTED_GUEST_MODE 0x00000001
d36f7de8 CH	443	#define KVM_STATE_NESTED_RUN_PENDING 0x00000002
966f2ec3	444	#define KVM_STATE_NESTED_EVMCS 0x00000004
dc6f8d45	445	#define KVM_STATE_NESTED_MTF_PENDING 0x00000008
f76b348e	446	#define KVM_STATE_NESTED_GIF_SET 0x00000100
d36f7de8 CH	447
	448	#define KVM_STATE_NESTED_SMM_GUEST_MODE 0x00000001
	449	#define KVM_STATE_NESTED_SMM_VMXON 0x00000002
	450
f363d039 EA	451	#define KVM_STATE_NESTED_VMX_VMCS_SIZE 0x1000
f363d039 EA	452
f76b348e CH	453	#define KVM_STATE_NESTED_SVM_VMCB_SIZE 0x1000
	454
	455	#define KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE 0x00000001
	456
1ea5208f PB	457	/* attributes for system fd (group 0) */
	458	#define KVM_X86_XCOMP_GUEST_SUPP 0
	459
1d33bea4 LA	460	struct kvm_vmx_nested_state_data {
	461	__u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE];
	462	__u8 shadow_vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE];
	463	};
	464
	465	struct kvm_vmx_nested_state_hdr {
d36f7de8	466	__u64 vmxon_pa;
1d33bea4	467	__u64 vmcs12_pa;
d36f7de8 CH	468
	469	struct {
	470	__u16 flags;
	471	} smm;
56908dc5	472
278f064e EH	473	__u16 pad;
278f064e EH	474
56908dc5 PB	475	__u32 flags;
56908dc5 PB	476	__u64 preemption_timer_deadline;
d36f7de8 CH	477	};
d36f7de8 CH	478
f76b348e CH	479	struct kvm_svm_nested_state_data {
	480	/* Save area only used if KVM_STATE_NESTED_RUN_PENDING. */
	481	__u8 vmcb12[KVM_STATE_NESTED_SVM_VMCB_SIZE];
	482	};
	483
	484	struct kvm_svm_nested_state_hdr {
	485	__u64 vmcb_pa;
	486	};
	487
d36f7de8 CH	488	/* for KVM_CAP_NESTED_STATE */
d36f7de8 CH	489	struct kvm_nested_state {
d36f7de8	490	__u16 flags;
d36f7de8	491	__u16 format;
d36f7de8 CH	492	__u32 size;
	493
	494	union {
1d33bea4	495	struct kvm_vmx_nested_state_hdr vmx;
f76b348e	496	struct kvm_svm_nested_state_hdr svm;
d36f7de8 CH	497
	498	/* Pad the header to 128 bytes. */
	499	__u8 pad[120];
1d33bea4	500	} hdr;
d36f7de8	501
1d33bea4 LA	502	/*
	503	* Define data region as 0 bytes to preserve backwards-compatability
	504	* to old definition of kvm_nested_state in order to avoid changing
	505	* KVM_{GET,PUT}_NESTED_STATE ioctl values.
	506	*/
	507	union {
	508	struct kvm_vmx_nested_state_data vmx[0];
f76b348e	509	struct kvm_svm_nested_state_data svm[0];
1d33bea4	510	} data;
d36f7de8 CH	511	};
d36f7de8 CH	512
f363d039 EA	513	/* for KVM_CAP_PMU_EVENT_FILTER */
	514	struct kvm_pmu_event_filter {
	515	__u32 action;
	516	__u32 nevents;
	517	__u32 fixed_counter_bitmap;
	518	__u32 flags;
	519	__u32 pad[4];
d525f73f	520	__u64 events[];
f363d039 EA	521	};
	522
	523	#define KVM_PMU_EVENT_ALLOW 0
	524	#define KVM_PMU_EVENT_DENY 1
	525
43709a0c PB	526	/* for KVM_{GET,SET,HAS}_DEVICE_ATTR */
	527	#define KVM_VCPU_TSC_CTRL 0 /* control group for the timestamp counter (TSC) */
	528	#define KVM_VCPU_TSC_OFFSET 0 /* attribute for the TSC offset */
	529
51b24e34	530	#endif /* _ASM_X86_KVM_H */