[thirdparty/qemu.git] / linux-headers / asm-x86 / kvm.h

/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef _ASM_X86_KVM_H
#define _ASM_X86_KVM_H

/*
 * KVM x86 specific structures and definitions
 *
 */

#include <linux/types.h>
#include <linux/ioctl.h>
#include <linux/stddef.h>

#define KVM_PIO_PAGE_OFFSET 1
#define KVM_COALESCED_MMIO_PAGE_OFFSET 2
#define KVM_DIRTY_LOG_PAGE_OFFSET 64

#define DE_VECTOR 0
#define DB_VECTOR 1
#define BP_VECTOR 3
#define OF_VECTOR 4
#define BR_VECTOR 5
#define UD_VECTOR 6
#define NM_VECTOR 7
#define DF_VECTOR 8
#define TS_VECTOR 10
#define NP_VECTOR 11
#define SS_VECTOR 12
#define GP_VECTOR 13
#define PF_VECTOR 14
#define MF_VECTOR 16
#define AC_VECTOR 17
#define MC_VECTOR 18
#define XM_VECTOR 19
#define VE_VECTOR 20

/* Select x86 specific features in <linux/kvm.h> */
#define __KVM_HAVE_PIT
#define __KVM_HAVE_IOAPIC
#define __KVM_HAVE_IRQ_LINE
#define __KVM_HAVE_MSI
#define __KVM_HAVE_USER_NMI
#define __KVM_HAVE_GUEST_DEBUG
#define __KVM_HAVE_MSIX
#define __KVM_HAVE_MCE
#define __KVM_HAVE_PIT_STATE2
#define __KVM_HAVE_XEN_HVM
#define __KVM_HAVE_VCPU_EVENTS
#define __KVM_HAVE_DEBUGREGS
#define __KVM_HAVE_XSAVE
#define __KVM_HAVE_XCRS
#define __KVM_HAVE_READONLY_MEM

/* Architectural interrupt line count. */
#define KVM_NR_INTERRUPTS 256

/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
struct kvm_pic_state {
	__u8 last_irr;	/* edge detection */
	__u8 irr;		/* interrupt request register */
	__u8 imr;		/* interrupt mask register */
	__u8 isr;		/* interrupt service register */
	__u8 priority_add;	/* highest irq priority */
	__u8 irq_base;
	__u8 read_reg_select;
	__u8 poll;
	__u8 special_mask;
	__u8 init_state;
	__u8 auto_eoi;
	__u8 rotate_on_auto_eoi;
	__u8 special_fully_nested_mode;
	__u8 init4;		/* true if 4 byte init */
	__u8 elcr;		/* PIIX edge/trigger selection */
	__u8 elcr_mask;
};

#define KVM_IOAPIC_NUM_PINS  24
struct kvm_ioapic_state {
	__u64 base_address;
	__u32 ioregsel;
	__u32 id;
	__u32 irr;
	__u32 pad;
	union {
		__u64 bits;
		struct {
			__u8 vector;
			__u8 delivery_mode:3;
			__u8 dest_mode:1;
			__u8 delivery_status:1;
			__u8 polarity:1;
			__u8 remote_irr:1;
			__u8 trig_mode:1;
			__u8 mask:1;
			__u8 reserve:7;
			__u8 reserved[4];
			__u8 dest_id;
		} fields;
	} redirtbl[KVM_IOAPIC_NUM_PINS];
};

#define KVM_IRQCHIP_PIC_MASTER   0
#define KVM_IRQCHIP_PIC_SLAVE    1
#define KVM_IRQCHIP_IOAPIC       2
#define KVM_NR_IRQCHIPS          3

#define KVM_RUN_X86_SMM		 (1 << 0)
#define KVM_RUN_X86_BUS_LOCK     (1 << 1)

/* for KVM_GET_REGS and KVM_SET_REGS */
struct kvm_regs {
	/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
	__u64 rax, rbx, rcx, rdx;
	__u64 rsi, rdi, rsp, rbp;
	__u64 r8,  r9,  r10, r11;
	__u64 r12, r13, r14, r15;
	__u64 rip, rflags;
};

/* for KVM_GET_LAPIC and KVM_SET_LAPIC */
#define KVM_APIC_REG_SIZE 0x400
struct kvm_lapic_state {
	char regs[KVM_APIC_REG_SIZE];
};

struct kvm_segment {
	__u64 base;
	__u32 limit;
	__u16 selector;
	__u8  type;
	__u8  present, dpl, db, s, l, g, avl;
	__u8  unusable;
	__u8  padding;
};

struct kvm_dtable {
	__u64 base;
	__u16 limit;
	__u16 padding[3];
};


/* for KVM_GET_SREGS and KVM_SET_SREGS */
struct kvm_sregs {
	/* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
	struct kvm_segment cs, ds, es, fs, gs, ss;
	struct kvm_segment tr, ldt;
	struct kvm_dtable gdt, idt;
	__u64 cr0, cr2, cr3, cr4, cr8;
	__u64 efer;
	__u64 apic_base;
	__u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
};

struct kvm_sregs2 {
	/* out (KVM_GET_SREGS2) / in (KVM_SET_SREGS2) */
	struct kvm_segment cs, ds, es, fs, gs, ss;
	struct kvm_segment tr, ldt;
	struct kvm_dtable gdt, idt;
	__u64 cr0, cr2, cr3, cr4, cr8;
	__u64 efer;
	__u64 apic_base;
	__u64 flags;
	__u64 pdptrs[4];
};
#define KVM_SREGS2_FLAGS_PDPTRS_VALID 1

/* for KVM_GET_FPU and KVM_SET_FPU */
struct kvm_fpu {
	__u8  fpr[8][16];
	__u16 fcw;
	__u16 fsw;
	__u8  ftwx;  /* in fxsave format */
	__u8  pad1;
	__u16 last_opcode;
	__u64 last_ip;
	__u64 last_dp;
	__u8  xmm[16][16];
	__u32 mxcsr;
	__u32 pad2;
};

struct kvm_msr_entry {
	__u32 index;
	__u32 reserved;
	__u64 data;
};

/* for KVM_GET_MSRS and KVM_SET_MSRS */
struct kvm_msrs {
	__u32 nmsrs; /* number of msrs in entries */
	__u32 pad;

	struct kvm_msr_entry entries[];
};

/* for KVM_GET_MSR_INDEX_LIST */
struct kvm_msr_list {
	__u32 nmsrs; /* number of msrs in entries */
	__u32 indices[];
};

/* Maximum size of any access bitmap in bytes */
#define KVM_MSR_FILTER_MAX_BITMAP_SIZE 0x600

/* for KVM_X86_SET_MSR_FILTER */
struct kvm_msr_filter_range {
#define KVM_MSR_FILTER_READ  (1 << 0)
#define KVM_MSR_FILTER_WRITE (1 << 1)
#define KVM_MSR_FILTER_RANGE_VALID_MASK (KVM_MSR_FILTER_READ | \
					 KVM_MSR_FILTER_WRITE)
	__u32 flags;
	__u32 nmsrs; /* number of msrs in bitmap */
	__u32 base;  /* MSR index the bitmap starts at */
	__u8 *bitmap; /* a 1 bit allows the operations in flags, 0 denies */
};

#define KVM_MSR_FILTER_MAX_RANGES 16
struct kvm_msr_filter {
#define KVM_MSR_FILTER_DEFAULT_ALLOW (0 << 0)
#define KVM_MSR_FILTER_DEFAULT_DENY  (1 << 0)
#define KVM_MSR_FILTER_VALID_MASK (KVM_MSR_FILTER_DEFAULT_DENY)
	__u32 flags;
	struct kvm_msr_filter_range ranges[KVM_MSR_FILTER_MAX_RANGES];
};

struct kvm_cpuid_entry {
	__u32 function;
	__u32 eax;
	__u32 ebx;
	__u32 ecx;
	__u32 edx;
	__u32 padding;
};

/* for KVM_SET_CPUID */
struct kvm_cpuid {
	__u32 nent;
	__u32 padding;
	struct kvm_cpuid_entry entries[];
};

struct kvm_cpuid_entry2 {
	__u32 function;
	__u32 index;
	__u32 flags;
	__u32 eax;
	__u32 ebx;
	__u32 ecx;
	__u32 edx;
	__u32 padding[3];
};

#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX		(1 << 0)
#define KVM_CPUID_FLAG_STATEFUL_FUNC		(1 << 1)
#define KVM_CPUID_FLAG_STATE_READ_NEXT		(1 << 2)

/* for KVM_SET_CPUID2 */
struct kvm_cpuid2 {
	__u32 nent;
	__u32 padding;
	struct kvm_cpuid_entry2 entries[];
};

/* for KVM_GET_PIT and KVM_SET_PIT */
struct kvm_pit_channel_state {
	__u32 count; /* can be 65536 */
	__u16 latched_count;
	__u8 count_latched;
	__u8 status_latched;
	__u8 status;
	__u8 read_state;
	__u8 write_state;
	__u8 write_latch;
	__u8 rw_mode;
	__u8 mode;
	__u8 bcd;
	__u8 gate;
	__s64 count_load_time;
};

struct kvm_debug_exit_arch {
	__u32 exception;
	__u32 pad;
	__u64 pc;
	__u64 dr6;
	__u64 dr7;
};

#define KVM_GUESTDBG_USE_SW_BP		0x00010000
#define KVM_GUESTDBG_USE_HW_BP		0x00020000
#define KVM_GUESTDBG_INJECT_DB		0x00040000
#define KVM_GUESTDBG_INJECT_BP		0x00080000
#define KVM_GUESTDBG_BLOCKIRQ		0x00100000

/* for KVM_SET_GUEST_DEBUG */
struct kvm_guest_debug_arch {
	__u64 debugreg[8];
};

struct kvm_pit_state {
	struct kvm_pit_channel_state channels[3];
};

#define KVM_PIT_FLAGS_HPET_LEGACY     0x00000001
#define KVM_PIT_FLAGS_SPEAKER_DATA_ON 0x00000002

struct kvm_pit_state2 {
	struct kvm_pit_channel_state channels[3];
	__u32 flags;
	__u32 reserved[9];
};

struct kvm_reinject_control {
	__u8 pit_reinject;
	__u8 reserved[31];
};

/* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
#define KVM_VCPUEVENT_VALID_NMI_PENDING	0x00000001
#define KVM_VCPUEVENT_VALID_SIPI_VECTOR	0x00000002
#define KVM_VCPUEVENT_VALID_SHADOW	0x00000004
#define KVM_VCPUEVENT_VALID_SMM		0x00000008
#define KVM_VCPUEVENT_VALID_PAYLOAD	0x00000010
#define KVM_VCPUEVENT_VALID_TRIPLE_FAULT	0x00000020

/* Interrupt shadow states */
#define KVM_X86_SHADOW_INT_MOV_SS	0x01
#define KVM_X86_SHADOW_INT_STI		0x02

/* for KVM_GET/SET_VCPU_EVENTS */
struct kvm_vcpu_events {
	struct {
		__u8 injected;
		__u8 nr;
		__u8 has_error_code;
		__u8 pending;
		__u32 error_code;
	} exception;
	struct {
		__u8 injected;
		__u8 nr;
		__u8 soft;
		__u8 shadow;
	} interrupt;
	struct {
		__u8 injected;
		__u8 pending;
		__u8 masked;
		__u8 pad;
	} nmi;
	__u32 sipi_vector;
	__u32 flags;
	struct {
		__u8 smm;
		__u8 pending;
		__u8 smm_inside_nmi;
		__u8 latched_init;
	} smi;
	struct {
		__u8 pending;
	} triple_fault;
	__u8 reserved[26];
	__u8 exception_has_payload;
	__u64 exception_payload;
};

/* for KVM_GET/SET_DEBUGREGS */
struct kvm_debugregs {
	__u64 db[4];
	__u64 dr6;
	__u64 dr7;
	__u64 flags;
	__u64 reserved[9];
};

/* for KVM_CAP_XSAVE and KVM_CAP_XSAVE2 */
struct kvm_xsave {
	/*
	 * KVM_GET_XSAVE2 and KVM_SET_XSAVE write and read as many bytes
	 * as are returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2)
	 * respectively, when invoked on the vm file descriptor.
	 *
	 * The size value returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2)
	 * will always be at least 4096. Currently, it is only greater
	 * than 4096 if a dynamic feature has been enabled with
	 * ``arch_prctl()``, but this may change in the future.
	 *
	 * The offsets of the state save areas in struct kvm_xsave follow
	 * the contents of CPUID leaf 0xD on the host.
	 */
	__u32 region[1024];
	__u32 extra[];
};

#define KVM_MAX_XCRS	16

struct kvm_xcr {
	__u32 xcr;
	__u32 reserved;
	__u64 value;
};

struct kvm_xcrs {
	__u32 nr_xcrs;
	__u32 flags;
	struct kvm_xcr xcrs[KVM_MAX_XCRS];
	__u64 padding[16];
};

#define KVM_SYNC_X86_REGS      (1UL << 0)
#define KVM_SYNC_X86_SREGS     (1UL << 1)
#define KVM_SYNC_X86_EVENTS    (1UL << 2)

#define KVM_SYNC_X86_VALID_FIELDS \
	(KVM_SYNC_X86_REGS| \
	 KVM_SYNC_X86_SREGS| \
	 KVM_SYNC_X86_EVENTS)

/* kvm_sync_regs struct included by kvm_run struct */
struct kvm_sync_regs {
	/* Members of this structure are potentially malicious.
	 * Care must be taken by code reading, esp. interpreting,
	 * data fields from them inside KVM to prevent TOCTOU and
	 * double-fetch types of vulnerabilities.
	 */
	struct kvm_regs regs;
	struct kvm_sregs sregs;
	struct kvm_vcpu_events events;
};

#define KVM_X86_QUIRK_LINT0_REENABLED		(1 << 0)
#define KVM_X86_QUIRK_CD_NW_CLEARED		(1 << 1)
#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE		(1 << 2)
#define KVM_X86_QUIRK_OUT_7E_INC_RIP		(1 << 3)
#define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT	(1 << 4)
#define KVM_X86_QUIRK_FIX_HYPERCALL_INSN	(1 << 5)
#define KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS	(1 << 6)

#define KVM_STATE_NESTED_FORMAT_VMX	0
#define KVM_STATE_NESTED_FORMAT_SVM	1

#define KVM_STATE_NESTED_GUEST_MODE	0x00000001
#define KVM_STATE_NESTED_RUN_PENDING	0x00000002
#define KVM_STATE_NESTED_EVMCS		0x00000004
#define KVM_STATE_NESTED_MTF_PENDING	0x00000008
#define KVM_STATE_NESTED_GIF_SET	0x00000100

#define KVM_STATE_NESTED_SMM_GUEST_MODE	0x00000001
#define KVM_STATE_NESTED_SMM_VMXON	0x00000002

#define KVM_STATE_NESTED_VMX_VMCS_SIZE	0x1000

#define KVM_STATE_NESTED_SVM_VMCB_SIZE	0x1000

#define KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE	0x00000001

/* attributes for system fd (group 0) */
#define KVM_X86_XCOMP_GUEST_SUPP	0

struct kvm_vmx_nested_state_data {
	__u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE];
	__u8 shadow_vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE];
};

struct kvm_vmx_nested_state_hdr {
	__u64 vmxon_pa;
	__u64 vmcs12_pa;

	struct {
		__u16 flags;
	} smm;

	__u16 pad;

	__u32 flags;
	__u64 preemption_timer_deadline;
};

struct kvm_svm_nested_state_data {
	/* Save area only used if KVM_STATE_NESTED_RUN_PENDING.  */
	__u8 vmcb12[KVM_STATE_NESTED_SVM_VMCB_SIZE];
};

struct kvm_svm_nested_state_hdr {
	__u64 vmcb_pa;
};

/* for KVM_CAP_NESTED_STATE */
struct kvm_nested_state {
	__u16 flags;
	__u16 format;
	__u32 size;

	union {
		struct kvm_vmx_nested_state_hdr vmx;
		struct kvm_svm_nested_state_hdr svm;

		/* Pad the header to 128 bytes.  */
		__u8 pad[120];
	} hdr;

	/*
	 * Define data region as 0 bytes to preserve backwards-compatability
	 * to old definition of kvm_nested_state in order to avoid changing
	 * KVM_{GET,PUT}_NESTED_STATE ioctl values.
	 */
	union {
		__DECLARE_FLEX_ARRAY(struct kvm_vmx_nested_state_data, vmx);
		__DECLARE_FLEX_ARRAY(struct kvm_svm_nested_state_data, svm);
	} data;
};

/* for KVM_CAP_PMU_EVENT_FILTER */
struct kvm_pmu_event_filter {
	__u32 action;
	__u32 nevents;
	__u32 fixed_counter_bitmap;
	__u32 flags;
	__u32 pad[4];
	__u64 events[];
};

#define KVM_PMU_EVENT_ALLOW 0
#define KVM_PMU_EVENT_DENY 1

#define KVM_PMU_EVENT_FLAG_MASKED_EVENTS BIT(0)
#define KVM_PMU_EVENT_FLAGS_VALID_MASK (KVM_PMU_EVENT_FLAG_MASKED_EVENTS)

/*
 * Masked event layout.
 * Bits   Description
 * ----   -----------
 * 7:0    event select (low bits)
 * 15:8   umask match
 * 31:16  unused
 * 35:32  event select (high bits)
 * 36:54  unused
 * 55     exclude bit
 * 63:56  umask mask
 */

#define KVM_PMU_ENCODE_MASKED_ENTRY(event_select, mask, match, exclude) \
	(((event_select) & 0xFFULL) | (((event_select) & 0XF00ULL) << 24) | \
	(((mask) & 0xFFULL) << 56) | \
	(((match) & 0xFFULL) << 8) | \
	((__u64)(!!(exclude)) << 55))

#define KVM_PMU_MASKED_ENTRY_EVENT_SELECT \
	(GENMASK_ULL(7, 0) | GENMASK_ULL(35, 32))
#define KVM_PMU_MASKED_ENTRY_UMASK_MASK		(GENMASK_ULL(63, 56))
#define KVM_PMU_MASKED_ENTRY_UMASK_MATCH	(GENMASK_ULL(15, 8))
#define KVM_PMU_MASKED_ENTRY_EXCLUDE		(BIT_ULL(55))
#define KVM_PMU_MASKED_ENTRY_UMASK_MASK_SHIFT	(56)

/* for KVM_{GET,SET,HAS}_DEVICE_ATTR */
#define KVM_VCPU_TSC_CTRL 0 /* control group for the timestamp counter (TSC) */
#define   KVM_VCPU_TSC_OFFSET 0 /* attribute for the TSC offset */

#endif /* _ASM_X86_KVM_H */
Commit	Line	Data
dd873966	1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
51b24e34 JK	2	#ifndef _ASM_X86_KVM_H
	3	#define _ASM_X86_KVM_H
	4
	5	/*
	6	* KVM x86 specific structures and definitions
	7	*
	8	*/
	9
	10	#include <linux/types.h>
	11	#include <linux/ioctl.h>
c5c0fdbe	12	#include <linux/stddef.h>
51b24e34	13
74c98e20 CH	14	#define KVM_PIO_PAGE_OFFSET 1
74c98e20 CH	15	#define KVM_COALESCED_MMIO_PAGE_OFFSET 2
b3c818a4	16	#define KVM_DIRTY_LOG_PAGE_OFFSET 64
74c98e20	17
716b8e4d AW	18	#define DE_VECTOR 0
	19	#define DB_VECTOR 1
	20	#define BP_VECTOR 3
	21	#define OF_VECTOR 4
	22	#define BR_VECTOR 5
	23	#define UD_VECTOR 6
	24	#define NM_VECTOR 7
	25	#define DF_VECTOR 8
	26	#define TS_VECTOR 10
	27	#define NP_VECTOR 11
	28	#define SS_VECTOR 12
	29	#define GP_VECTOR 13
	30	#define PF_VECTOR 14
	31	#define MF_VECTOR 16
a9fd1654	32	#define AC_VECTOR 17
716b8e4d	33	#define MC_VECTOR 18
a9fd1654 JF	34	#define XM_VECTOR 19
a9fd1654 JF	35	#define VE_VECTOR 20
716b8e4d	36
51b24e34 JK	37	/* Select x86 specific features in <linux/kvm.h> */
	38	#define __KVM_HAVE_PIT
	39	#define __KVM_HAVE_IOAPIC
651682dc	40	#define __KVM_HAVE_IRQ_LINE
51b24e34 JK	41	#define __KVM_HAVE_MSI
	42	#define __KVM_HAVE_USER_NMI
	43	#define __KVM_HAVE_GUEST_DEBUG
	44	#define __KVM_HAVE_MSIX
	45	#define __KVM_HAVE_MCE
	46	#define __KVM_HAVE_PIT_STATE2
	47	#define __KVM_HAVE_XEN_HVM
	48	#define __KVM_HAVE_VCPU_EVENTS
	49	#define __KVM_HAVE_DEBUGREGS
	50	#define __KVM_HAVE_XSAVE
	51	#define __KVM_HAVE_XCRS
716b8e4d	52	#define __KVM_HAVE_READONLY_MEM
51b24e34 JK	53
	54	/* Architectural interrupt line count. */
	55	#define KVM_NR_INTERRUPTS 256
	56
51b24e34 JK	57	/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
	58	struct kvm_pic_state {
	59	__u8 last_irr; /* edge detection */
	60	__u8 irr; /* interrupt request register */
	61	__u8 imr; /* interrupt mask register */
	62	__u8 isr; /* interrupt service register */
	63	__u8 priority_add; /* highest irq priority */
	64	__u8 irq_base;
	65	__u8 read_reg_select;
	66	__u8 poll;
	67	__u8 special_mask;
	68	__u8 init_state;
	69	__u8 auto_eoi;
	70	__u8 rotate_on_auto_eoi;
	71	__u8 special_fully_nested_mode;
	72	__u8 init4; /* true if 4 byte init */
	73	__u8 elcr; /* PIIX edge/trigger selection */
	74	__u8 elcr_mask;
	75	};
	76
	77	#define KVM_IOAPIC_NUM_PINS 24
	78	struct kvm_ioapic_state {
	79	__u64 base_address;
	80	__u32 ioregsel;
	81	__u32 id;
	82	__u32 irr;
	83	__u32 pad;
	84	union {
	85	__u64 bits;
	86	struct {
	87	__u8 vector;
	88	__u8 delivery_mode:3;
	89	__u8 dest_mode:1;
	90	__u8 delivery_status:1;
	91	__u8 polarity:1;
	92	__u8 remote_irr:1;
	93	__u8 trig_mode:1;
	94	__u8 mask:1;
	95	__u8 reserve:7;
	96	__u8 reserved[4];
	97	__u8 dest_id;
	98	} fields;
	99	} redirtbl[KVM_IOAPIC_NUM_PINS];
	100	};
	101
	102	#define KVM_IRQCHIP_PIC_MASTER 0
	103	#define KVM_IRQCHIP_PIC_SLAVE 1
	104	#define KVM_IRQCHIP_IOAPIC 2
	105	#define KVM_NR_IRQCHIPS 3
	106
24a31426	107	#define KVM_RUN_X86_SMM (1 << 0)
278f064e	108	#define KVM_RUN_X86_BUS_LOCK (1 << 1)
24a31426	109
51b24e34 JK	110	/* for KVM_GET_REGS and KVM_SET_REGS */
	111	struct kvm_regs {
	112	/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
	113	__u64 rax, rbx, rcx, rdx;
	114	__u64 rsi, rdi, rsp, rbp;
	115	__u64 r8, r9, r10, r11;
	116	__u64 r12, r13, r14, r15;
	117	__u64 rip, rflags;
	118	};
	119
	120	/* for KVM_GET_LAPIC and KVM_SET_LAPIC */
	121	#define KVM_APIC_REG_SIZE 0x400
	122	struct kvm_lapic_state {
	123	char regs[KVM_APIC_REG_SIZE];
	124	};
	125
	126	struct kvm_segment {
	127	__u64 base;
	128	__u32 limit;
	129	__u16 selector;
	130	__u8 type;
	131	__u8 present, dpl, db, s, l, g, avl;
	132	__u8 unusable;
	133	__u8 padding;
	134	};
	135
	136	struct kvm_dtable {
	137	__u64 base;
	138	__u16 limit;
	139	__u16 padding[3];
	140	};
	141
	142
	143	/* for KVM_GET_SREGS and KVM_SET_SREGS */
	144	struct kvm_sregs {
	145	/* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
	146	struct kvm_segment cs, ds, es, fs, gs, ss;
	147	struct kvm_segment tr, ldt;
	148	struct kvm_dtable gdt, idt;
	149	__u64 cr0, cr2, cr3, cr4, cr8;
	150	__u64 efer;
	151	__u64 apic_base;
b07d1c2f	152	__u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
51b24e34 JK	153	};
51b24e34 JK	154
327d4b7f BR	155	struct kvm_sregs2 {
	156	/* out (KVM_GET_SREGS2) / in (KVM_SET_SREGS2) */
	157	struct kvm_segment cs, ds, es, fs, gs, ss;
	158	struct kvm_segment tr, ldt;
	159	struct kvm_dtable gdt, idt;
	160	__u64 cr0, cr2, cr3, cr4, cr8;
	161	__u64 efer;
	162	__u64 apic_base;
	163	__u64 flags;
	164	__u64 pdptrs[4];
	165	};
	166	#define KVM_SREGS2_FLAGS_PDPTRS_VALID 1
	167
51b24e34 JK	168	/* for KVM_GET_FPU and KVM_SET_FPU */
	169	struct kvm_fpu {
	170	__u8 fpr[8][16];
	171	__u16 fcw;
	172	__u16 fsw;
	173	__u8 ftwx; /* in fxsave format */
	174	__u8 pad1;
	175	__u16 last_opcode;
	176	__u64 last_ip;
	177	__u64 last_dp;
	178	__u8 xmm[16][16];
	179	__u32 mxcsr;
	180	__u32 pad2;
	181	};
	182
	183	struct kvm_msr_entry {
	184	__u32 index;
	185	__u32 reserved;
	186	__u64 data;
	187	};
	188
	189	/* for KVM_GET_MSRS and KVM_SET_MSRS */
	190	struct kvm_msrs {
	191	__u32 nmsrs; /* number of msrs in entries */
	192	__u32 pad;
	193
d525f73f	194	struct kvm_msr_entry entries[];
51b24e34 JK	195	};
	196
	197	/* for KVM_GET_MSR_INDEX_LIST */
	198	struct kvm_msr_list {
	199	__u32 nmsrs; /* number of msrs in entries */
d525f73f	200	__u32 indices[];
51b24e34 JK	201	};
51b24e34 JK	202
53ba2eee MR	203	/* Maximum size of any access bitmap in bytes */
	204	#define KVM_MSR_FILTER_MAX_BITMAP_SIZE 0x600
	205
	206	/* for KVM_X86_SET_MSR_FILTER */
	207	struct kvm_msr_filter_range {
	208	#define KVM_MSR_FILTER_READ (1 << 0)
	209	#define KVM_MSR_FILTER_WRITE (1 << 1)
93d7620c AH	210	#define KVM_MSR_FILTER_RANGE_VALID_MASK (KVM_MSR_FILTER_READ \| \
93d7620c AH	211	KVM_MSR_FILTER_WRITE)
53ba2eee MR	212	__u32 flags;
	213	__u32 nmsrs; /* number of msrs in bitmap */
	214	__u32 base; /* MSR index the bitmap starts at */
	215	__u8 bitmap; / a 1 bit allows the operations in flags, 0 denies */
	216	};
	217
	218	#define KVM_MSR_FILTER_MAX_RANGES 16
	219	struct kvm_msr_filter {
	220	#define KVM_MSR_FILTER_DEFAULT_ALLOW (0 << 0)
	221	#define KVM_MSR_FILTER_DEFAULT_DENY (1 << 0)
93d7620c	222	#define KVM_MSR_FILTER_VALID_MASK (KVM_MSR_FILTER_DEFAULT_DENY)
53ba2eee MR	223	__u32 flags;
	224	struct kvm_msr_filter_range ranges[KVM_MSR_FILTER_MAX_RANGES];
	225	};
51b24e34 JK	226
	227	struct kvm_cpuid_entry {
	228	__u32 function;
	229	__u32 eax;
	230	__u32 ebx;
	231	__u32 ecx;
	232	__u32 edx;
	233	__u32 padding;
	234	};
	235
	236	/* for KVM_SET_CPUID */
	237	struct kvm_cpuid {
	238	__u32 nent;
	239	__u32 padding;
d525f73f	240	struct kvm_cpuid_entry entries[];
51b24e34 JK	241	};
	242
	243	struct kvm_cpuid_entry2 {
	244	__u32 function;
	245	__u32 index;
	246	__u32 flags;
	247	__u32 eax;
	248	__u32 ebx;
	249	__u32 ecx;
	250	__u32 edx;
	251	__u32 padding[3];
	252	};
	253
ff804f15 CH	254	#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX (1 << 0)
	255	#define KVM_CPUID_FLAG_STATEFUL_FUNC (1 << 1)
	256	#define KVM_CPUID_FLAG_STATE_READ_NEXT (1 << 2)
51b24e34 JK	257
	258	/* for KVM_SET_CPUID2 */
	259	struct kvm_cpuid2 {
	260	__u32 nent;
	261	__u32 padding;
d525f73f	262	struct kvm_cpuid_entry2 entries[];
51b24e34 JK	263	};
	264
	265	/* for KVM_GET_PIT and KVM_SET_PIT */
	266	struct kvm_pit_channel_state {
	267	__u32 count; /* can be 65536 */
	268	__u16 latched_count;
	269	__u8 count_latched;
	270	__u8 status_latched;
	271	__u8 status;
	272	__u8 read_state;
	273	__u8 write_state;
	274	__u8 write_latch;
	275	__u8 rw_mode;
	276	__u8 mode;
	277	__u8 bcd;
	278	__u8 gate;
	279	__s64 count_load_time;
	280	};
	281
	282	struct kvm_debug_exit_arch {
	283	__u32 exception;
	284	__u32 pad;
	285	__u64 pc;
	286	__u64 dr6;
	287	__u64 dr7;
	288	};
	289
	290	#define KVM_GUESTDBG_USE_SW_BP 0x00010000
	291	#define KVM_GUESTDBG_USE_HW_BP 0x00020000
	292	#define KVM_GUESTDBG_INJECT_DB 0x00040000
	293	#define KVM_GUESTDBG_INJECT_BP 0x00080000
43709a0c	294	#define KVM_GUESTDBG_BLOCKIRQ 0x00100000
51b24e34 JK	295
	296	/* for KVM_SET_GUEST_DEBUG */
	297	struct kvm_guest_debug_arch {
	298	__u64 debugreg[8];
	299	};
	300
	301	struct kvm_pit_state {
	302	struct kvm_pit_channel_state channels[3];
	303	};
	304
d525f73f CQ	305	#define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001
d525f73f CQ	306	#define KVM_PIT_FLAGS_SPEAKER_DATA_ON 0x00000002
51b24e34 JK	307
	308	struct kvm_pit_state2 {
	309	struct kvm_pit_channel_state channels[3];
	310	__u32 flags;
	311	__u32 reserved[9];
	312	};
	313
	314	struct kvm_reinject_control {
	315	__u8 pit_reinject;
	316	__u8 reserved[31];
	317	};
	318
	319	/* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
	320	#define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
	321	#define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
	322	#define KVM_VCPUEVENT_VALID_SHADOW 0x00000004
24a31426	323	#define KVM_VCPUEVENT_VALID_SMM 0x00000008
966f2ec3	324	#define KVM_VCPUEVENT_VALID_PAYLOAD 0x00000010
d525f73f	325	#define KVM_VCPUEVENT_VALID_TRIPLE_FAULT 0x00000020
51b24e34 JK	326
	327	/* Interrupt shadow states */
	328	#define KVM_X86_SHADOW_INT_MOV_SS 0x01
	329	#define KVM_X86_SHADOW_INT_STI 0x02
	330
	331	/* for KVM_GET/SET_VCPU_EVENTS */
	332	struct kvm_vcpu_events {
	333	struct {
	334	__u8 injected;
	335	__u8 nr;
	336	__u8 has_error_code;
966f2ec3	337	__u8 pending;
51b24e34 JK	338	__u32 error_code;
	339	} exception;
	340	struct {
	341	__u8 injected;
	342	__u8 nr;
	343	__u8 soft;
	344	__u8 shadow;
	345	} interrupt;
	346	struct {
	347	__u8 injected;
	348	__u8 pending;
	349	__u8 masked;
	350	__u8 pad;
	351	} nmi;
	352	__u32 sipi_vector;
	353	__u32 flags;
24a31426 PB	354	struct {
	355	__u8 smm;
	356	__u8 pending;
	357	__u8 smm_inside_nmi;
	358	__u8 latched_init;
	359	} smi;
d525f73f CQ	360	struct {
	361	__u8 pending;
	362	} triple_fault;
	363	__u8 reserved[26];
966f2ec3 PB	364	__u8 exception_has_payload;
966f2ec3 PB	365	__u64 exception_payload;
51b24e34 JK	366	};
	367
	368	/* for KVM_GET/SET_DEBUGREGS */
	369	struct kvm_debugregs {
	370	__u64 db[4];
	371	__u64 dr6;
	372	__u64 dr7;
	373	__u64 flags;
	374	__u64 reserved[9];
	375	};
	376
ef17dd6a	377	/* for KVM_CAP_XSAVE and KVM_CAP_XSAVE2 */
51b24e34	378	struct kvm_xsave {
ef17dd6a VG	379	/*
	380	* KVM_GET_XSAVE2 and KVM_SET_XSAVE write and read as many bytes
	381	* as are returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2)
	382	* respectively, when invoked on the vm file descriptor.
	383	*
	384	* The size value returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2)
	385	* will always be at least 4096. Currently, it is only greater
	386	* than 4096 if a dynamic feature has been enabled with
	387	* ``arch_prctl()``, but this may change in the future.
	388	*
	389	* The offsets of the state save areas in struct kvm_xsave follow
	390	* the contents of CPUID leaf 0xD on the host.
	391	*/
51b24e34	392	__u32 region[1024];
d525f73f	393	__u32 extra[];
51b24e34 JK	394	};
	395
	396	#define KVM_MAX_XCRS 16
	397
	398	struct kvm_xcr {
	399	__u32 xcr;
	400	__u32 reserved;
	401	__u64 value;
	402	};
	403
	404	struct kvm_xcrs {
	405	__u32 nr_xcrs;
	406	__u32 flags;
	407	struct kvm_xcr xcrs[KVM_MAX_XCRS];
	408	__u64 padding[16];
	409	};
	410
65a6d8dd PM	411	#define KVM_SYNC_X86_REGS (1UL << 0)
	412	#define KVM_SYNC_X86_SREGS (1UL << 1)
	413	#define KVM_SYNC_X86_EVENTS (1UL << 2)
	414
	415	#define KVM_SYNC_X86_VALID_FIELDS \
	416	(KVM_SYNC_X86_REGS\| \
	417	KVM_SYNC_X86_SREGS\| \
	418	KVM_SYNC_X86_EVENTS)
	419
	420	/* kvm_sync_regs struct included by kvm_run struct */
1529ae1b	421	struct kvm_sync_regs {
65a6d8dd PM	422	/* Members of this structure are potentially malicious.
	423	* Care must be taken by code reading, esp. interpreting,
	424	* data fields from them inside KVM to prevent TOCTOU and
	425	* double-fetch types of vulnerabilities.
	426	*/
	427	struct kvm_regs regs;
	428	struct kvm_sregs sregs;
	429	struct kvm_vcpu_events events;
1529ae1b AG	430	};
1529ae1b AG	431
d525f73f CQ	432	#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0)
	433	#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1)
	434	#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2)
	435	#define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3)
	436	#define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4)
	437	#define KVM_X86_QUIRK_FIX_HYPERCALL_INSN (1 << 5)
	438	#define KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS (1 << 6)
24a31426	439
1d33bea4	440	#define KVM_STATE_NESTED_FORMAT_VMX 0
f76b348e	441	#define KVM_STATE_NESTED_FORMAT_SVM 1
1d33bea4	442
d36f7de8 CH	443	#define KVM_STATE_NESTED_GUEST_MODE 0x00000001
d36f7de8 CH	444	#define KVM_STATE_NESTED_RUN_PENDING 0x00000002
966f2ec3	445	#define KVM_STATE_NESTED_EVMCS 0x00000004
dc6f8d45	446	#define KVM_STATE_NESTED_MTF_PENDING 0x00000008
f76b348e	447	#define KVM_STATE_NESTED_GIF_SET 0x00000100
d36f7de8 CH	448
	449	#define KVM_STATE_NESTED_SMM_GUEST_MODE 0x00000001
	450	#define KVM_STATE_NESTED_SMM_VMXON 0x00000002
	451
f363d039 EA	452	#define KVM_STATE_NESTED_VMX_VMCS_SIZE 0x1000
f363d039 EA	453
f76b348e CH	454	#define KVM_STATE_NESTED_SVM_VMCB_SIZE 0x1000
	455
	456	#define KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE 0x00000001
	457
1ea5208f PB	458	/* attributes for system fd (group 0) */
	459	#define KVM_X86_XCOMP_GUEST_SUPP 0
	460
1d33bea4 LA	461	struct kvm_vmx_nested_state_data {
	462	__u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE];
	463	__u8 shadow_vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE];
	464	};
	465
	466	struct kvm_vmx_nested_state_hdr {
d36f7de8	467	__u64 vmxon_pa;
1d33bea4	468	__u64 vmcs12_pa;
d36f7de8 CH	469
	470	struct {
	471	__u16 flags;
	472	} smm;
56908dc5	473
278f064e EH	474	__u16 pad;
278f064e EH	475
56908dc5 PB	476	__u32 flags;
56908dc5 PB	477	__u64 preemption_timer_deadline;
d36f7de8 CH	478	};
d36f7de8 CH	479
f76b348e CH	480	struct kvm_svm_nested_state_data {
	481	/* Save area only used if KVM_STATE_NESTED_RUN_PENDING. */
	482	__u8 vmcb12[KVM_STATE_NESTED_SVM_VMCB_SIZE];
	483	};
	484
	485	struct kvm_svm_nested_state_hdr {
	486	__u64 vmcb_pa;
	487	};
	488
d36f7de8 CH	489	/* for KVM_CAP_NESTED_STATE */
d36f7de8 CH	490	struct kvm_nested_state {
d36f7de8	491	__u16 flags;
d36f7de8	492	__u16 format;
d36f7de8 CH	493	__u32 size;
	494
	495	union {
1d33bea4	496	struct kvm_vmx_nested_state_hdr vmx;
f76b348e	497	struct kvm_svm_nested_state_hdr svm;
d36f7de8 CH	498
	499	/* Pad the header to 128 bytes. */
	500	__u8 pad[120];
1d33bea4	501	} hdr;
d36f7de8	502
1d33bea4 LA	503	/*
	504	* Define data region as 0 bytes to preserve backwards-compatability
	505	* to old definition of kvm_nested_state in order to avoid changing
	506	* KVM_{GET,PUT}_NESTED_STATE ioctl values.
	507	*/
	508	union {
c5c0fdbe DDT	509	__DECLARE_FLEX_ARRAY(struct kvm_vmx_nested_state_data, vmx);
c5c0fdbe DDT	510	__DECLARE_FLEX_ARRAY(struct kvm_svm_nested_state_data, svm);
1d33bea4	511	} data;
d36f7de8 CH	512	};
d36f7de8 CH	513
f363d039 EA	514	/* for KVM_CAP_PMU_EVENT_FILTER */
	515	struct kvm_pmu_event_filter {
	516	__u32 action;
	517	__u32 nevents;
	518	__u32 fixed_counter_bitmap;
	519	__u32 flags;
	520	__u32 pad[4];
d525f73f	521	__u64 events[];
f363d039 EA	522	};
	523
	524	#define KVM_PMU_EVENT_ALLOW 0
	525	#define KVM_PMU_EVENT_DENY 1
	526
c5c0fdbe DDT	527	#define KVM_PMU_EVENT_FLAG_MASKED_EVENTS BIT(0)
	528	#define KVM_PMU_EVENT_FLAGS_VALID_MASK (KVM_PMU_EVENT_FLAG_MASKED_EVENTS)
	529
	530	/*
	531	* Masked event layout.
	532	* Bits Description
	533	* ---- -----------
	534	* 7:0 event select (low bits)
	535	* 15:8 umask match
	536	* 31:16 unused
	537	* 35:32 event select (high bits)
	538	* 36:54 unused
	539	* 55 exclude bit
	540	* 63:56 umask mask
	541	*/
	542
	543	#define KVM_PMU_ENCODE_MASKED_ENTRY(event_select, mask, match, exclude) \
	544	(((event_select) & 0xFFULL) \| (((event_select) & 0XF00ULL) << 24) \| \
	545	(((mask) & 0xFFULL) << 56) \| \
	546	(((match) & 0xFFULL) << 8) \| \
	547	((__u64)(!!(exclude)) << 55))
	548
	549	#define KVM_PMU_MASKED_ENTRY_EVENT_SELECT \
	550	(GENMASK_ULL(7, 0) \| GENMASK_ULL(35, 32))
	551	#define KVM_PMU_MASKED_ENTRY_UMASK_MASK (GENMASK_ULL(63, 56))
	552	#define KVM_PMU_MASKED_ENTRY_UMASK_MATCH (GENMASK_ULL(15, 8))
	553	#define KVM_PMU_MASKED_ENTRY_EXCLUDE (BIT_ULL(55))
	554	#define KVM_PMU_MASKED_ENTRY_UMASK_MASK_SHIFT (56)
	555
43709a0c PB	556	/* for KVM_{GET,SET,HAS}_DEVICE_ATTR */
	557	#define KVM_VCPU_TSC_CTRL 0 /* control group for the timestamp counter (TSC) */
	558	#define KVM_VCPU_TSC_OFFSET 0 /* attribute for the TSC offset */
	559
51b24e34	560	#endif /* _ASM_X86_KVM_H */