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rename CFG_ macros to CONFIG_SYS
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887e2ec9 1/*
46f37383 2 * (C) Copyright 2006-2008
887e2ec9
SR
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#include <common.h>
22#include <nand.h>
c568f77a 23#include <asm/io.h>
887e2ec9 24
6d0f6bcf 25#define CONFIG_SYS_NAND_READ_DELAY \
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26 { volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; }
27
6d0f6bcf 28static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
42be56f5 29
887e2ec9 30extern void board_nand_init(struct nand_chip *nand);
887e2ec9 31
6d0f6bcf 32#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
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SR
33/*
34 * NAND command for small page NAND devices (512)
35 */
42be56f5 36static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
887e2ec9 37{
511d0c72 38 struct nand_chip *this = mtd->priv;
6d0f6bcf 39 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
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SR
40
41 if (this->dev_ready)
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SR
42 while (!this->dev_ready(mtd))
43 ;
42be56f5 44 else
6d0f6bcf 45 CONFIG_SYS_NAND_READ_DELAY;
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SR
46
47 /* Begin command latch cycle */
4f32d776 48 this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
887e2ec9 49 /* Set ALE and clear CLE to start address cycle */
887e2ec9 50 /* Column address */
4f32d776
SW
51 this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
52 this->cmd_ctrl(mtd, page_addr & 0xff, 0); /* A[16:9] */
53 this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff, 0); /* A[24:17] */
6d0f6bcf 54#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
887e2ec9 55 /* One more address cycle for devices > 32MiB */
4f32d776 56 this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, 0); /* A[28:25] */
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57#endif
58 /* Latch in address */
c568f77a 59 this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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60
61 /*
62 * Wait a while for the data to be ready
63 */
64 if (this->dev_ready)
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65 while (!this->dev_ready(mtd))
66 ;
887e2ec9 67 else
6d0f6bcf 68 CONFIG_SYS_NAND_READ_DELAY;
887e2ec9 69
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70 return 0;
71}
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72#else
73/*
74 * NAND command for large page NAND devices (2k)
75 */
76static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
77{
78 struct nand_chip *this = mtd->priv;
6d0f6bcf 79 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
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80
81 if (this->dev_ready)
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SW
82 while (!this->dev_ready(mtd))
83 ;
46f37383 84 else
6d0f6bcf 85 CONFIG_SYS_NAND_READ_DELAY;
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SR
86
87 /* Emulate NAND_CMD_READOOB */
88 if (cmd == NAND_CMD_READOOB) {
6d0f6bcf 89 offs += CONFIG_SYS_NAND_PAGE_SIZE;
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SR
90 cmd = NAND_CMD_READ0;
91 }
92
93 /* Begin command latch cycle */
4f32d776 94 this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
46f37383 95 /* Set ALE and clear CLE to start address cycle */
46f37383 96 /* Column address */
4f32d776 97 this->cmd_ctrl(mtd, offs & 0xff,
4b070809 98 NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
4f32d776 99 this->cmd_ctrl(mtd, (offs >> 8) & 0xff, 0); /* A[11:9] */
46f37383 100 /* Row address */
4f32d776
SW
101 this->cmd_ctrl(mtd, (page_addr & 0xff), 0); /* A[19:12] */
102 this->cmd_ctrl(mtd, ((page_addr >> 8) & 0xff), 0); /* A[27:20] */
6d0f6bcf 103#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
46f37383 104 /* One more address cycle for devices > 128MiB */
4f32d776 105 this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, 0); /* A[31:28] */
46f37383
SR
106#endif
107 /* Latch in address */
4f32d776 108 this->cmd_ctrl(mtd, NAND_CMD_READSTART,
4b070809 109 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
4f32d776 110 this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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SR
111
112 /*
113 * Wait a while for the data to be ready
114 */
115 if (this->dev_ready)
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SW
116 while (!this->dev_ready(mtd))
117 ;
46f37383 118 else
6d0f6bcf 119 CONFIG_SYS_NAND_READ_DELAY;
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120
121 return 0;
122}
123#endif
42be56f5
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124
125static int nand_is_bad_block(struct mtd_info *mtd, int block)
126{
127 struct nand_chip *this = mtd->priv;
128
6d0f6bcf 129 nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
42be56f5 130
887e2ec9 131 /*
10c7382b 132 * Read one byte
887e2ec9 133 */
aa646643 134 if (readb(this->IO_ADDR_R) != 0xff)
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135 return 1;
136
137 return 0;
138}
139
140static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
141{
511d0c72 142 struct nand_chip *this = mtd->priv;
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SR
143 u_char *ecc_calc;
144 u_char *ecc_code;
145 u_char *oob_data;
887e2ec9 146 int i;
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JCPV
147 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
148 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
149 int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
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SR
150 uint8_t *p = dst;
151 int stat;
887e2ec9 152
42be56f5 153 nand_command(mtd, block, page, 0, NAND_CMD_READ0);
887e2ec9 154
42be56f5
SR
155 /* No malloc available for now, just use some temporary locations
156 * in SDRAM
887e2ec9 157 */
6d0f6bcf 158 ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
42be56f5
SR
159 ecc_code = ecc_calc + 0x100;
160 oob_data = ecc_calc + 0x200;
161
162 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
c568f77a 163 this->ecc.hwctl(mtd, NAND_ECC_READ);
42be56f5 164 this->read_buf(mtd, p, eccsize);
c568f77a 165 this->ecc.calculate(mtd, p, &ecc_calc[i]);
42be56f5 166 }
6d0f6bcf 167 this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
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SR
168
169 /* Pick the ECC bytes out of the oob data */
6d0f6bcf 170 for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
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SR
171 ecc_code[i] = oob_data[nand_ecc_pos[i]];
172
6d0f6bcf 173 eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
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174 p = dst;
175
176 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
177 /* No chance to do something with the possible error message
178 * from correct_data(). We just hope that all possible errors
179 * are corrected by this routine.
180 */
c568f77a 181 stat = this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
42be56f5 182 }
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183
184 return 0;
185}
186
aa646643 187static int nand_load(struct mtd_info *mtd, unsigned int offs,
4b070809 188 unsigned int uboot_size, uchar *dst)
887e2ec9 189{
aa646643
GL
190 unsigned int block, lastblock;
191 unsigned int page;
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192
193 /*
aa646643 194 * offs has to be aligned to a page address!
887e2ec9 195 */
6d0f6bcf
JCPV
196 block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
197 lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
198 page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
887e2ec9 199
aa646643 200 while (block <= lastblock) {
887e2ec9
SR
201 if (!nand_is_bad_block(mtd, block)) {
202 /*
203 * Skip bad blocks
204 */
6d0f6bcf 205 while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
887e2ec9 206 nand_read_page(mtd, block, page, dst);
6d0f6bcf 207 dst += CONFIG_SYS_NAND_PAGE_SIZE;
aa646643 208 page++;
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209 }
210
aa646643
GL
211 page = 0;
212 } else {
213 lastblock++;
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214 }
215
216 block++;
217 }
218
219 return 0;
220}
221
64852d09
SR
222/*
223 * The main entry for NAND booting. It's necessary that SDRAM is already
224 * configured and available since this code loads the main U-Boot image
225 * from NAND into SDRAM and starts it from there.
226 */
887e2ec9
SR
227void nand_boot(void)
228{
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SR
229 struct nand_chip nand_chip;
230 nand_info_t nand_info;
231 int ret;
e4c09508 232 __attribute__((noreturn)) void (*uboot)(void);
887e2ec9 233
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SR
234 /*
235 * Init board specific nand support
236 */
237 nand_info.priv = &nand_chip;
6d0f6bcf 238 nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
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SR
239 nand_chip.dev_ready = NULL; /* preset to NULL */
240 board_nand_init(&nand_chip);
241
aa646643
GL
242 if (nand_chip.select_chip)
243 nand_chip.select_chip(&nand_info, 0);
244
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SR
245 /*
246 * Load U-Boot image from NAND into RAM
247 */
6d0f6bcf
JCPV
248 ret = nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
249 (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
887e2ec9 250
aa646643
GL
251 if (nand_chip.select_chip)
252 nand_chip.select_chip(&nand_info, -1);
253
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SR
254 /*
255 * Jump to U-Boot image
256 */
6d0f6bcf 257 uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
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SR
258 (*uboot)();
259}