[thirdparty/binutils-gdb.git] / opcodes / ChangeLog

2006-05-22  Nick Clifton  <nickc@redhat.com>

	* po/nl.po: Updated translation.

2006-05-18  Alan Modra  <amodra@bigpond.net.au>

	* avr-dis.c: Formatting fix.

2006-05-14  Thiemo Seufer  <ths@mips.com>

	* mips16-opc.c (I1, I32, I64): New shortcut defines.
	(mips16_opcodes): Change membership of instructions to their
	lowest baseline ISA.

2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (grps): Update sgdt/sidt for 64bit.

2006-05-05  Julian Brown  <julian@codesourcery.com>

	* arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
	vldm/vstm.

2006-05-05  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>

	* mips-opc.c: Add macro for cache instruction.

2006-05-04  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
	    David Ung  <davidu@mips.com>

	* mips-dis.c (mips_arch_choices): Add smartmips instruction
	decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
	2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
	MIPS64R2.
	* mips-opc.c: fix random typos in comments.
	(INSN_SMARTMIPS): New defines.
	(mips_builtin_opcodes): Add paired single support for MIPS32R2.
	Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
	flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
	FP_S and FP_D flags to denote single and double register
	accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
	Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
	for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
	variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
	release 2 ISAs.
	* mips16-opc.c (mips16_opcodes): Add sdbbp instruction.

2006-05-03  Thiemo Seufer  <ths@mips.com>

	* mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.

2006-05-02  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
            David Ung  <davidu@mips.com>

	* mips-dis.c (print_insn_args): Force mips16 to odd addresses.
	(print_mips16_insn_arg): Force mips16 to odd addresses.

2006-04-30  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>

	* mips-opc.c (mips_builtin_opcodes): Add udi instructions
	"udi0" to "udi15".
	* mips-dis.c (print_insn_args): Adds udi argument handling.

2006-04-28  James E Wilson  <wilson@specifix.com>

	* m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
	error message.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>
	    Nigel Stephens  <nigel@mips.com>

	* mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
	names.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
            David Ung  <davidu@mips.com>

	* mips-dis.c (print_insn_args): Add mips_opcode argument.
	(print_insn_mips):  Adjust print_insn_args call.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>

	* mips-dis.c (print_insn_args): Print $fcc only for FP
	instructions, use $cc elsewise.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>

	* opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
	Map MIPS16 registers to O32 names.
	(print_mips16_insn_arg): Use mips16_reg_names.

2006-04-26  Julian Brown  <julian@codesourcery.com>

	* arm-dis.c (print_insn_neon): Disassemble floating-point constant
	VMOV.

2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
	    Julian Brown  <julian@codesourcery.com>

	* opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
	%<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
	Add unified load/store instruction names.
	(neon_opcode_table): New.
	(arm_opcodes): Expand meaning of %<bitfield>['`?].
	(arm_decode_bitfield): New.
	(print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
	Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
	(print_insn_neon): New.
	(print_insn_arm): Adjust print_insn_coprocessor call. Call
	print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
	(print_insn_thumb32): Likewise.

2006-04-19  Alan Modra  <amodra@bigpond.net.au>

	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.

2006-04-19  Alan Modra  <amodra@bigpond.net.au>

	* avr-dis.c (avr_operand): Warning fix.

	* configure: Regenerate.

2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>

	* po/POTFILES.in: Regenerated.

2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>

	PR binutils/2454
	* avr-dis.c (avr_operand): Arrange for a comment to appear before
	the symolic form of an address, so that the output of objdump -d
	can be reassembled.

2006-04-10  DJ Delorie  <dj@redhat.com>

	* m32c-asm.c: Regenerate.

2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>

	* Makefile.am: Add install-html target.
	* Makefile.in: Regenerate.

2006-04-06  Nick Clifton  <nickc@redhat.com>

	* po/vi/po: Updated Vietnamese translation.

2006-03-31  Paul Koning  <ni1d@arrl.net>

	* pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.

2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>

	* bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
	logic to identify halfword shifts.

2006-03-16  Paul Brook  <paul@codesourcery.com>

	* arm-dis.c (arm_opcodes): Rename swi to svc.
	(thumb_opcodes): Ditto.

2006-03-13  DJ Delorie  <dj@redhat.com>

	* m32c-asm.c: Regenerate.
	* m32c-desc.c: Likewise.
	* m32c-desc.h: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-ibld.c: Likewise.
	* m32c-opc.c: Likewise.
	* m32c-opc.h: Likewise.

2006-03-10  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate with mul.l, mulu.l.
	* m32c-opc.c: Likewise.
	* m32c-opc.h: Likewise.


2006-03-09  Nick Clifton  <nickc@redhat.com>

	* po/sv.po: Updated Swedish translation.

2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/2428
	* i386-dis.c (REP_Fixup): New function.
	(AL): Remove duplicate.
	(Xbr): New.
	(Xvr): Likewise.
	(Ybr): Likewise.
	(Yvr): Likewise.
	(indirDXr): Likewise.
	(ALr): Likewise.
	(eAXr): Likewise.
	(dis386): Updated entries of ins, outs, movs, lods and stos.

2006-03-05  Nick Clifton  <nickc@redhat.com>

	* cgen-ibld.in (insert_normal): Cope with attempts to insert a
	signed 32-bit value into an unsigned 32-bit field when the host is
	a 64-bit machine.
	* fr30-ibld.c: Regenerate.
	* frv-ibld.c: Regenerate.
	* ip2k-ibld.c: Regenerate.
	* iq2000-asm.c: Regenerate.
	* iq2000-ibld.c: Regenerate.
	* m32c-ibld.c: Regenerate.
	* m32r-ibld.c: Regenerate.
	* openrisc-ibld.c: Regenerate.
	* xc16x-ibld.c: Regenerate.
	* xstormy16-ibld.c: Regenerate.

2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)

	* xc16x-asm.c: Regenerate.
	* xc16x-dis.c: Regenerate.

2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>

	* po/Make-in: Add html target.

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
	Intel Merom New Instructions.
	(THREE_BYTE_0): Likewise.
	(THREE_BYTE_1): Likewise.
	(three_byte_table): Likewise.
	(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
	THREE_BYTE_1 for entry 0x3a.
	(twobyte_has_modrm): Updated.
	(twobyte_uses_SSE_prefix): Likewise.
	(print_insn): Handle 3-byte opcodes used by Intel Merom New
	Instructions.

2006-02-24  David S. Miller  <davem@sunset.davemloft.net>

	* sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
	(v9_hpriv_reg_names): New table.
	(print_insn_sparc): Allow values up to 16 for '?' and '!'.
	New cases '$' and '%' for read/write hyperprivileged register.
	* sparc-opc.c (sparc_opcodes): Add new entries for UA2005
	window handling and rdhpr/wrhpr instructions.
	
2006-02-24  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate with linker relaxation attributes.
	* m32c-desc.h: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-opc.c: Likewise.

2006-02-24  Paul Brook  <paul@codesourcery.com>

	* arm-dis.c (arm_opcodes): Add V7 instructions.
	(thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
	(print_arm_address): New function.
	(print_insn_arm): Use it.  Add 'P' and 'U' cases.
	(psr_name): New function.
	(print_insn_thumb32): Add 'U', 'C' and 'D' cases.

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-opc-i.c (bXc): New.
	(mXc): Likewise.
	(OpX2TaTbYaXcC): Likewise.
	(TF). Likewise.
	(TFCM). Likewise.
	(ia64_opcodes_i): Add instructions for tf.

	* ia64-opc.h (IMMU5b): New.

	* ia64-asmtab.c: Regenerated.

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-gen.c: Update copyright years.
	* ia64-opc-b.c: Likewise.

2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-gen.c (lookup_regindex): Handle ".vm".
	(print_dependency_table): Handle '\"'.

	* ia64-ic.tbl: Updated from SDM 2.2.
	* ia64-raw.tbl: Likewise.
	* ia64-waw.tbl: Likewise.
	* ia64-asmtab.c: Regenerated.

	* ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.

2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
            Anil Paranjape   <anilp1@kpitcummins.com>
            Shilin Shakti    <shilins@kpitcummins.com>

	* xc16x-desc.h: New file
	* xc16x-desc.c: New file
	* xc16x-opc.h: New file	
	* xc16x-opc.c: New file
	* xc16x-ibld.c: New file
	* xc16x-asm.c: New file
	* xc16x-dis.c: New file
	* Makefile.am: Entries for xc16x 
	* Makefile.in: Regenerate 
	* cofigure.in: Add xc16x target information.
	* configure: Regenerate.
	* disassemble.c: Add xc16x target information.

2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (dis386_twobyte): Use "movZ" for debug register
	moves.

2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c ('Z'): Add a new macro.
	(dis386_twobyte): Use "movZ" for control register moves.

2006-02-10  Nick Clifton  <nickc@redhat.com>

	* iq2000-asm.c: Regenerate.

2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>

	* m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.

2006-01-26  David Ung  <davidu@mips.com>

	* mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
	ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
	floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
	nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
	rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.

2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>

	* z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
	ld_d_r, pref_xd_cb): Use signed char to hold data to be
	disassembled.	
	* z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
	buffer overflows when disassembling instructions like
	ld (ix+123),0x23
	* z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
	operand, if the offset is negative.

2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>

	* z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
	unsigned char to hold data to be disassembled.

2006-01-17  Andreas Schwab  <schwab@suse.de>

	PR binutils/1486
	* disassemble.c (disassemble_init_for_target): Set
	disassembler_needs_relocs for bfd_arch_arm.

2006-01-16  Paul Brook  <paul@codesourcery.com>

	* m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
	f?add?, and f?sub? instructions.

2006-01-16  Nick Clifton  <nickc@redhat.com>

	* po/zh_CN.po: New Chinese (simplified) translation.
	* configure.in (ALL_LINGUAS): Add "zh_CH".
	* configure: Regenerate.

2006-01-05  Paul Brook  <paul@codesourcery.com>

	* m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.

2006-01-06  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate.
	* m32c-opc.c: Regenerate.
	* m32c-opc.h: Regenerate.

2006-01-03  DJ Delorie  <dj@redhat.com>

	* cgen-ibld.in (extract_normal): Avoid memory range errors.
	* m32c-ibld.c: Regenerated.

For older changes see ChangeLog-2005
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
0bd79061 NC	1	2006-05-22 Nick Clifton <nickc@redhat.com>
	2
	3	* po/nl.po: Updated translation.
	4
00988f49 AM	5	2006-05-18 Alan Modra <amodra@bigpond.net.au>
	6
	7	* avr-dis.c: Formatting fix.
	8
9b3f89ee TS	9	2006-05-14 Thiemo Seufer <ths@mips.com>
	10
	11	* mips16-opc.c (I1, I32, I64): New shortcut defines.
	12	(mips16_opcodes): Change membership of instructions to their
	13	lowest baseline ISA.
	14
cb6d3433 L	15	2006-05-09 H.J. Lu <hongjiu.lu@intel.com>
	16
	17	* i386-dis.c (grps): Update sgdt/sidt for 64bit.
	18
1f3c39b9 JB	19	2006-05-05 Julian Brown <julian@codesourcery.com>
	20
	21	* arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
	22	vldm/vstm.
	23
d43b4baf TS	24	2006-05-05 Thiemo Seufer <ths@mips.com>
	25	David Ung <davidu@mips.com>
	26
	27	* mips-opc.c: Add macro for cache instruction.
	28
39a7806d TS	29	2006-05-04 Thiemo Seufer <ths@mips.com>
	30	Nigel Stephens <nigel@mips.com>
	31	David Ung <davidu@mips.com>
	32
	33	* mips-dis.c (mips_arch_choices): Add smartmips instruction
	34	decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
	35	2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
	36	MIPS64R2.
	37	* mips-opc.c: fix random typos in comments.
	38	(INSN_SMARTMIPS): New defines.
	39	(mips_builtin_opcodes): Add paired single support for MIPS32R2.
	40	Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
	41	flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
	42	FP_S and FP_D flags to denote single and double register
	43	accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
	44	Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
	45	for MIPS32R2. Add SmartMIPS instructions. Add two-argument
	46	variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
	47	release 2 ISAs.
	48	* mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
	49
104b4fab TS	50	2006-05-03 Thiemo Seufer <ths@mips.com>
	51
	52	* mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
	53
022fac6d TS	54	2006-05-02 Thiemo Seufer <ths@mips.com>
	55	Nigel Stephens <nigel@mips.com>
	56	David Ung <davidu@mips.com>
	57
	58	* mips-dis.c (print_insn_args): Force mips16 to odd addresses.
	59	(print_mips16_insn_arg): Force mips16 to odd addresses.
	60
9bcd4f99 TS	61	2006-04-30 Thiemo Seufer <ths@mips.com>
	62	David Ung <davidu@mips.com>
	63
	64	* mips-opc.c (mips_builtin_opcodes): Add udi instructions
	65	"udi0" to "udi15".
	66	* mips-dis.c (print_insn_args): Adds udi argument handling.
	67
f095b97b JW	68	2006-04-28 James E Wilson <wilson@specifix.com>
	69
	70	* m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
	71	error message.
	72
59c455b3 TS	73	2006-04-28 Thiemo Seufer <ths@mips.com>
59c455b3 TS	74	David Ung <davidu@mips.com>
bdb09db1	75	Nigel Stephens <nigel@mips.com>
59c455b3 TS	76
	77	* mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
	78	names.
	79
cc0ca239	80	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	81	Nigel Stephens <nigel@mips.com>
cc0ca239 TS	82	David Ung <davidu@mips.com>
	83
	84	* mips-dis.c (print_insn_args): Add mips_opcode argument.
	85	(print_insn_mips): Adjust print_insn_args call.
	86
0d09bfe6	87	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	88	Nigel Stephens <nigel@mips.com>
0d09bfe6 TS	89
	90	* mips-dis.c (print_insn_args): Print $fcc only for FP
	91	instructions, use $cc elsewise.
	92
654c225a	93	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	94	Nigel Stephens <nigel@mips.com>
654c225a TS	95
	96	* opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
	97	Map MIPS16 registers to O32 names.
	98	(print_mips16_insn_arg): Use mips16_reg_names.
	99
0dbde4cf JB	100	2006-04-26 Julian Brown <julian@codesourcery.com>
	101
	102	* arm-dis.c (print_insn_neon): Disassemble floating-point constant
	103	VMOV.
	104
16980d0b JB	105	2006-04-26 Nathan Sidwell <nathan@codesourcery.com>
	106	Julian Brown <julian@codesourcery.com>
	107
	108	* opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
	109	%<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
	110	Add unified load/store instruction names.
	111	(neon_opcode_table): New.
	112	(arm_opcodes): Expand meaning of %<bitfield>['`?].
	113	(arm_decode_bitfield): New.
	114	(print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
	115	Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
	116	(print_insn_neon): New.
	117	(print_insn_arm): Adjust print_insn_coprocessor call. Call
	118	print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
	119	(print_insn_thumb32): Likewise.
	120
ec3fcc56 AM	121	2006-04-19 Alan Modra <amodra@bigpond.net.au>
	122
	123	* Makefile.am: Run "make dep-am".
	124	* Makefile.in: Regenerate.
	125
241a6c40 AM	126	2006-04-19 Alan Modra <amodra@bigpond.net.au>
241a6c40 AM	127
7c6646cd AM	128	* avr-dis.c (avr_operand): Warning fix.
7c6646cd AM	129
241a6c40 AM	130	* configure: Regenerate.
241a6c40 AM	131
e7403566 DJ	132	2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
	133
	134	* po/POTFILES.in: Regenerated.
	135
52f16a0e NC	136	2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
	137
	138	PR binutils/2454
	139	* avr-dis.c (avr_operand): Arrange for a comment to appear before
	140	the symolic form of an address, so that the output of objdump -d
	141	can be reassembled.
	142
e78efa90 DD	143	2006-04-10 DJ Delorie <dj@redhat.com>
	144
	145	* m32c-asm.c: Regenerate.
	146
108a6f8e CD	147	2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
	148
	149	* Makefile.am: Add install-html target.
	150	* Makefile.in: Regenerate.
	151
a135cb2c NC	152	2006-04-06 Nick Clifton <nickc@redhat.com>
	153
	154	* po/vi/po: Updated Vietnamese translation.
	155
47426b41 AM	156	2006-03-31 Paul Koning <ni1d@arrl.net>
	157
	158	* pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
	159
331f1cbe BS	160	2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
	161
	162	* bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
	163	logic to identify halfword shifts.
	164
c16d2bf0 PB	165	2006-03-16 Paul Brook <paul@codesourcery.com>
	166
	167	* arm-dis.c (arm_opcodes): Rename swi to svc.
	168	(thumb_opcodes): Ditto.
	169
5348b81e DD	170	2006-03-13 DJ Delorie <dj@redhat.com>
5348b81e DD	171
5398310a DD	172	* m32c-asm.c: Regenerate.
	173	* m32c-desc.c: Likewise.
	174	* m32c-desc.h: Likewise.
	175	* m32c-dis.c: Likewise.
	176	* m32c-ibld.c: Likewise.
5348b81e DD	177	* m32c-opc.c: Likewise.
	178	* m32c-opc.h: Likewise.
	179
253d272c DD	180	2006-03-10 DJ Delorie <dj@redhat.com>
	181
	182	* m32c-desc.c: Regenerate with mul.l, mulu.l.
	183	* m32c-opc.c: Likewise.
	184	* m32c-opc.h: Likewise.
	185
	186
f530741d NC	187	2006-03-09 Nick Clifton <nickc@redhat.com>
	188
	189	* po/sv.po: Updated Swedish translation.
	190
35c52694 L	191	2006-03-07 H.J. Lu <hongjiu.lu@intel.com>
	192
	193	PR binutils/2428
	194	* i386-dis.c (REP_Fixup): New function.
	195	(AL): Remove duplicate.
	196	(Xbr): New.
	197	(Xvr): Likewise.
	198	(Ybr): Likewise.
	199	(Yvr): Likewise.
	200	(indirDXr): Likewise.
	201	(ALr): Likewise.
	202	(eAXr): Likewise.
	203	(dis386): Updated entries of ins, outs, movs, lods and stos.
	204
ed963e2d NC	205	2006-03-05 Nick Clifton <nickc@redhat.com>
	206
	207	* cgen-ibld.in (insert_normal): Cope with attempts to insert a
	208	signed 32-bit value into an unsigned 32-bit field when the host is
	209	a 64-bit machine.
	210	* fr30-ibld.c: Regenerate.
	211	* frv-ibld.c: Regenerate.
	212	* ip2k-ibld.c: Regenerate.
	213	* iq2000-asm.c: Regenerate.
	214	* iq2000-ibld.c: Regenerate.
	215	* m32c-ibld.c: Regenerate.
	216	* m32r-ibld.c: Regenerate.
	217	* openrisc-ibld.c: Regenerate.
	218	* xc16x-ibld.c: Regenerate.
	219	* xstormy16-ibld.c: Regenerate.
	220
c7d41dc5 NC	221	2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
	222
	223	* xc16x-asm.c: Regenerate.
	224	* xc16x-dis.c: Regenerate.
c7d41dc5	225
f7d9e5c3 CD	226	2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
	227
	228	* po/Make-in: Add html target.
	229
331d2d0d L	230	2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
	231
	232	* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
	233	Intel Merom New Instructions.
	234	(THREE_BYTE_0): Likewise.
	235	(THREE_BYTE_1): Likewise.
	236	(three_byte_table): Likewise.
	237	(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
	238	THREE_BYTE_1 for entry 0x3a.
	239	(twobyte_has_modrm): Updated.
	240	(twobyte_uses_SSE_prefix): Likewise.
	241	(print_insn): Handle 3-byte opcodes used by Intel Merom New
	242	Instructions.
	243
ff3f9d5b DM	244	2006-02-24 David S. Miller <davem@sunset.davemloft.net>
	245
	246	* sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
	247	(v9_hpriv_reg_names): New table.
	248	(print_insn_sparc): Allow values up to 16 for '?' and '!'.
	249	New cases '$' and '%' for read/write hyperprivileged register.
	250	* sparc-opc.c (sparc_opcodes): Add new entries for UA2005
	251	window handling and rdhpr/wrhpr instructions.
	252
6772dd07 DD	253	2006-02-24 DJ Delorie <dj@redhat.com>
	254
	255	* m32c-desc.c: Regenerate with linker relaxation attributes.
	256	* m32c-desc.h: Likewise.
	257	* m32c-dis.c: Likewise.
	258	* m32c-opc.c: Likewise.
	259
62b3e311 PB	260	2006-02-24 Paul Brook <paul@codesourcery.com>
	261
	262	* arm-dis.c (arm_opcodes): Add V7 instructions.
	263	(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
	264	(print_arm_address): New function.
	265	(print_insn_arm): Use it. Add 'P' and 'U' cases.
	266	(psr_name): New function.
	267	(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
	268
59cf82fe L	269	2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
	270
	271	* ia64-opc-i.c (bXc): New.
	272	(mXc): Likewise.
	273	(OpX2TaTbYaXcC): Likewise.
	274	(TF). Likewise.
	275	(TFCM). Likewise.
	276	(ia64_opcodes_i): Add instructions for tf.
	277
	278	* ia64-opc.h (IMMU5b): New.
	279
	280	* ia64-asmtab.c: Regenerated.
	281
19a7219f L	282	2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
	283
	284	* ia64-gen.c: Update copyright years.
	285	* ia64-opc-b.c: Likewise.
	286
7f3dfb9c L	287	2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
	288
	289	* ia64-gen.c (lookup_regindex): Handle ".vm".
	290	(print_dependency_table): Handle '\"'.
	291
	292	* ia64-ic.tbl: Updated from SDM 2.2.
	293	* ia64-raw.tbl: Likewise.
	294	* ia64-waw.tbl: Likewise.
	295	* ia64-asmtab.c: Regenerated.
	296
	297	* ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
	298
d70c5fc7 NC	299	2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
	300	Anil Paranjape <anilp1@kpitcummins.com>
	301	Shilin Shakti <shilins@kpitcummins.com>
	302
	303	* xc16x-desc.h: New file
	304	* xc16x-desc.c: New file
	305	* xc16x-opc.h: New file
	306	* xc16x-opc.c: New file
	307	* xc16x-ibld.c: New file
	308	* xc16x-asm.c: New file
	309	* xc16x-dis.c: New file
	310	* Makefile.am: Entries for xc16x
	311	* Makefile.in: Regenerate
	312	* cofigure.in: Add xc16x target information.
	313	* configure: Regenerate.
	314	* disassemble.c: Add xc16x target information.
	315
a1cfb73e L	316	2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
	317
	318	* i386-dis.c (dis386_twobyte): Use "movZ" for debug register
	319	moves.
	320
6dd5059a L	321	2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
	322
	323	* i386-dis.c ('Z'): Add a new macro.
	324	(dis386_twobyte): Use "movZ" for control register moves.
	325
8536c657 NC	326	2006-02-10 Nick Clifton <nickc@redhat.com>
	327
	328	* iq2000-asm.c: Regenerate.
	329
266abb8f NS	330	2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
	331
	332	* m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
	333
f1a64f49 DU	334	2006-01-26 David Ung <davidu@mips.com>
	335
	336	* mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
	337	ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
	338	floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
	339	nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
	340	rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
	341
9e919b5f AM	342	2006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
	343
	344	* z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
	345	ld_d_r, pref_xd_cb): Use signed char to hold data to be
	346	disassembled.
	347	* z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
	348	buffer overflows when disassembling instructions like
	349	ld (ix+123),0x23
	350	* z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
	351	operand, if the offset is negative.
	352
c9021189 AM	353	2006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
	354
	355	* z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
	356	unsigned char to hold data to be disassembled.
	357
d99b6465 AS	358	2006-01-17 Andreas Schwab <schwab@suse.de>
	359
	360	PR binutils/1486
	361	* disassemble.c (disassemble_init_for_target): Set
	362	disassembler_needs_relocs for bfd_arch_arm.
	363
c2fe9327 PB	364	2006-01-16 Paul Brook <paul@codesourcery.com>
c2fe9327 PB	365
e88d958a	366	* m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
c2fe9327 PB	367	f?add?, and f?sub? instructions.
c2fe9327 PB	368
32fba81d NC	369	2006-01-16 Nick Clifton <nickc@redhat.com>
	370
	371	* po/zh_CN.po: New Chinese (simplified) translation.
	372	* configure.in (ALL_LINGUAS): Add "zh_CH".
	373	* configure: Regenerate.
	374
1b3a26b5 PB	375	2006-01-05 Paul Brook <paul@codesourcery.com>
	376
	377	* m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
	378
db313fa6 DD	379	2006-01-06 DJ Delorie <dj@redhat.com>
	380
	381	* m32c-desc.c: Regenerate.
	382	* m32c-opc.c: Regenerate.
	383	* m32c-opc.h: Regenerate.
	384
54d46aca DD	385	2006-01-03 DJ Delorie <dj@redhat.com>
	386
	387	* cgen-ibld.in (extract_normal): Avoid memory range errors.
	388	* m32c-ibld.c: Regenerated.
	389
e88d958a	390	For older changes see ChangeLog-2005
252b5132 RH	391	\f
252b5132 RH	392	Local Variables:
2f6d2f85 NC	393	mode: change-log
	394	left-margin: 8
	395	fill-column: 74
252b5132 RH	396	version-control: never
252b5132 RH	397	End: