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Remove Kaz Kojima as SH maintainer.
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
f91d48de
KC		 12017-05-03 Kito Cheng <kito.cheng@gmail.com>
2
3 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
4
43e379d7
MC		 52017-05-01 Michael Clark <michaeljclark@mac.com>
6
7 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
8 register.
9
a4ddc54e
MR		 102017-05-02 Maciej W. Rozycki <macro@imgtec.com>
11
12 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
13 and branches and not synthetic data instructions.
14
fe50e98c
BE		 152017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
16
17 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
18
126124cc
CZ		 192017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
20
21 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
22 * arc-opc.c (insert_r13el): New function.
23 (R13_EL): Define.
24 * arc-tbl.h: Add new enter/leave variants.
25
be6a24d8
CZ		 262017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
27
28 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
29
0348fd79
MR		 302017-04-25 Maciej W. Rozycki <macro@imgtec.com>
31
32 * mips-dis.c (print_mips_disassembler_options): Add
33 `no-aliases'.
34
6e3d1f07
MR		 352017-04-25 Maciej W. Rozycki <macro@imgtec.com>
36
37 * mips16-opc.c (AL): New macro.
38 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
39 of "ld" and "lw" as aliases.
40
957f6b39
TC		 412017-04-24 Tamar Christina <tamar.christina@arm.com>
42
43 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
44 arguments.
45
a8cc8a54
AM		 462017-04-22 Alexander Fedotov <alfedotov@gmail.com>
47 Alan Modra <amodra@gmail.com>
48
49 * ppc-opc.c (ELEV): Define.
50 (vle_opcodes): Add se_rfgi and e_sc.
51 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
52 for E200Z4.
53
3ab87b68
JM		 542017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
55
56 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
57
792f174f
NC		 582017-04-21 Nick Clifton <nickc@redhat.com>
59
60 PR binutils/21380
61 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
62 LD3R and LD4R.
63
42742084
AM		 642017-04-13 Alan Modra <amodra@gmail.com>
65
66 * epiphany-desc.c: Regenerate.
67 * fr30-desc.c: Regenerate.
68 * frv-desc.c: Regenerate.
69 * ip2k-desc.c: Regenerate.
70 * iq2000-desc.c: Regenerate.
71 * lm32-desc.c: Regenerate.
72 * m32c-desc.c: Regenerate.
73 * m32r-desc.c: Regenerate.
74 * mep-desc.c: Regenerate.
75 * mt-desc.c: Regenerate.
76 * or1k-desc.c: Regenerate.
77 * xc16x-desc.c: Regenerate.
78 * xstormy16-desc.c: Regenerate.
79
9a85b496
AM		 802017-04-11 Alan Modra <amodra@gmail.com>
81
ef85eab0 82 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 83 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
84 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 85 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
86 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 87 (PPCVSX2): Define as PPC_OPCODE_POWER8.
88 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 89 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 90 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 91
62adc510
AM		 922017-04-10 Alan Modra <amodra@gmail.com>
93
94 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
95 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
96 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
97 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
98
aa808707
PC		 992017-04-09 Pip Cet <pipcet@gmail.com>
100
101 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
102 appropriate floating-point precision directly.
103
ac8f0f72
AM		 1042017-04-07 Alan Modra <amodra@gmail.com>
105
106 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
107 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
108 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
109 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
110 vector instructions with E6500 not PPCVEC2.
111
62ecb94c
PC		 1122017-04-06 Pip Cet <pipcet@gmail.com>
113
114 * Makefile.am: Add wasm32-dis.c.
115 * configure.ac: Add wasm32-dis.c to wasm32 target.
116 * disassemble.c: Add wasm32 disassembler code.
117 * wasm32-dis.c: New file.
118 * Makefile.in: Regenerate.
119 * configure: Regenerate.
120 * po/POTFILES.in: Regenerate.
121 * po/opcodes.pot: Regenerate.
122
f995bbe8
PA		 1232017-04-05 Pedro Alves <palves@redhat.com>
124
125 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
126 * arm-dis.c (parse_arm_disassembler_options): Constify.
127 * ppc-dis.c (powerpc_init_dialect): Constify local.
128 * vax-dis.c (parse_disassembler_options): Constify.
129
b5292032
PD		 1302017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
131
132 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
133 RISCV_GP_SYMBOL.
134
f96bd6c2
PC		 1352017-03-30 Pip Cet <pipcet@gmail.com>
136
137 * configure.ac: Add (empty) bfd_wasm32_arch target.
138 * configure: Regenerate
139 * po/opcodes.pot: Regenerate.
140
f7c514a3
JM		 1412017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
142
143 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
144 OSA2015.
145 * opcodes/sparc-opc.c (asi_table): New ASIs.
146
52be03fd
AM		 1472017-03-29 Alan Modra <amodra@gmail.com>
148
149 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
150 "raw" option.
151 (lookup_powerpc): Don't special case -1 dialect. Handle
152 PPC_OPCODE_RAW.
153 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
154 lookup_powerpc call, pass it on second.
155
9b753937
AM		 1562017-03-27 Alan Modra <amodra@gmail.com>
157
158 PR 21303
159 * ppc-dis.c (struct ppc_mopt): Comment.
160 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
161
c0c31e91
RZ		 1622017-03-27 Rinat Zelig <rinat@mellanox.com>
163
164 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
165 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
166 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
167 (insert_nps_misc_imm_offset): New function.
168 (extract_nps_misc imm_offset): New function.
169 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
170 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
171
2253c8f0
AK		 1722017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
173
174 * s390-mkopc.c (main): Remove vx2 check.
175 * s390-opc.txt: Remove vx2 instruction flags.
176
645d3342
RZ		 1772017-03-21 Rinat Zelig <rinat@mellanox.com>
178
179 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
180 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
181 (insert_nps_imm_offset): New function.
182 (extract_nps_imm_offset): New function.
183 (insert_nps_imm_entry): New function.
184 (extract_nps_imm_entry): New function.
185
4b94dd2d
AM		 1862017-03-17 Alan Modra <amodra@gmail.com>
187
188 PR 21248
189 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
190 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
191 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
192
b416fe87
KC		 1932017-03-14 Kito Cheng <kito.cheng@gmail.com>
194
195 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
196 <c.andi>: Likewise.
197 <c.addiw> Likewise.
198
03b039a5
KC		 1992017-03-14 Kito Cheng <kito.cheng@gmail.com>
200
201 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
202
2c232b83
AW		 2032017-03-13 Andrew Waterman <andrew@sifive.com>
204
205 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
206 <srl> Likewise.
207 <srai> Likewise.
208 <sra> Likewise.
209
86fa6981
L		 2102017-03-09 H.J. Lu <hongjiu.lu@intel.com>
211
212 * i386-gen.c (opcode_modifiers): Replace S with Load.
213 * i386-opc.h (S): Removed.
214 (Load): New.
215 (i386_opcode_modifier): Replace s with load.
216 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
217 and {evex}. Replace S with Load.
218 * i386-tbl.h: Regenerated.
219
c1fe188b
L		 2202017-03-09 H.J. Lu <hongjiu.lu@intel.com>
221
222 * i386-opc.tbl: Use CpuCET on rdsspq.
223 * i386-tbl.h: Regenerated.
224
4b8b687e
PB		 2252017-03-08 Peter Bergner <bergner@vnet.ibm.com>
226
227 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
228 <vsx>: Do not use PPC_OPCODE_VSX3;
229
1437d063
PB		 2302017-03-08 Peter Bergner <bergner@vnet.ibm.com>
231
232 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
233
603555e5
L		 2342017-03-06 H.J. Lu <hongjiu.lu@intel.com>
235
236 * i386-dis.c (REG_0F1E_MOD_3): New enum.
237 (MOD_0F1E_PREFIX_1): Likewise.
238 (MOD_0F38F5_PREFIX_2): Likewise.
239 (MOD_0F38F6_PREFIX_0): Likewise.
240 (RM_0F1E_MOD_3_REG_7): Likewise.
241 (PREFIX_MOD_0_0F01_REG_5): Likewise.
242 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
243 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
244 (PREFIX_0F1E): Likewise.
245 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
246 (PREFIX_0F38F5): Likewise.
247 (dis386_twobyte): Use PREFIX_0F1E.
248 (reg_table): Add REG_0F1E_MOD_3.
249 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
250 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
251 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
252 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
253 (three_byte_table): Use PREFIX_0F38F5.
254 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
255 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
256 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
257 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
258 PREFIX_MOD_3_0F01_REG_5_RM_2.
259 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
260 (cpu_flags): Add CpuCET.
261 * i386-opc.h (CpuCET): New enum.
262 (CpuUnused): Commented out.
263 (i386_cpu_flags): Add cpucet.
264 * i386-opc.tbl: Add Intel CET instructions.
265 * i386-init.h: Regenerated.
266 * i386-tbl.h: Likewise.
267
73f07bff
AM		 2682017-03-06 Alan Modra <amodra@gmail.com>
269
270 PR 21124
271 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
272 (extract_raq, extract_ras, extract_rbx): New functions.
273 (powerpc_operands): Use opposite corresponding insert function.
274 (Q_MASK): Define.
275 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
276 register restriction.
277
65b48a81
PB		 2782017-02-28 Peter Bergner <bergner@vnet.ibm.com>
279
280 * disassemble.c Include "safe-ctype.h".
281 (disassemble_init_for_target): Handle s390 init.
282 (remove_whitespace_and_extra_commas): New function.
283 (disassembler_options_cmp): Likewise.
284 * arm-dis.c: Include "libiberty.h".
285 (NUM_ELEM): Delete.
286 (regnames): Use long disassembler style names.
287 Add force-thumb and no-force-thumb options.
288 (NUM_ARM_REGNAMES): Rename from this...
289 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
290 (get_arm_regname_num_options): Delete.
291 (set_arm_regname_option): Likewise.
292 (get_arm_regnames): Likewise.
293 (parse_disassembler_options): Likewise.
294 (parse_arm_disassembler_option): Rename from this...
295 (parse_arm_disassembler_options): ...to this. Make static.
296 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
297 (print_insn): Use parse_arm_disassembler_options.
298 (disassembler_options_arm): New function.
299 (print_arm_disassembler_options): Handle updated regnames.
300 * ppc-dis.c: Include "libiberty.h".
301 (ppc_opts): Add "32" and "64" entries.
302 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
303 (powerpc_init_dialect): Add break to switch statement.
304 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
305 (disassembler_options_powerpc): New function.
306 (print_ppc_disassembler_options): Use ARRAY_SIZE.
307 Remove printing of "32" and "64".
308 * s390-dis.c: Include "libiberty.h".
309 (init_flag): Remove unneeded variable.
310 (struct s390_options_t): New structure type.
311 (options): New structure.
312 (init_disasm): Rename from this...
313 (disassemble_init_s390): ...to this. Add initializations for
314 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
315 (print_insn_s390): Delete call to init_disasm.
316 (disassembler_options_s390): New function.
317 (print_s390_disassembler_options): Print using information from
318 struct 'options'.
319 * po/opcodes.pot: Regenerate.
320
15c7c1d8
JB		 3212017-02-28 Jan Beulich <jbeulich@suse.com>
322
323 * i386-dis.c (PCMPESTR_Fixup): New.
324 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
325 (prefix_table): Use PCMPESTR_Fixup.
326 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
327 PCMPESTR_Fixup.
328 (vex_w_table): Delete VPCMPESTR{I,M} entries.
329 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
330 Split 64-bit and non-64-bit variants.
331 * opcodes/i386-tbl.h: Re-generate.
332
582e12bf
RS		 3332017-02-24 Richard Sandiford <richard.sandiford@arm.com>
334
335 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
336 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
337 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
338 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
339 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
340 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
341 (OP_SVE_V_HSD): New macros.
342 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
343 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
344 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
345 (aarch64_opcode_table): Add new SVE instructions.
346 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
347 for rotation operands. Add new SVE operands.
348 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
349 (ins_sve_quad_index): Likewise.
350 (ins_imm_rotate): Split into...
351 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
352 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
353 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
354 functions.
355 (aarch64_ins_sve_addr_ri_s4): New function.
356 (aarch64_ins_sve_quad_index): Likewise.
357 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
358 * aarch64-asm-2.c: Regenerate.
359 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
360 (ext_sve_quad_index): Likewise.
361 (ext_imm_rotate): Split into...
362 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
363 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
364 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
365 functions.
366 (aarch64_ext_sve_addr_ri_s4): New function.
367 (aarch64_ext_sve_quad_index): Likewise.
368 (aarch64_ext_sve_index): Allow quad indices.
369 (do_misc_decoding): Likewise.
370 * aarch64-dis-2.c: Regenerate.
371 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
372 aarch64_field_kinds.
373 (OPD_F_OD_MASK): Widen by one bit.
374 (OPD_F_NO_ZR): Bump accordingly.
375 (get_operand_field_width): New function.
376 * aarch64-opc.c (fields): Add new SVE fields.
377 (operand_general_constraint_met_p): Handle new SVE operands.
378 (aarch64_print_operand): Likewise.
379 * aarch64-opc-2.c: Regenerate.
380
f482d304
RS		 3812017-02-24 Richard Sandiford <richard.sandiford@arm.com>
382
383 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
384 (aarch64_feature_compnum): ...this.
385 (SIMD_V8_3): Replace with...
386 (COMPNUM): ...this.
387 (CNUM_INSN): New macro.
388 (aarch64_opcode_table): Use it for the complex number instructions.
389
7db2c588
JB		 3902017-02-24 Jan Beulich <jbeulich@suse.com>
391
392 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
393
1e9d41d4
SL		 3942017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
395
396 Add support for associating SPARC ASIs with an architecture level.
397 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
398 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
399 decoding of SPARC ASIs.
400
53c4d625
JB		 4012017-02-23 Jan Beulich <jbeulich@suse.com>
402
403 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
404 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
405
11648de5
JB		 4062017-02-21 Jan Beulich <jbeulich@suse.com>
407
408 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
409 1 (instead of to itself). Correct typo.
410
f98d33be
AW		 4112017-02-14 Andrew Waterman <andrew@sifive.com>
412
413 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
414 pseudoinstructions.
415
773fb663
RS		 4162017-02-15 Richard Sandiford <richard.sandiford@arm.com>
417
418 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
419 (aarch64_sys_reg_supported_p): Handle them.
420
cc07cda6
CZ		 4212017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
422
423 * arc-opc.c (UIMM6_20R): Define.
424 (SIMM12_20): Use above.
425 (SIMM12_20R): Define.
426 (SIMM3_5_S): Use above.
427 (UIMM7_A32_11R_S): Define.
428 (UIMM7_9_S): Use above.
429 (UIMM3_13R_S): Define.
430 (SIMM11_A32_7_S): Use above.
431 (SIMM9_8R): Define.
432 (UIMM10_A32_8_S): Use above.
433 (UIMM8_8R_S): Define.
434 (W6): Use above.
435 (arc_relax_opcodes): Use all above defines.
436
66a5a740
VG		 4372017-02-15 Vineet Gupta <vgupta@synopsys.com>
438
439 * arc-regs.h: Distinguish some of the registers different on
440 ARC700 and HS38 cpus.
441
7e0de605
AM		 4422017-02-14 Alan Modra <amodra@gmail.com>
443
444 PR 21118
445 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
446 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
447
54064fdb
AM		 4482017-02-11 Stafford Horne <shorne@gmail.com>
449 Alan Modra <amodra@gmail.com>
450
451 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
452 Use insn_bytes_value and insn_int_value directly instead. Don't
453 free allocated memory until function exit.
454
dce75bf9
NP		 4552017-02-10 Nicholas Piggin <npiggin@gmail.com>
456
457 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
458
1b7e3d2f
NC		 4592017-02-03 Nick Clifton <nickc@redhat.com>
460
461 PR 21096
462 * aarch64-opc.c (print_register_list): Ensure that the register
463 list index will fir into the tb buffer.
464 (print_register_offset_address): Likewise.
465 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
466
8ec5cf65
AD		 4672017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
468
469 PR 21056
470 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
471 instructions when the previous fetch packet ends with a 32-bit
472 instruction.
473
a1aa5e81
DD		 4742017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
475
476 * pru-opc.c: Remove vague reference to a future GDB port.
477
add3afb2
NC		 4782017-01-20 Nick Clifton <nickc@redhat.com>
479
480 * po/ga.po: Updated Irish translation.
481
c13a63b0
SN		 4822017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
483
484 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
485
9608051a
YQ		 4862017-01-13 Yao Qi <yao.qi@linaro.org>
487
488 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
489 if FETCH_DATA returns 0.
490 (m68k_scan_mask): Likewise.
491 (print_insn_m68k): Update code to handle -1 return value.
492
f622ea96
YQ		 4932017-01-13 Yao Qi <yao.qi@linaro.org>
494
495 * m68k-dis.c (enum print_insn_arg_error): New.
496 (NEXTBYTE): Replace -3 with
497 PRINT_INSN_ARG_MEMORY_ERROR.
498 (NEXTULONG): Likewise.
499 (NEXTSINGLE): Likewise.
500 (NEXTDOUBLE): Likewise.
501 (NEXTDOUBLE): Likewise.
502 (NEXTPACKED): Likewise.
503 (FETCH_ARG): Likewise.
504 (FETCH_DATA): Update comments.
505 (print_insn_arg): Update comments. Replace magic numbers with
506 enum.
507 (match_insn_m68k): Likewise.
508
620214f7
IT		 5092017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
510
511 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
512 * i386-dis-evex.h (evex_table): Updated.
513 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
514 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
515 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
516 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
517 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
518 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
519 * i386-init.h: Regenerate.
520 * i386-tbl.h: Ditto.
521
d95014a2
YQ		 5222017-01-12 Yao Qi <yao.qi@linaro.org>
523
524 * msp430-dis.c (msp430_singleoperand): Return -1 if
525 msp430dis_opcode_signed returns false.
526 (msp430_doubleoperand): Likewise.
527 (msp430_branchinstr): Return -1 if
528 msp430dis_opcode_unsigned returns false.
529 (msp430x_calla_instr): Likewise.
530 (print_insn_msp430): Likewise.
531
0ae60c3e
NC		 5322017-01-05 Nick Clifton <nickc@redhat.com>
533
534 PR 20946
535 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
536 could not be matched.
537 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
538 NULL.
539
d74d4880
SN		 5402017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
541
542 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
543 (aarch64_opcode_table): Use RCPC_INSN.
544
cc917fd9
KC		 5452017-01-03 Kito Cheng <kito.cheng@gmail.com>
546
547 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
548 extension.
549 * riscv-opcodes/all-opcodes: Likewise.
550
b52d3cfc
DP		 5512017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
552
553 * riscv-dis.c (print_insn_args): Add fall through comment.
554
f90c58d5
NC		 5552017-01-03 Nick Clifton <nickc@redhat.com>
556
557 * po/sr.po: New Serbian translation.
558 * configure.ac (ALL_LINGUAS): Add sr.
559 * configure: Regenerate.
560
f47b0d4a
AM		 5612017-01-02 Alan Modra <amodra@gmail.com>
562
563 * epiphany-desc.h: Regenerate.
564 * epiphany-opc.h: Regenerate.
565 * fr30-desc.h: Regenerate.
566 * fr30-opc.h: Regenerate.
567 * frv-desc.h: Regenerate.
568 * frv-opc.h: Regenerate.
569 * ip2k-desc.h: Regenerate.
570 * ip2k-opc.h: Regenerate.
571 * iq2000-desc.h: Regenerate.
572 * iq2000-opc.h: Regenerate.
573 * lm32-desc.h: Regenerate.
574 * lm32-opc.h: Regenerate.
575 * m32c-desc.h: Regenerate.
576 * m32c-opc.h: Regenerate.
577 * m32r-desc.h: Regenerate.
578 * m32r-opc.h: Regenerate.
579 * mep-desc.h: Regenerate.
580 * mep-opc.h: Regenerate.
581 * mt-desc.h: Regenerate.
582 * mt-opc.h: Regenerate.
583 * or1k-desc.h: Regenerate.
584 * or1k-opc.h: Regenerate.
585 * xc16x-desc.h: Regenerate.
586 * xc16x-opc.h: Regenerate.
587 * xstormy16-desc.h: Regenerate.
588 * xstormy16-opc.h: Regenerate.
589
2571583a
AM		 5902017-01-02 Alan Modra <amodra@gmail.com>
591
592 Update year range in copyright notice of all files.
593
5c1ad6b5 594For older changes see ChangeLog-2016
3499769a 595\f
5c1ad6b5 596Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 597
598Copying and distribution of this file, with or without modification,
599are permitted in any medium without royalty provided the copyright
600notice and this notice are preserved.
601
602Local Variables:
603mode: change-log
604left-margin: 8
605fill-column: 74
606version-control: never
607End:
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