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infcall-nested-structs: Test up to five fields
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
9cf7e568
AM		 12018-08-21 Alan Modra <amodra@gmail.com>
2
3 * ppc-dis.c (operand_value_powerpc): Init "invalid".
4 (skip_optional_operands): Count optional operands, and update
5 ppc_optional_operand_value call.
6 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
7 (extract_vlensi): Likewise.
8 (extract_fxm): Return default value for missing optional operand.
9 (extract_ls, extract_raq, extract_tbr): Likewise.
10 (insert_sxl, extract_sxl): New functions.
11 (insert_esync, extract_esync): Remove Power9 handling and simplify.
12 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
13 flag and extra entry.
14 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
15 extract_sxl.
16
d203b41a 172018-08-20 Alan Modra <amodra@gmail.com>
f4107842 18
d203b41a 19 * sh-opc.h (MASK): Simplify.
f4107842 20
08a8fe2f 212018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 22
d203b41a
AM		 23 * s12z-dis.c (bm_decode): Deal with cases where the mode is
24 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 25 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 26
08a8fe2f 272018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 28
29 * s12z.h: Delete.
7ba3ba91 30
1bc60e56
L		 312018-08-14 H.J. Lu <hongjiu.lu@intel.com>
32
33 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
34 address with the addr32 prefix and without base nor index
35 registers.
36
d871f3f4
L		 372018-08-11 H.J. Lu <hongjiu.lu@intel.com>
38
39 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
40 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
41 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
42 (cpu_flags): Add CpuCMOV and CpuFXSR.
43 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
44 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
45 * i386-init.h: Regenerated.
46 * i386-tbl.h: Likewise.
47
b6523c37 482018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
49
50 * arc-regs.h: Update auxiliary registers.
51
e968fc9b
JB		 522018-08-06 Jan Beulich <jbeulich@suse.com>
53
54 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
55 (RegIP, RegIZ): Define.
56 * i386-reg.tbl: Adjust comments.
57 (rip): Use Qword instead of BaseIndex. Use RegIP.
58 (eip): Use Dword instead of BaseIndex. Use RegIP.
59 (riz): Add Qword. Use RegIZ.
60 (eiz): Add Dword. Use RegIZ.
61 * i386-tbl.h: Re-generate.
62
dbf8be89
JB		 632018-08-03 Jan Beulich <jbeulich@suse.com>
64
65 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
66 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
67 vpmovzxdq, vpmovzxwd): Remove NoRex64.
68 * i386-tbl.h: Re-generate.
69
c48dadc9
JB		 702018-08-03 Jan Beulich <jbeulich@suse.com>
71
72 * i386-gen.c (operand_types): Remove Mem field.
73 * i386-opc.h (union i386_operand_type): Remove mem field.
74 * i386-init.h, i386-tbl.h: Re-generate.
75
cb86a42a
AM		 762018-08-01 Alan Modra <amodra@gmail.com>
77
78 * po/POTFILES.in: Regenerate.
79
07cc0450
NC		 802018-07-31 Nick Clifton <nickc@redhat.com>
81
82 * po/sv.po: Updated Swedish translation.
83
1424ad86
JB		 842018-07-31 Jan Beulich <jbeulich@suse.com>
85
86 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
87 * i386-init.h, i386-tbl.h: Re-generate.
88
ae2387fe
JB		 892018-07-31 Jan Beulich <jbeulich@suse.com>
90
91 * i386-opc.h (ZEROING_MASKING) Rename to ...
92 (DYNAMIC_MASKING): ... this. Adjust comment.
93 * i386-opc.tbl (MaskingMorZ): Define.
94 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
95 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
96 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
97 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
98 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
99 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
100 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
101 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
102 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
103
6ff00b5e
JB		 1042018-07-31 Jan Beulich <jbeulich@suse.com>
105
106 * i386-opc.tbl: Use element rather than vector size for AVX512*
107 scatter/gather insns.
108 * i386-tbl.h: Re-generate.
109
e951d5ca
JB		 1102018-07-31 Jan Beulich <jbeulich@suse.com>
111
112 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
113 (cpu_flags): Drop CpuVREX.
114 * i386-opc.h (CpuVREX): Delete.
115 (union i386_cpu_flags): Remove cpuvrex.
116 * i386-init.h, i386-tbl.h: Re-generate.
117
eb41b248
JW		 1182018-07-30 Jim Wilson <jimw@sifive.com>
119
120 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
121 fields.
122 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
123
b8891f8d
AJ		 1242018-07-30 Andrew Jenner <andrew@codesourcery.com>
125
126 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
127 * Makefile.in: Regenerated.
128 * configure.ac: Add C-SKY.
129 * configure: Regenerated.
130 * csky-dis.c: New file.
131 * csky-opc.h: New file.
132 * disassemble.c (ARCH_csky): Define.
133 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
134 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
135
16065af1
AM		 1362018-07-27 Alan Modra <amodra@gmail.com>
137
138 * ppc-opc.c (insert_sprbat): Correct function parameter and
139 return type.
140 (extract_sprbat): Likewise, variable too.
141
fa758a70
AC		 1422018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
143 Alan Modra <amodra@gmail.com>
144
145 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
146 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
147 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
148 support disjointed BAT.
149 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
150 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
151 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
152
4a1b91ea
L		 1532018-07-25 H.J. Lu <hongjiu.lu@intel.com>
154 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
155
156 * i386-gen.c (adjust_broadcast_modifier): New function.
157 (process_i386_opcode_modifier): Add an argument for operands.
158 Adjust the Broadcast value based on operands.
159 (output_i386_opcode): Pass operand_types to
160 process_i386_opcode_modifier.
161 (process_i386_opcodes): Pass NULL as operands to
162 process_i386_opcode_modifier.
163 * i386-opc.h (BYTE_BROADCAST): New.
164 (WORD_BROADCAST): Likewise.
165 (DWORD_BROADCAST): Likewise.
166 (QWORD_BROADCAST): Likewise.
167 (i386_opcode_modifier): Expand broadcast to 3 bits.
168 * i386-tbl.h: Regenerated.
169
67ce483b
AM		 1702018-07-24 Alan Modra <amodra@gmail.com>
171
172 PR 23430
173 * or1k-desc.h: Regenerate.
174
4174bfff
JB		 1752018-07-24 Jan Beulich <jbeulich@suse.com>
176
177 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
178 vcvtusi2ss, and vcvtusi2sd.
179 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
180 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
181 * i386-tbl.h: Re-generate.
182
04e65276
CZ		 1832018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
184
185 * arc-opc.c (extract_w6): Fix extending the sign.
186
47e6f81c
CZ		 1872018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
188
189 * arc-tbl.h (vewt): Allow it for ARC EM family.
190
bb71536f
AM		 1912018-07-23 Alan Modra <amodra@gmail.com>
192
193 PR 23419
194 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
195 opcode variants for mtspr/mfspr encodings.
196
8095d2f7
CX		 1972018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
198 Maciej W. Rozycki <macro@mips.com>
199
200 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
201 loongson3a descriptors.
202 (parse_mips_ase_option): Handle -M loongson-mmi option.
203 (print_mips_disassembler_options): Document -M loongson-mmi.
204 * mips-opc.c (LMMI): New macro.
205 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
206 instructions.
207
5f32791e
JB		 2082018-07-19 Jan Beulich <jbeulich@suse.com>
209
210 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
211 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
212 IgnoreSize and [XYZ]MMword where applicable.
213 * i386-tbl.h: Re-generate.
214
625cbd7a
JB		 2152018-07-19 Jan Beulich <jbeulich@suse.com>
216
217 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
218 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
219 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
220 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
221 * i386-tbl.h: Re-generate.
222
86b15c32
JB		 2232018-07-19 Jan Beulich <jbeulich@suse.com>
224
225 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
226 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
227 VPCLMULQDQ templates into their respective AVX512VL counterparts
228 where possible, using Disp8ShiftVL and CheckRegSize instead of
229 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
230 * i386-tbl.h: Re-generate.
231
cf769ed5
JB		 2322018-07-19 Jan Beulich <jbeulich@suse.com>
233
234 * i386-opc.tbl: Fold AVX512DQ templates into their respective
235 AVX512VL counterparts where possible, using Disp8ShiftVL and
236 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
237 IgnoreSize) as appropriate.
238 * i386-tbl.h: Re-generate.
239
8282b7ad
JB		 2402018-07-19 Jan Beulich <jbeulich@suse.com>
241
242 * i386-opc.tbl: Fold AVX512BW templates into their respective
243 AVX512VL counterparts where possible, using Disp8ShiftVL and
244 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
245 IgnoreSize) as appropriate.
246 * i386-tbl.h: Re-generate.
247
755908cc
JB		 2482018-07-19 Jan Beulich <jbeulich@suse.com>
249
250 * i386-opc.tbl: Fold AVX512CD templates into their respective
251 AVX512VL counterparts where possible, using Disp8ShiftVL and
252 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
253 IgnoreSize) as appropriate.
254 * i386-tbl.h: Re-generate.
255
7091c612
JB		 2562018-07-19 Jan Beulich <jbeulich@suse.com>
257
258 * i386-opc.h (DISP8_SHIFT_VL): New.
259 * i386-opc.tbl (Disp8ShiftVL): Define.
260 (various): Fold AVX512VL templates into their respective
261 AVX512F counterparts where possible, using Disp8ShiftVL and
262 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
263 IgnoreSize) as appropriate.
264 * i386-tbl.h: Re-generate.
265
c30be56e
JB		 2662018-07-19 Jan Beulich <jbeulich@suse.com>
267
268 * Makefile.am: Change dependencies and rule for
269 $(srcdir)/i386-init.h.
270 * Makefile.in: Re-generate.
271 * i386-gen.c (process_i386_opcodes): New local variable
272 "marker". Drop opening of input file. Recognize marker and line
273 number directives.
274 * i386-opc.tbl (OPCODE_I386_H): Define.
275 (i386-opc.h): Include it.
276 (None): Undefine.
277
11a322db
L		 2782018-07-18 H.J. Lu <hongjiu.lu@intel.com>
279
280 PR gas/23418
281 * i386-opc.h (Byte): Update comments.
282 (Word): Likewise.
283 (Dword): Likewise.
284 (Fword): Likewise.
285 (Qword): Likewise.
286 (Tbyte): Likewise.
287 (Xmmword): Likewise.
288 (Ymmword): Likewise.
289 (Zmmword): Likewise.
290 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
291 vcvttps2uqq.
292 * i386-tbl.h: Regenerated.
293
cde3679e
NC		 2942018-07-12 Sudakshina Das <sudi.das@arm.com>
295
296 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
297 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
298 * aarch64-asm-2.c: Regenerate.
299 * aarch64-dis-2.c: Regenerate.
300 * aarch64-opc-2.c: Regenerate.
301
45a28947
TC		 3022018-07-12 Tamar Christina <tamar.christina@arm.com>
303
304 PR binutils/23192
305 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
306 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
307 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
308 sqdmulh, sqrdmulh): Use Em16.
309
c597cc3d
SD		 3102018-07-11 Sudakshina Das <sudi.das@arm.com>
311
312 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
313 csdb together with them.
314 (thumb32_opcodes): Likewise.
315
a79eaed6
JB		 3162018-07-11 Jan Beulich <jbeulich@suse.com>
317
318 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
319 requiring 32-bit registers as operands 2 and 3. Improve
320 comments.
321 (mwait, mwaitx): Fold templates. Improve comments.
322 OPERAND_TYPE_INOUTPORTREG.
323 * i386-tbl.h: Re-generate.
324
2fb5be8d
JB		 3252018-07-11 Jan Beulich <jbeulich@suse.com>
326
327 * i386-gen.c (operand_type_init): Remove
328 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
329 OPERAND_TYPE_INOUTPORTREG.
330 * i386-init.h: Re-generate.
331
7f5cad30
JB		 3322018-07-11 Jan Beulich <jbeulich@suse.com>
333
334 * i386-opc.tbl (wrssd, wrussd): Add Dword.
335 (wrssq, wrussq): Add Qword.
336 * i386-tbl.h: Re-generate.
337
f0a85b07
JB		 3382018-07-11 Jan Beulich <jbeulich@suse.com>
339
340 * i386-opc.h: Rename OTMax to OTNum.
341 (OTNumOfUints): Adjust calculation.
342 (OTUnused): Directly alias to OTNum.
343
9dcb0ba4
MR		 3442018-07-09 Maciej W. Rozycki <macro@mips.com>
345
346 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
347 `reg_xys'.
348 (lea_reg_xys): Likewise.
349 (print_insn_loop_primitive): Rename `reg' local variable to
350 `reg_dxy'.
351
f311ba7e
TC		 3522018-07-06 Tamar Christina <tamar.christina@arm.com>
353
354 PR binutils/23242
355 * aarch64-tbl.h (ldarh): Fix disassembly mask.
356
cba05feb
TC		 3572018-07-06 Tamar Christina <tamar.christina@arm.com>
358
359 PR binutils/23369
360 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
361 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
362
471b9d15
MR		 3632018-07-02 Maciej W. Rozycki <macro@mips.com>
364
365 PR tdep/8282
366 * mips-dis.c (mips_option_arg_t): New enumeration.
367 (mips_options): New variable.
368 (disassembler_options_mips): New function.
369 (print_mips_disassembler_options): Reimplement in terms of
370 `disassembler_options_mips'.
371 * arm-dis.c (disassembler_options_arm): Adapt to using the
372 `disasm_options_and_args_t' structure.
373 * ppc-dis.c (disassembler_options_powerpc): Likewise.
374 * s390-dis.c (disassembler_options_s390): Likewise.
375
c0c468d5
TP		 3762018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
377
378 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
379 expected result.
380 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
381 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
382 * testsuite/ld-arm/tls-longplt.d: Likewise.
383
369c9167
TC		 3842018-06-29 Tamar Christina <tamar.christina@arm.com>
385
386 PR binutils/23192
387 * aarch64-asm-2.c: Regenerate.
388 * aarch64-dis-2.c: Likewise.
389 * aarch64-opc-2.c: Likewise.
390 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
391 * aarch64-opc.c (operand_general_constraint_met_p,
392 aarch64_print_operand): Likewise.
393 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
394 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
395 fmlal2, fmlsl2.
396 (AARCH64_OPERANDS): Add Em2.
397
30aa1306
NC		 3982018-06-26 Nick Clifton <nickc@redhat.com>
399
400 * po/uk.po: Updated Ukranian translation.
401 * po/de.po: Updated German translation.
402 * po/pt_BR.po: Updated Brazilian Portuguese translation.
403
eca4b721
NC		 4042018-06-26 Nick Clifton <nickc@redhat.com>
405
406 * nfp-dis.c: Fix spelling mistake.
407
71300e2c
NC		 4082018-06-24 Nick Clifton <nickc@redhat.com>
409
410 * configure: Regenerate.
411 * po/opcodes.pot: Regenerate.
412
719d8288
NC		 4132018-06-24 Nick Clifton <nickc@redhat.com>
414
415 2.31 branch created.
416
514cd3a0
TC		 4172018-06-19 Tamar Christina <tamar.christina@arm.com>
418
419 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
420 * aarch64-asm-2.c: Regenerate.
421 * aarch64-dis-2.c: Likewise.
422
385e4d0f
MR		 4232018-06-21 Maciej W. Rozycki <macro@mips.com>
424
425 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
426 `-M ginv' option description.
427
160d1b3d
SH		 4282018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
429
430 PR gas/23305
431 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
432 la and lla.
433
d0ac1c44
SM		 4342018-06-19 Simon Marchi <simon.marchi@ericsson.com>
435
436 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
437 * configure.ac: Remove AC_PREREQ.
438 * Makefile.in: Re-generate.
439 * aclocal.m4: Re-generate.
440 * configure: Re-generate.
441
6f20c942
FS		 4422018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
443
444 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
445 mips64r6 descriptors.
446 (parse_mips_ase_option): Handle -Mginv option.
447 (print_mips_disassembler_options): Document -Mginv.
448 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
449 (GINV): New macro.
450 (mips_opcodes): Define ginvi and ginvt.
451
730c3174
SE		 4522018-06-13 Scott Egerton <scott.egerton@imgtec.com>
453 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
454
455 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
456 * mips-opc.c (CRC, CRC64): New macros.
457 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
458 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
459 crc32cd for CRC64.
460
cb366992
EB		 4612018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
462
463 PR 20319
464 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
465 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
466
ce72cd46
AM		 4672018-06-06 Alan Modra <amodra@gmail.com>
468
469 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
470 setjmp. Move init for some other vars later too.
471
4b8e28c7
MF		 4722018-06-04 Max Filippov <jcmvbkbc@gmail.com>
473
474 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
475 (dis_private): Add new fields for property section tracking.
476 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
477 (xtensa_instruction_fits): New functions.
478 (fetch_data): Bump minimal fetch size to 4.
479 (print_insn_xtensa): Make struct dis_private static.
480 Load and prepare property table on section change.
481 Don't disassemble literals. Don't disassemble instructions that
482 cross property table boundaries.
483
55e99962
L		 4842018-06-01 H.J. Lu <hongjiu.lu@intel.com>
485
486 * configure: Regenerated.
487
733bd0ab
JB		 4882018-06-01 Jan Beulich <jbeulich@suse.com>
489
490 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
491 * i386-tbl.h: Re-generate.
492
dfd27d41
JB		 4932018-06-01 Jan Beulich <jbeulich@suse.com>
494
495 * i386-opc.tbl (sldt, str): Add NoRex64.
496 * i386-tbl.h: Re-generate.
497
64795710
JB		 4982018-06-01 Jan Beulich <jbeulich@suse.com>
499
500 * i386-opc.tbl (invpcid): Add Oword.
501 * i386-tbl.h: Re-generate.
502
030157d8
AM		 5032018-06-01 Alan Modra <amodra@gmail.com>
504
505 * sysdep.h (_bfd_error_handler): Don't declare.
506 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
507 * rl78-decode.opc: Likewise.
508 * msp430-decode.c: Regenerate.
509 * rl78-decode.c: Regenerate.
510
a9660a6f
AP		 5112018-05-30 Amit Pawar <Amit.Pawar@amd.com>
512
513 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
514 * i386-init.h : Regenerated.
515
277eb7f6
AM		 5162018-05-25 Alan Modra <amodra@gmail.com>
517
518 * Makefile.in: Regenerate.
519 * po/POTFILES.in: Regenerate.
520
98553ad3
PB		 5212018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
522
523 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
524 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
525 (insert_bab, extract_bab, insert_btab, extract_btab,
526 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
527 (BAT, BBA VBA RBS XB6S): Delete macros.
528 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
529 (BB, BD, RBX, XC6): Update for new macros.
530 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
531 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
532 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
533 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
534
7b4ae824
JD		 5352018-05-18 John Darrington <john@darrington.wattle.id.au>
536
537 * Makefile.am: Add support for s12z architecture.
538 * configure.ac: Likewise.
539 * disassemble.c: Likewise.
540 * disassemble.h: Likewise.
541 * Makefile.in: Regenerate.
542 * configure: Regenerate.
543 * s12z-dis.c: New file.
544 * s12z.h: New file.
545
29e0f0a1
AM		 5462018-05-18 Alan Modra <amodra@gmail.com>
547
548 * nfp-dis.c: Don't #include libbfd.h.
549 (init_nfp3200_priv): Use bfd_get_section_contents.
550 (nit_nfp6000_mecsr_sec): Likewise.
551
809276d2
NC		 5522018-05-17 Nick Clifton <nickc@redhat.com>
553
554 * po/zh_CN.po: Updated simplified Chinese translation.
555
ff329288
TC		 5562018-05-16 Tamar Christina <tamar.christina@arm.com>
557
558 PR binutils/23109
559 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
560 * aarch64-dis-2.c: Regenerate.
561
f9830ec1
TC		 5622018-05-15 Tamar Christina <tamar.christina@arm.com>
563
564 PR binutils/21446
565 * aarch64-asm.c (opintl.h): Include.
566 (aarch64_ins_sysreg): Enforce read/write constraints.
567 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
568 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
569 (F_REG_READ, F_REG_WRITE): New.
570 * aarch64-opc.c (aarch64_print_operand): Generate notes for
571 AARCH64_OPND_SYSREG.
572 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
573 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
574 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
575 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
576 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
577 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
578 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
579 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
580 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
581 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
582 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
583 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
584 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
585 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
586 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
587 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
588 msr (F_SYS_WRITE), mrs (F_SYS_READ).
589
7d02540a
TC		 5902018-05-15 Tamar Christina <tamar.christina@arm.com>
591
592 PR binutils/21446
593 * aarch64-dis.c (no_notes: New.
594 (parse_aarch64_dis_option): Support notes.
595 (aarch64_decode_insn, print_operands): Likewise.
596 (print_aarch64_disassembler_options): Document notes.
597 * aarch64-opc.c (aarch64_print_operand): Support notes.
598
561a72d4
TC		 5992018-05-15 Tamar Christina <tamar.christina@arm.com>
600
601 PR binutils/21446
602 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
603 and take error struct.
604 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
605 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
606 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
607 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
608 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
609 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
610 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
611 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
612 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
613 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
614 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
615 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
616 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
617 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
618 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
619 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
620 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
621 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
622 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
623 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
624 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
625 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
626 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
627 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
628 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
629 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
630 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
631 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
632 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
633 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
634 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
635 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
636 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
637 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
638 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
639 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
640 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
641 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
642 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
643 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
644 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
645 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
646 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
647 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
648 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
649 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
650 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
651 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
652 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
653 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
654 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
655 (determine_disassembling_preference, aarch64_decode_insn,
656 print_insn_aarch64_word, print_insn_data): Take errors struct.
657 (print_insn_aarch64): Use errors.
658 * aarch64-asm-2.c: Regenerate.
659 * aarch64-dis-2.c: Regenerate.
660 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
661 boolean in aarch64_insert_operan.
662 (print_operand_extractor): Likewise.
663 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
664
1678bd35
FT		 6652018-05-15 Francois H. Theron <francois.theron@netronome.com>
666
667 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
668
06cfb1c8
L		 6692018-05-09 H.J. Lu <hongjiu.lu@intel.com>
670
671 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
672
84f9f8c3
AM		 6732018-05-09 Sebastian Rasmussen <sebras@gmail.com>
674
675 * cr16-opc.c (cr16_instruction): Comment typo fix.
676 * hppa-dis.c (print_insn_hppa): Likewise.
677
e6f372ba
JW		 6782018-05-08 Jim Wilson <jimw@sifive.com>
679
680 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
681 (match_c_slli64, match_srxi_as_c_srxi): New.
682 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
683 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
684 <c.slli, c.srli, c.srai>: Use match_s_slli.
685 <c.slli64, c.srli64, c.srai64>: New.
686
f413a913
AM		 6872018-05-08 Alan Modra <amodra@gmail.com>
688
689 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
690 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
691 partition opcode space for index lookup.
692
a87a6478
PB		 6932018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
694
695 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
696 <insn_length>: ...with this. Update usage.
697 Remove duplicate call to *info->memory_error_func.
698
c0a30a9f
L		 6992018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
700 H.J. Lu <hongjiu.lu@intel.com>
701
702 * i386-dis.c (Gva): New.
703 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
704 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
705 (prefix_table): New instructions (see prefix above).
706 (mod_table): New instructions (see prefix above).
707 (OP_G): Handle va_mode.
708 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
709 CPU_MOVDIR64B_FLAGS.
710 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
711 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
712 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
713 * i386-opc.tbl: Add movidir{i,64b}.
714 * i386-init.h: Regenerated.
715 * i386-tbl.h: Likewise.
716
75c0a438
L		 7172018-05-07 H.J. Lu <hongjiu.lu@intel.com>
718
719 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
720 AddrPrefixOpReg.
721 * i386-opc.h (AddrPrefixOp0): Renamed to ...
722 (AddrPrefixOpReg): This.
723 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
724 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
725
2ceb7719
PB		 7262018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
727
728 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
729 (vle_num_opcodes): Likewise.
730 (spe2_num_opcodes): Likewise.
731 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
732 initialization loop.
733 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
734 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
735 only once.
736
b3ac5c6c
TC		 7372018-05-01 Tamar Christina <tamar.christina@arm.com>
738
739 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
740
fe944acf
FT		 7412018-04-30 Francois H. Theron <francois.theron@netronome.com>
742
743 Makefile.am: Added nfp-dis.c.
744 configure.ac: Added bfd_nfp_arch.
745 disassemble.h: Added print_insn_nfp prototype.
746 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
747 nfp-dis.c: New, for NFP support.
748 po/POTFILES.in: Added nfp-dis.c to the list.
749 Makefile.in: Regenerate.
750 configure: Regenerate.
751
e2195274
JB		 7522018-04-26 Jan Beulich <jbeulich@suse.com>
753
754 * i386-opc.tbl: Fold various non-memory operand AVX512VL
755 templates into their base ones.
756 * i386-tlb.h: Re-generate.
757
59ef5df4
JB		 7582018-04-26 Jan Beulich <jbeulich@suse.com>
759
760 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
761 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
762 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
763 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
764 * i386-init.h: Re-generate.
765
6e041cf4
JB		 7662018-04-26 Jan Beulich <jbeulich@suse.com>
767
768 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
769 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
770 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
771 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
772 comment.
773 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
774 and CpuRegMask.
775 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
776 CpuRegMask: Delete.
777 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
778 cpuregzmm, and cpuregmask.
779 * i386-init.h: Re-generate.
780 * i386-tbl.h: Re-generate.
781
0e0eea78
JB		 7822018-04-26 Jan Beulich <jbeulich@suse.com>
783
784 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
785 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
786 * i386-init.h: Re-generate.
787
2f1bada2
JB		 7882018-04-26 Jan Beulich <jbeulich@suse.com>
789
790 * i386-gen.c (VexImmExt): Delete.
791 * i386-opc.h (VexImmExt, veximmext): Delete.
792 * i386-opc.tbl: Drop all VexImmExt uses.
793 * i386-tlb.h: Re-generate.
794
bacd1457
JB		 7952018-04-25 Jan Beulich <jbeulich@suse.com>
796
797 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
798 register-only forms.
799 * i386-tlb.h: Re-generate.
800
10bba94b
TC		 8012018-04-25 Tamar Christina <tamar.christina@arm.com>
802
803 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
804
c48935d7
IT		 8052018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
806
807 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
808 PREFIX_0F1C.
809 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
810 (cpu_flags): Add CpuCLDEMOTE.
811 * i386-init.h: Regenerate.
812 * i386-opc.h (enum): Add CpuCLDEMOTE,
813 (i386_cpu_flags): Add cpucldemote.
814 * i386-opc.tbl: Add cldemote.
815 * i386-tbl.h: Regenerate.
816
211dc24b
AM		 8172018-04-16 Alan Modra <amodra@gmail.com>
818
819 * Makefile.am: Remove sh5 and sh64 support.
820 * configure.ac: Likewise.
821 * disassemble.c: Likewise.
822 * disassemble.h: Likewise.
823 * sh-dis.c: Likewise.
824 * sh64-dis.c: Delete.
825 * sh64-opc.c: Delete.
826 * sh64-opc.h: Delete.
827 * Makefile.in: Regenerate.
828 * configure: Regenerate.
829 * po/POTFILES.in: Regenerate.
830
a9a4b302
AM		 8312018-04-16 Alan Modra <amodra@gmail.com>
832
833 * Makefile.am: Remove w65 support.
834 * configure.ac: Likewise.
835 * disassemble.c: Likewise.
836 * disassemble.h: Likewise.
837 * w65-dis.c: Delete.
838 * w65-opc.h: Delete.
839 * Makefile.in: Regenerate.
840 * configure: Regenerate.
841 * po/POTFILES.in: Regenerate.
842
04cb01fd
AM		 8432018-04-16 Alan Modra <amodra@gmail.com>
844
845 * configure.ac: Remove we32k support.
846 * configure: Regenerate.
847
c2bf1eec
AM		 8482018-04-16 Alan Modra <amodra@gmail.com>
849
850 * Makefile.am: Remove m88k support.
851 * configure.ac: Likewise.
852 * disassemble.c: Likewise.
853 * disassemble.h: Likewise.
854 * m88k-dis.c: Delete.
855 * Makefile.in: Regenerate.
856 * configure: Regenerate.
857 * po/POTFILES.in: Regenerate.
858
6793974d
AM		 8592018-04-16 Alan Modra <amodra@gmail.com>
860
861 * Makefile.am: Remove i370 support.
862 * configure.ac: Likewise.
863 * disassemble.c: Likewise.
864 * disassemble.h: Likewise.
865 * i370-dis.c: Delete.
866 * i370-opc.c: Delete.
867 * Makefile.in: Regenerate.
868 * configure: Regenerate.
869 * po/POTFILES.in: Regenerate.
870
e82aa794
AM		 8712018-04-16 Alan Modra <amodra@gmail.com>
872
873 * Makefile.am: Remove h8500 support.
874 * configure.ac: Likewise.
875 * disassemble.c: Likewise.
876 * disassemble.h: Likewise.
877 * h8500-dis.c: Delete.
878 * h8500-opc.h: Delete.
879 * Makefile.in: Regenerate.
880 * configure: Regenerate.
881 * po/POTFILES.in: Regenerate.
882
fceadf09
AM		 8832018-04-16 Alan Modra <amodra@gmail.com>
884
885 * configure.ac: Remove tahoe support.
886 * configure: Regenerate.
887
ae1d3843
L		 8882018-04-15 H.J. Lu <hongjiu.lu@intel.com>
889
890 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
891 umwait.
892 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
893 64-bit mode.
894 * i386-tbl.h: Regenerated.
895
de89d0a3
IT		 8962018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
897
898 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
899 PREFIX_MOD_1_0FAE_REG_6.
900 (va_mode): New.
901 (OP_E_register): Use va_mode.
902 * i386-dis-evex.h (prefix_table):
903 New instructions (see prefixes above).
904 * i386-gen.c (cpu_flag_init): Add WAITPKG.
905 (cpu_flags): Likewise.
906 * i386-opc.h (enum): Likewise.
907 (i386_cpu_flags): Likewise.
908 * i386-opc.tbl: Add umonitor, umwait, tpause.
909 * i386-init.h: Regenerate.
910 * i386-tbl.h: Likewise.
911
a8eb42a8
AM		 9122018-04-11 Alan Modra <amodra@gmail.com>
913
914 * opcodes/i860-dis.c: Delete.
915 * opcodes/i960-dis.c: Delete.
916 * Makefile.am: Remove i860 and i960 support.
917 * configure.ac: Likewise.
918 * disassemble.c: Likewise.
919 * disassemble.h: Likewise.
920 * Makefile.in: Regenerate.
921 * configure: Regenerate.
922 * po/POTFILES.in: Regenerate.
923
caf0678c
L		 9242018-04-04 H.J. Lu <hongjiu.lu@intel.com>
925
926 PR binutils/23025
927 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
928 to 0.
929 (print_insn): Clear vex instead of vex.evex.
930
4fb0d2b9
NC		 9312018-04-04 Nick Clifton <nickc@redhat.com>
932
933 * po/es.po: Updated Spanish translation.
934
c39e5b26
JB		 9352018-03-28 Jan Beulich <jbeulich@suse.com>
936
937 * i386-gen.c (opcode_modifiers): Delete VecESize.
938 * i386-opc.h (VecESize): Delete.
939 (struct i386_opcode_modifier): Delete vecesize.
940 * i386-opc.tbl: Drop VecESize.
941 * i386-tlb.h: Re-generate.
942
8e6e0792
JB		 9432018-03-28 Jan Beulich <jbeulich@suse.com>
944
945 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
946 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
947 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
948 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
949 * i386-tlb.h: Re-generate.
950
9f123b91
JB		 9512018-03-28 Jan Beulich <jbeulich@suse.com>
952
953 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
954 Fold AVX512 forms
955 * i386-tlb.h: Re-generate.
956
9646c87b
JB		 9572018-03-28 Jan Beulich <jbeulich@suse.com>
958
959 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
960 (vex_len_table): Drop Y for vcvt*2si.
961 (putop): Replace plain 'Y' handling by abort().
962
c8d59609
NC		 9632018-03-28 Nick Clifton <nickc@redhat.com>
964
965 PR 22988
966 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
967 instructions with only a base address register.
968 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
969 handle AARHC64_OPND_SVE_ADDR_R.
970 (aarch64_print_operand): Likewise.
971 * aarch64-asm-2.c: Regenerate.
972 * aarch64_dis-2.c: Regenerate.
973 * aarch64-opc-2.c: Regenerate.
974
b8c169f3
JB		 9752018-03-22 Jan Beulich <jbeulich@suse.com>
976
977 * i386-opc.tbl: Drop VecESize from register only insn forms and
978 memory forms not allowing broadcast.
979 * i386-tlb.h: Re-generate.
980
96bc132a
JB		 9812018-03-22 Jan Beulich <jbeulich@suse.com>
982
983 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
984 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
985 sha256*): Drop Disp<N>.
986
9f79e886
JB		 9872018-03-22 Jan Beulich <jbeulich@suse.com>
988
989 * i386-dis.c (EbndS, bnd_swap_mode): New.
990 (prefix_table): Use EbndS.
991 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
992 * i386-opc.tbl (bndmov): Move misplaced Load.
993 * i386-tlb.h: Re-generate.
994
d6793fa1
JB		 9952018-03-22 Jan Beulich <jbeulich@suse.com>
996
997 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
998 templates allowing memory operands and folded ones for register
999 only flavors.
1000 * i386-tlb.h: Re-generate.
1001
f7768225
JB		 10022018-03-22 Jan Beulich <jbeulich@suse.com>
1003
1004 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1005 256-bit templates. Drop redundant leftover Disp<N>.
1006 * i386-tlb.h: Re-generate.
1007
0e35537d
JW		 10082018-03-14 Kito Cheng <kito.cheng@gmail.com>
1009
1010 * riscv-opc.c (riscv_insn_types): New.
1011
b4a3689a
NC		 10122018-03-13 Nick Clifton <nickc@redhat.com>
1013
1014 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1015
d3d50934
L		 10162018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1017
1018 * i386-opc.tbl: Add Optimize to clr.
1019 * i386-tbl.h: Regenerated.
1020
bd5dea88
L		 10212018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1022
1023 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1024 * i386-opc.h (OldGcc): Removed.
1025 (i386_opcode_modifier): Remove oldgcc.
1026 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1027 instructions for old (<= 2.8.1) versions of gcc.
1028 * i386-tbl.h: Regenerated.
1029
e771e7c9
JB		 10302018-03-08 Jan Beulich <jbeulich@suse.com>
1031
1032 * i386-opc.h (EVEXDYN): New.
1033 * i386-opc.tbl: Fold various AVX512VL templates.
1034 * i386-tlb.h: Re-generate.
1035
ed438a93
JB		 10362018-03-08 Jan Beulich <jbeulich@suse.com>
1037
1038 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1039 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1040 vpexpandd, vpexpandq): Fold AFX512VF templates.
1041 * i386-tlb.h: Re-generate.
1042
454172a9
JB		 10432018-03-08 Jan Beulich <jbeulich@suse.com>
1044
1045 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1046 Fold 128- and 256-bit VEX-encoded templates.
1047 * i386-tlb.h: Re-generate.
1048
36824150
JB		 10492018-03-08 Jan Beulich <jbeulich@suse.com>
1050
1051 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1052 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1053 vpexpandd, vpexpandq): Fold AVX512F templates.
1054 * i386-tlb.h: Re-generate.
1055
e7f5c0a9
JB		 10562018-03-08 Jan Beulich <jbeulich@suse.com>
1057
1058 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1059 64-bit templates. Drop Disp<N>.
1060 * i386-tlb.h: Re-generate.
1061
25a4277f
JB		 10622018-03-08 Jan Beulich <jbeulich@suse.com>
1063
1064 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1065 and 256-bit templates.
1066 * i386-tlb.h: Re-generate.
1067
d2224064
JB		 10682018-03-08 Jan Beulich <jbeulich@suse.com>
1069
1070 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1071 * i386-tlb.h: Re-generate.
1072
1b193f0b
JB		 10732018-03-08 Jan Beulich <jbeulich@suse.com>
1074
1075 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1076 Drop NoAVX.
1077 * i386-tlb.h: Re-generate.
1078
f2f6a710
JB		 10792018-03-08 Jan Beulich <jbeulich@suse.com>
1080
1081 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1082 * i386-tlb.h: Re-generate.
1083
38e314eb
JB		 10842018-03-08 Jan Beulich <jbeulich@suse.com>
1085
1086 * i386-gen.c (opcode_modifiers): Delete FloatD.
1087 * i386-opc.h (FloatD): Delete.
1088 (struct i386_opcode_modifier): Delete floatd.
1089 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1090 FloatD by D.
1091 * i386-tlb.h: Re-generate.
1092
d53e6b98
JB		 10932018-03-08 Jan Beulich <jbeulich@suse.com>
1094
1095 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1096
2907c2f5
JB		 10972018-03-08 Jan Beulich <jbeulich@suse.com>
1098
1099 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1100 * i386-tlb.h: Re-generate.
1101
73053c1f
JB		 11022018-03-08 Jan Beulich <jbeulich@suse.com>
1103
1104 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1105 forms.
1106 * i386-tlb.h: Re-generate.
1107
52fe4420
AM		 11082018-03-07 Alan Modra <amodra@gmail.com>
1109
1110 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1111 bfd_arch_rs6000.
1112 * disassemble.h (print_insn_rs6000): Delete.
1113 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1114 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1115 (print_insn_rs6000): Delete.
1116
a6743a54
AM		 11172018-03-03 Alan Modra <amodra@gmail.com>
1118
1119 * sysdep.h (opcodes_error_handler): Define.
1120 (_bfd_error_handler): Declare.
1121 * Makefile.am: Remove stray #.
1122 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1123 EDIT" comment.
1124 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1125 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1126 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1127 opcodes_error_handler to print errors. Standardize error messages.
1128 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1129 and include opintl.h.
1130 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1131 * i386-gen.c: Standardize error messages.
1132 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1133 * Makefile.in: Regenerate.
1134 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1135 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1136 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1137 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1138 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1139 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1140 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1141 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1142 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1143 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1144 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1145 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1146 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1147
8305403a
L		 11482018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1149
1150 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1151 vpsub[bwdq] instructions.
1152 * i386-tbl.h: Regenerated.
1153
e184813f
AM		 11542018-03-01 Alan Modra <amodra@gmail.com>
1155
1156 * configure.ac (ALL_LINGUAS): Sort.
1157 * configure: Regenerate.
1158
5b616bef
TP		 11592018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1160
1161 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1162 macro by assignements.
1163
b6f8c7c4
L		 11642018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1165
1166 PR gas/22871
1167 * i386-gen.c (opcode_modifiers): Add Optimize.
1168 * i386-opc.h (Optimize): New enum.
1169 (i386_opcode_modifier): Add optimize.
1170 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1171 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1172 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1173 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1174 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1175 vpxord and vpxorq.
1176 * i386-tbl.h: Regenerated.
1177
e95b887f
AM		 11782018-02-26 Alan Modra <amodra@gmail.com>
1179
1180 * crx-dis.c (getregliststring): Allocate a large enough buffer
1181 to silence false positive gcc8 warning.
1182
0bccfb29
JW		 11832018-02-22 Shea Levy <shea@shealevy.com>
1184
1185 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1186
6b6b6807
L		 11872018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1188
1189 * i386-opc.tbl: Add {rex},
1190 * i386-tbl.h: Regenerated.
1191
75f31665
MR		 11922018-02-20 Maciej W. Rozycki <macro@mips.com>
1193
1194 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1195 (mips16_opcodes): Replace `M' with `m' for "restore".
1196
e207bc53
TP		 11972018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1198
1199 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1200
87993319
MR		 12012018-02-13 Maciej W. Rozycki <macro@mips.com>
1202
1203 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1204 variable to `function_index'.
1205
68d20676
NC		 12062018-02-13 Nick Clifton <nickc@redhat.com>
1207
1208 PR 22823
1209 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1210 about truncation of printing.
1211
d2159fdc
HW		 12122018-02-12 Henry Wong <henry@stuffedcow.net>
1213
1214 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1215
f174ef9f
NC		 12162018-02-05 Nick Clifton <nickc@redhat.com>
1217
1218 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1219
be3a8dca
IT		 12202018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1221
1222 * i386-dis.c (enum): Add pconfig.
1223 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1224 (cpu_flags): Add CpuPCONFIG.
1225 * i386-opc.h (enum): Add CpuPCONFIG.
1226 (i386_cpu_flags): Add cpupconfig.
1227 * i386-opc.tbl: Add PCONFIG instruction.
1228 * i386-init.h: Regenerate.
1229 * i386-tbl.h: Likewise.
1230
3233d7d0
IT		 12312018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1232
1233 * i386-dis.c (enum): Add PREFIX_0F09.
1234 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1235 (cpu_flags): Add CpuWBNOINVD.
1236 * i386-opc.h (enum): Add CpuWBNOINVD.
1237 (i386_cpu_flags): Add cpuwbnoinvd.
1238 * i386-opc.tbl: Add WBNOINVD instruction.
1239 * i386-init.h: Regenerate.
1240 * i386-tbl.h: Likewise.
1241
e925c834
JW		 12422018-01-17 Jim Wilson <jimw@sifive.com>
1243
1244 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1245
d777820b
IT		 12462018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1247
1248 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1249 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1250 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1251 (cpu_flags): Add CpuIBT, CpuSHSTK.
1252 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1253 (i386_cpu_flags): Add cpuibt, cpushstk.
1254 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1255 * i386-init.h: Regenerate.
1256 * i386-tbl.h: Likewise.
1257
f6efed01
NC		 12582018-01-16 Nick Clifton <nickc@redhat.com>
1259
1260 * po/pt_BR.po: Updated Brazilian Portugese translation.
1261 * po/de.po: Updated German translation.
1262
2721d702
JW		 12632018-01-15 Jim Wilson <jimw@sifive.com>
1264
1265 * riscv-opc.c (match_c_nop): New.
1266 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1267
616dcb87
NC		 12682018-01-15 Nick Clifton <nickc@redhat.com>
1269
1270 * po/uk.po: Updated Ukranian translation.
1271
3957a496
NC		 12722018-01-13 Nick Clifton <nickc@redhat.com>
1273
1274 * po/opcodes.pot: Regenerated.
1275
769c7ea5
NC		 12762018-01-13 Nick Clifton <nickc@redhat.com>
1277
1278 * configure: Regenerate.
1279
faf766e3
NC		 12802018-01-13 Nick Clifton <nickc@redhat.com>
1281
1282 2.30 branch created.
1283
888a89da
IT		 12842018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1285
1286 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1287 * i386-tbl.h: Regenerate.
1288
cbda583a
JB		 12892018-01-10 Jan Beulich <jbeulich@suse.com>
1290
1291 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1292 * i386-tbl.h: Re-generate.
1293
c9e92278
JB		 12942018-01-10 Jan Beulich <jbeulich@suse.com>
1295
1296 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1297 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1298 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1299 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1300 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1301 Disp8MemShift of AVX512VL forms.
1302 * i386-tbl.h: Re-generate.
1303
35fd2b2b
JW		 13042018-01-09 Jim Wilson <jimw@sifive.com>
1305
1306 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1307 then the hi_addr value is zero.
1308
91d8b670
JG		 13092018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1310
1311 * arm-dis.c (arm_opcodes): Add csdb.
1312 (thumb32_opcodes): Add csdb.
1313
be2e7d95
JG		 13142018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1315
1316 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1317 * aarch64-asm-2.c: Regenerate.
1318 * aarch64-dis-2.c: Regenerate.
1319 * aarch64-opc-2.c: Regenerate.
1320
704a705d
L		 13212018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1322
1323 PR gas/22681
1324 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1325 Remove AVX512 vmovd with 64-bit operands.
1326 * i386-tbl.h: Regenerated.
1327
35eeb78f
JW		 13282018-01-05 Jim Wilson <jimw@sifive.com>
1329
1330 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1331 jalr.
1332
219d1afa
AM		 13332018-01-03 Alan Modra <amodra@gmail.com>
1334
1335 Update year range in copyright notice of all files.
1336
1508bbf5
JB		 13372018-01-02 Jan Beulich <jbeulich@suse.com>
1338
1339 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1340 and OPERAND_TYPE_REGZMM entries.
1341
1e563868 1342For older changes see ChangeLog-2017
3499769a 1343\f
1e563868 1344Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1345
1346Copying and distribution of this file, with or without modification,
1347are permitted in any medium without royalty provided the copyright
1348notice and this notice are preserved.
1349
1350Local Variables:
1351mode: change-log
1352left-margin: 8
1353fill-column: 74
1354version-control: never
1355End:
A mirror of the official binutils-gdb repository