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Fix memory access violation when attempting to shorten a suffixed micromips instructi...
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
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75f31665
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12018-02-20 Maciej W. Rozycki <macro@mips.com>
2
3 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
4 (mips16_opcodes): Replace `M' with `m' for "restore".
5
e207bc53
TP
62018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
7
8 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
9
87993319
MR
102018-02-13 Maciej W. Rozycki <macro@mips.com>
11
12 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
13 variable to `function_index'.
14
68d20676
NC
152018-02-13 Nick Clifton <nickc@redhat.com>
16
17 PR 22823
18 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
19 about truncation of printing.
20
d2159fdc
HW
212018-02-12 Henry Wong <henry@stuffedcow.net>
22
23 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
24
f174ef9f
NC
252018-02-05 Nick Clifton <nickc@redhat.com>
26
27 * po/pt_BR.po: Updated Brazilian Portuguese translation.
28
be3a8dca
IT
292018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
30
31 * i386-dis.c (enum): Add pconfig.
32 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
33 (cpu_flags): Add CpuPCONFIG.
34 * i386-opc.h (enum): Add CpuPCONFIG.
35 (i386_cpu_flags): Add cpupconfig.
36 * i386-opc.tbl: Add PCONFIG instruction.
37 * i386-init.h: Regenerate.
38 * i386-tbl.h: Likewise.
39
3233d7d0
IT
402018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
41
42 * i386-dis.c (enum): Add PREFIX_0F09.
43 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
44 (cpu_flags): Add CpuWBNOINVD.
45 * i386-opc.h (enum): Add CpuWBNOINVD.
46 (i386_cpu_flags): Add cpuwbnoinvd.
47 * i386-opc.tbl: Add WBNOINVD instruction.
48 * i386-init.h: Regenerate.
49 * i386-tbl.h: Likewise.
50
e925c834
JW
512018-01-17 Jim Wilson <jimw@sifive.com>
52
53 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
54
d777820b
IT
552018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
56
57 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
58 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
59 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
60 (cpu_flags): Add CpuIBT, CpuSHSTK.
61 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
62 (i386_cpu_flags): Add cpuibt, cpushstk.
63 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
64 * i386-init.h: Regenerate.
65 * i386-tbl.h: Likewise.
66
f6efed01
NC
672018-01-16 Nick Clifton <nickc@redhat.com>
68
69 * po/pt_BR.po: Updated Brazilian Portugese translation.
70 * po/de.po: Updated German translation.
71
2721d702
JW
722018-01-15 Jim Wilson <jimw@sifive.com>
73
74 * riscv-opc.c (match_c_nop): New.
75 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
76
616dcb87
NC
772018-01-15 Nick Clifton <nickc@redhat.com>
78
79 * po/uk.po: Updated Ukranian translation.
80
3957a496
NC
812018-01-13 Nick Clifton <nickc@redhat.com>
82
83 * po/opcodes.pot: Regenerated.
84
769c7ea5
NC
852018-01-13 Nick Clifton <nickc@redhat.com>
86
87 * configure: Regenerate.
88
faf766e3
NC
892018-01-13 Nick Clifton <nickc@redhat.com>
90
91 2.30 branch created.
92
888a89da
IT
932018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
94
95 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
96 * i386-tbl.h: Regenerate.
97
cbda583a
JB
982018-01-10 Jan Beulich <jbeulich@suse.com>
99
100 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
101 * i386-tbl.h: Re-generate.
102
c9e92278
JB
1032018-01-10 Jan Beulich <jbeulich@suse.com>
104
105 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
106 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
107 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
108 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
109 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
110 Disp8MemShift of AVX512VL forms.
111 * i386-tbl.h: Re-generate.
112
35fd2b2b
JW
1132018-01-09 Jim Wilson <jimw@sifive.com>
114
115 * riscv-dis.c (maybe_print_address): If base_reg is zero,
116 then the hi_addr value is zero.
117
91d8b670
JG
1182018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
119
120 * arm-dis.c (arm_opcodes): Add csdb.
121 (thumb32_opcodes): Add csdb.
122
be2e7d95
JG
1232018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
124
125 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
126 * aarch64-asm-2.c: Regenerate.
127 * aarch64-dis-2.c: Regenerate.
128 * aarch64-opc-2.c: Regenerate.
129
704a705d
L
1302018-01-08 H.J. Lu <hongjiu.lu@intel.com>
131
132 PR gas/22681
133 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
134 Remove AVX512 vmovd with 64-bit operands.
135 * i386-tbl.h: Regenerated.
136
35eeb78f
JW
1372018-01-05 Jim Wilson <jimw@sifive.com>
138
139 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
140 jalr.
141
219d1afa
AM
1422018-01-03 Alan Modra <amodra@gmail.com>
143
144 Update year range in copyright notice of all files.
145
1508bbf5
JB
1462018-01-02 Jan Beulich <jbeulich@suse.com>
147
148 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
149 and OPERAND_TYPE_REGZMM entries.
150
1e563868 151For older changes see ChangeLog-2017
3499769a 152\f
1e563868 153Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
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154
155Copying and distribution of this file, with or without modification,
156are permitted in any medium without royalty provided the copyright
157notice and this notice are preserved.
158
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