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514cd3a0
TC		 12018-06-19 Tamar Christina <tamar.christina@arm.com>
2
3 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
4 * aarch64-asm-2.c: Regenerate.
5 * aarch64-dis-2.c: Likewise.
6
385e4d0f
MR		 72018-06-21 Maciej W. Rozycki <macro@mips.com>
8
9 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
10 `-M ginv' option description.
11
160d1b3d
SH		 122018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
13
14 PR gas/23305
15 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
16 la and lla.
17
d0ac1c44
SM		 182018-06-19 Simon Marchi <simon.marchi@ericsson.com>
19
20 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
21 * configure.ac: Remove AC_PREREQ.
22 * Makefile.in: Re-generate.
23 * aclocal.m4: Re-generate.
24 * configure: Re-generate.
25
6f20c942
FS		 262018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
27
28 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
29 mips64r6 descriptors.
30 (parse_mips_ase_option): Handle -Mginv option.
31 (print_mips_disassembler_options): Document -Mginv.
32 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
33 (GINV): New macro.
34 (mips_opcodes): Define ginvi and ginvt.
35
730c3174
SE		 362018-06-13 Scott Egerton <scott.egerton@imgtec.com>
37 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
38
39 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
40 * mips-opc.c (CRC, CRC64): New macros.
41 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
42 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
43 crc32cd for CRC64.
44
cb366992
EB		 452018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
46
47 PR 20319
48 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
49 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
50
ce72cd46
AM		 512018-06-06 Alan Modra <amodra@gmail.com>
52
53 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
54 setjmp. Move init for some other vars later too.
55
4b8e28c7
MF		 562018-06-04 Max Filippov <jcmvbkbc@gmail.com>
57
58 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
59 (dis_private): Add new fields for property section tracking.
60 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
61 (xtensa_instruction_fits): New functions.
62 (fetch_data): Bump minimal fetch size to 4.
63 (print_insn_xtensa): Make struct dis_private static.
64 Load and prepare property table on section change.
65 Don't disassemble literals. Don't disassemble instructions that
66 cross property table boundaries.
67
55e99962
L		 682018-06-01 H.J. Lu <hongjiu.lu@intel.com>
69
70 * configure: Regenerated.
71
733bd0ab
JB		 722018-06-01 Jan Beulich <jbeulich@suse.com>
73
74 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
75 * i386-tbl.h: Re-generate.
76
dfd27d41
JB		 772018-06-01 Jan Beulich <jbeulich@suse.com>
78
79 * i386-opc.tbl (sldt, str): Add NoRex64.
80 * i386-tbl.h: Re-generate.
81
64795710
JB		 822018-06-01 Jan Beulich <jbeulich@suse.com>
83
84 * i386-opc.tbl (invpcid): Add Oword.
85 * i386-tbl.h: Re-generate.
86
030157d8
AM		 872018-06-01 Alan Modra <amodra@gmail.com>
88
89 * sysdep.h (_bfd_error_handler): Don't declare.
90 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
91 * rl78-decode.opc: Likewise.
92 * msp430-decode.c: Regenerate.
93 * rl78-decode.c: Regenerate.
94
a9660a6f
AP		 952018-05-30 Amit Pawar <Amit.Pawar@amd.com>
96
97 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
98 * i386-init.h : Regenerated.
99
277eb7f6
AM		 1002018-05-25 Alan Modra <amodra@gmail.com>
101
102 * Makefile.in: Regenerate.
103 * po/POTFILES.in: Regenerate.
104
98553ad3
PB		 1052018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
106
107 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
108 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
109 (insert_bab, extract_bab, insert_btab, extract_btab,
110 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
111 (BAT, BBA VBA RBS XB6S): Delete macros.
112 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
113 (BB, BD, RBX, XC6): Update for new macros.
114 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
115 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
116 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
117 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
118
7b4ae824
JD		 1192018-05-18 John Darrington <john@darrington.wattle.id.au>
120
121 * Makefile.am: Add support for s12z architecture.
122 * configure.ac: Likewise.
123 * disassemble.c: Likewise.
124 * disassemble.h: Likewise.
125 * Makefile.in: Regenerate.
126 * configure: Regenerate.
127 * s12z-dis.c: New file.
128 * s12z.h: New file.
129
29e0f0a1
AM		 1302018-05-18 Alan Modra <amodra@gmail.com>
131
132 * nfp-dis.c: Don't #include libbfd.h.
133 (init_nfp3200_priv): Use bfd_get_section_contents.
134 (nit_nfp6000_mecsr_sec): Likewise.
135
809276d2
NC		 1362018-05-17 Nick Clifton <nickc@redhat.com>
137
138 * po/zh_CN.po: Updated simplified Chinese translation.
139
ff329288
TC		 1402018-05-16 Tamar Christina <tamar.christina@arm.com>
141
142 PR binutils/23109
143 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
144 * aarch64-dis-2.c: Regenerate.
145
f9830ec1
TC		 1462018-05-15 Tamar Christina <tamar.christina@arm.com>
147
148 PR binutils/21446
149 * aarch64-asm.c (opintl.h): Include.
150 (aarch64_ins_sysreg): Enforce read/write constraints.
151 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
152 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
153 (F_REG_READ, F_REG_WRITE): New.
154 * aarch64-opc.c (aarch64_print_operand): Generate notes for
155 AARCH64_OPND_SYSREG.
156 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
157 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
158 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
159 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
160 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
161 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
162 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
163 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
164 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
165 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
166 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
167 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
168 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
169 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
170 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
171 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
172 msr (F_SYS_WRITE), mrs (F_SYS_READ).
173
7d02540a
TC		 1742018-05-15 Tamar Christina <tamar.christina@arm.com>
175
176 PR binutils/21446
177 * aarch64-dis.c (no_notes: New.
178 (parse_aarch64_dis_option): Support notes.
179 (aarch64_decode_insn, print_operands): Likewise.
180 (print_aarch64_disassembler_options): Document notes.
181 * aarch64-opc.c (aarch64_print_operand): Support notes.
182
561a72d4
TC		 1832018-05-15 Tamar Christina <tamar.christina@arm.com>
184
185 PR binutils/21446
186 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
187 and take error struct.
188 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
189 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
190 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
191 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
192 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
193 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
194 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
195 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
196 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
197 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
198 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
199 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
200 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
201 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
202 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
203 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
204 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
205 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
206 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
207 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
208 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
209 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
210 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
211 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
212 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
213 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
214 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
215 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
216 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
217 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
218 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
219 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
220 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
221 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
222 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
223 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
224 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
225 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
226 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
227 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
228 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
229 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
230 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
231 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
232 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
233 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
234 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
235 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
236 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
237 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
238 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
239 (determine_disassembling_preference, aarch64_decode_insn,
240 print_insn_aarch64_word, print_insn_data): Take errors struct.
241 (print_insn_aarch64): Use errors.
242 * aarch64-asm-2.c: Regenerate.
243 * aarch64-dis-2.c: Regenerate.
244 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
245 boolean in aarch64_insert_operan.
246 (print_operand_extractor): Likewise.
247 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
248
1678bd35
FT		 2492018-05-15 Francois H. Theron <francois.theron@netronome.com>
250
251 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
252
06cfb1c8
L		 2532018-05-09 H.J. Lu <hongjiu.lu@intel.com>
254
255 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
256
84f9f8c3
AM		 2572018-05-09 Sebastian Rasmussen <sebras@gmail.com>
258
259 * cr16-opc.c (cr16_instruction): Comment typo fix.
260 * hppa-dis.c (print_insn_hppa): Likewise.
261
e6f372ba
JW		 2622018-05-08 Jim Wilson <jimw@sifive.com>
263
264 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
265 (match_c_slli64, match_srxi_as_c_srxi): New.
266 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
267 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
268 <c.slli, c.srli, c.srai>: Use match_s_slli.
269 <c.slli64, c.srli64, c.srai64>: New.
270
f413a913
AM		 2712018-05-08 Alan Modra <amodra@gmail.com>
272
273 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
274 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
275 partition opcode space for index lookup.
276
a87a6478
PB		 2772018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
278
279 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
280 <insn_length>: ...with this. Update usage.
281 Remove duplicate call to *info->memory_error_func.
282
c0a30a9f
L		 2832018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
284 H.J. Lu <hongjiu.lu@intel.com>
285
286 * i386-dis.c (Gva): New.
287 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
288 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
289 (prefix_table): New instructions (see prefix above).
290 (mod_table): New instructions (see prefix above).
291 (OP_G): Handle va_mode.
292 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
293 CPU_MOVDIR64B_FLAGS.
294 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
295 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
296 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
297 * i386-opc.tbl: Add movidir{i,64b}.
298 * i386-init.h: Regenerated.
299 * i386-tbl.h: Likewise.
300
75c0a438
L		 3012018-05-07 H.J. Lu <hongjiu.lu@intel.com>
302
303 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
304 AddrPrefixOpReg.
305 * i386-opc.h (AddrPrefixOp0): Renamed to ...
306 (AddrPrefixOpReg): This.
307 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
308 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
309
2ceb7719
PB		 3102018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
311
312 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
313 (vle_num_opcodes): Likewise.
314 (spe2_num_opcodes): Likewise.
315 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
316 initialization loop.
317 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
318 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
319 only once.
320
b3ac5c6c
TC		 3212018-05-01 Tamar Christina <tamar.christina@arm.com>
322
323 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
324
fe944acf
FT		 3252018-04-30 Francois H. Theron <francois.theron@netronome.com>
326
327 Makefile.am: Added nfp-dis.c.
328 configure.ac: Added bfd_nfp_arch.
329 disassemble.h: Added print_insn_nfp prototype.
330 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
331 nfp-dis.c: New, for NFP support.
332 po/POTFILES.in: Added nfp-dis.c to the list.
333 Makefile.in: Regenerate.
334 configure: Regenerate.
335
e2195274
JB		 3362018-04-26 Jan Beulich <jbeulich@suse.com>
337
338 * i386-opc.tbl: Fold various non-memory operand AVX512VL
339 templates into their base ones.
340 * i386-tlb.h: Re-generate.
341
59ef5df4
JB		 3422018-04-26 Jan Beulich <jbeulich@suse.com>
343
344 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
345 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
346 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
347 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
348 * i386-init.h: Re-generate.
349
6e041cf4
JB		 3502018-04-26 Jan Beulich <jbeulich@suse.com>
351
352 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
353 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
354 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
355 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
356 comment.
357 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
358 and CpuRegMask.
359 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
360 CpuRegMask: Delete.
361 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
362 cpuregzmm, and cpuregmask.
363 * i386-init.h: Re-generate.
364 * i386-tbl.h: Re-generate.
365
0e0eea78
JB		 3662018-04-26 Jan Beulich <jbeulich@suse.com>
367
368 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
369 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
370 * i386-init.h: Re-generate.
371
2f1bada2
JB		 3722018-04-26 Jan Beulich <jbeulich@suse.com>
373
374 * i386-gen.c (VexImmExt): Delete.
375 * i386-opc.h (VexImmExt, veximmext): Delete.
376 * i386-opc.tbl: Drop all VexImmExt uses.
377 * i386-tlb.h: Re-generate.
378
bacd1457
JB		 3792018-04-25 Jan Beulich <jbeulich@suse.com>
380
381 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
382 register-only forms.
383 * i386-tlb.h: Re-generate.
384
10bba94b
TC		 3852018-04-25 Tamar Christina <tamar.christina@arm.com>
386
387 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
388
c48935d7
IT		 3892018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
390
391 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
392 PREFIX_0F1C.
393 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
394 (cpu_flags): Add CpuCLDEMOTE.
395 * i386-init.h: Regenerate.
396 * i386-opc.h (enum): Add CpuCLDEMOTE,
397 (i386_cpu_flags): Add cpucldemote.
398 * i386-opc.tbl: Add cldemote.
399 * i386-tbl.h: Regenerate.
400
211dc24b
AM		 4012018-04-16 Alan Modra <amodra@gmail.com>
402
403 * Makefile.am: Remove sh5 and sh64 support.
404 * configure.ac: Likewise.
405 * disassemble.c: Likewise.
406 * disassemble.h: Likewise.
407 * sh-dis.c: Likewise.
408 * sh64-dis.c: Delete.
409 * sh64-opc.c: Delete.
410 * sh64-opc.h: Delete.
411 * Makefile.in: Regenerate.
412 * configure: Regenerate.
413 * po/POTFILES.in: Regenerate.
414
a9a4b302
AM		 4152018-04-16 Alan Modra <amodra@gmail.com>
416
417 * Makefile.am: Remove w65 support.
418 * configure.ac: Likewise.
419 * disassemble.c: Likewise.
420 * disassemble.h: Likewise.
421 * w65-dis.c: Delete.
422 * w65-opc.h: Delete.
423 * Makefile.in: Regenerate.
424 * configure: Regenerate.
425 * po/POTFILES.in: Regenerate.
426
04cb01fd
AM		 4272018-04-16 Alan Modra <amodra@gmail.com>
428
429 * configure.ac: Remove we32k support.
430 * configure: Regenerate.
431
c2bf1eec
AM		 4322018-04-16 Alan Modra <amodra@gmail.com>
433
434 * Makefile.am: Remove m88k support.
435 * configure.ac: Likewise.
436 * disassemble.c: Likewise.
437 * disassemble.h: Likewise.
438 * m88k-dis.c: Delete.
439 * Makefile.in: Regenerate.
440 * configure: Regenerate.
441 * po/POTFILES.in: Regenerate.
442
6793974d
AM		 4432018-04-16 Alan Modra <amodra@gmail.com>
444
445 * Makefile.am: Remove i370 support.
446 * configure.ac: Likewise.
447 * disassemble.c: Likewise.
448 * disassemble.h: Likewise.
449 * i370-dis.c: Delete.
450 * i370-opc.c: Delete.
451 * Makefile.in: Regenerate.
452 * configure: Regenerate.
453 * po/POTFILES.in: Regenerate.
454
e82aa794
AM		 4552018-04-16 Alan Modra <amodra@gmail.com>
456
457 * Makefile.am: Remove h8500 support.
458 * configure.ac: Likewise.
459 * disassemble.c: Likewise.
460 * disassemble.h: Likewise.
461 * h8500-dis.c: Delete.
462 * h8500-opc.h: Delete.
463 * Makefile.in: Regenerate.
464 * configure: Regenerate.
465 * po/POTFILES.in: Regenerate.
466
fceadf09
AM		 4672018-04-16 Alan Modra <amodra@gmail.com>
468
469 * configure.ac: Remove tahoe support.
470 * configure: Regenerate.
471
ae1d3843
L		 4722018-04-15 H.J. Lu <hongjiu.lu@intel.com>
473
474 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
475 umwait.
476 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
477 64-bit mode.
478 * i386-tbl.h: Regenerated.
479
de89d0a3
IT		 4802018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
481
482 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
483 PREFIX_MOD_1_0FAE_REG_6.
484 (va_mode): New.
485 (OP_E_register): Use va_mode.
486 * i386-dis-evex.h (prefix_table):
487 New instructions (see prefixes above).
488 * i386-gen.c (cpu_flag_init): Add WAITPKG.
489 (cpu_flags): Likewise.
490 * i386-opc.h (enum): Likewise.
491 (i386_cpu_flags): Likewise.
492 * i386-opc.tbl: Add umonitor, umwait, tpause.
493 * i386-init.h: Regenerate.
494 * i386-tbl.h: Likewise.
495
a8eb42a8
AM		 4962018-04-11 Alan Modra <amodra@gmail.com>
497
498 * opcodes/i860-dis.c: Delete.
499 * opcodes/i960-dis.c: Delete.
500 * Makefile.am: Remove i860 and i960 support.
501 * configure.ac: Likewise.
502 * disassemble.c: Likewise.
503 * disassemble.h: Likewise.
504 * Makefile.in: Regenerate.
505 * configure: Regenerate.
506 * po/POTFILES.in: Regenerate.
507
caf0678c
L		 5082018-04-04 H.J. Lu <hongjiu.lu@intel.com>
509
510 PR binutils/23025
511 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
512 to 0.
513 (print_insn): Clear vex instead of vex.evex.
514
4fb0d2b9
NC		 5152018-04-04 Nick Clifton <nickc@redhat.com>
516
517 * po/es.po: Updated Spanish translation.
518
c39e5b26
JB		 5192018-03-28 Jan Beulich <jbeulich@suse.com>
520
521 * i386-gen.c (opcode_modifiers): Delete VecESize.
522 * i386-opc.h (VecESize): Delete.
523 (struct i386_opcode_modifier): Delete vecesize.
524 * i386-opc.tbl: Drop VecESize.
525 * i386-tlb.h: Re-generate.
526
8e6e0792
JB		 5272018-03-28 Jan Beulich <jbeulich@suse.com>
528
529 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
530 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
531 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
532 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
533 * i386-tlb.h: Re-generate.
534
9f123b91
JB		 5352018-03-28 Jan Beulich <jbeulich@suse.com>
536
537 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
538 Fold AVX512 forms
539 * i386-tlb.h: Re-generate.
540
9646c87b
JB		 5412018-03-28 Jan Beulich <jbeulich@suse.com>
542
543 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
544 (vex_len_table): Drop Y for vcvt*2si.
545 (putop): Replace plain 'Y' handling by abort().
546
c8d59609
NC		 5472018-03-28 Nick Clifton <nickc@redhat.com>
548
549 PR 22988
550 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
551 instructions with only a base address register.
552 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
553 handle AARHC64_OPND_SVE_ADDR_R.
554 (aarch64_print_operand): Likewise.
555 * aarch64-asm-2.c: Regenerate.
556 * aarch64_dis-2.c: Regenerate.
557 * aarch64-opc-2.c: Regenerate.
558
b8c169f3
JB		 5592018-03-22 Jan Beulich <jbeulich@suse.com>
560
561 * i386-opc.tbl: Drop VecESize from register only insn forms and
562 memory forms not allowing broadcast.
563 * i386-tlb.h: Re-generate.
564
96bc132a
JB		 5652018-03-22 Jan Beulich <jbeulich@suse.com>
566
567 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
568 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
569 sha256*): Drop Disp<N>.
570
9f79e886
JB		 5712018-03-22 Jan Beulich <jbeulich@suse.com>
572
573 * i386-dis.c (EbndS, bnd_swap_mode): New.
574 (prefix_table): Use EbndS.
575 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
576 * i386-opc.tbl (bndmov): Move misplaced Load.
577 * i386-tlb.h: Re-generate.
578
d6793fa1
JB		 5792018-03-22 Jan Beulich <jbeulich@suse.com>
580
581 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
582 templates allowing memory operands and folded ones for register
583 only flavors.
584 * i386-tlb.h: Re-generate.
585
f7768225
JB		 5862018-03-22 Jan Beulich <jbeulich@suse.com>
587
588 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
589 256-bit templates. Drop redundant leftover Disp<N>.
590 * i386-tlb.h: Re-generate.
591
0e35537d
JW		 5922018-03-14 Kito Cheng <kito.cheng@gmail.com>
593
594 * riscv-opc.c (riscv_insn_types): New.
595
b4a3689a
NC		 5962018-03-13 Nick Clifton <nickc@redhat.com>
597
598 * po/pt_BR.po: Updated Brazilian Portuguese translation.
599
d3d50934
L		 6002018-03-08 H.J. Lu <hongjiu.lu@intel.com>
601
602 * i386-opc.tbl: Add Optimize to clr.
603 * i386-tbl.h: Regenerated.
604
bd5dea88
L		 6052018-03-08 H.J. Lu <hongjiu.lu@intel.com>
606
607 * i386-gen.c (opcode_modifiers): Remove OldGcc.
608 * i386-opc.h (OldGcc): Removed.
609 (i386_opcode_modifier): Remove oldgcc.
610 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
611 instructions for old (<= 2.8.1) versions of gcc.
612 * i386-tbl.h: Regenerated.
613
e771e7c9
JB		 6142018-03-08 Jan Beulich <jbeulich@suse.com>
615
616 * i386-opc.h (EVEXDYN): New.
617 * i386-opc.tbl: Fold various AVX512VL templates.
618 * i386-tlb.h: Re-generate.
619
ed438a93
JB		 6202018-03-08 Jan Beulich <jbeulich@suse.com>
621
622 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
623 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
624 vpexpandd, vpexpandq): Fold AFX512VF templates.
625 * i386-tlb.h: Re-generate.
626
454172a9
JB		 6272018-03-08 Jan Beulich <jbeulich@suse.com>
628
629 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
630 Fold 128- and 256-bit VEX-encoded templates.
631 * i386-tlb.h: Re-generate.
632
36824150
JB		 6332018-03-08 Jan Beulich <jbeulich@suse.com>
634
635 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
636 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
637 vpexpandd, vpexpandq): Fold AVX512F templates.
638 * i386-tlb.h: Re-generate.
639
e7f5c0a9
JB		 6402018-03-08 Jan Beulich <jbeulich@suse.com>
641
642 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
643 64-bit templates. Drop Disp<N>.
644 * i386-tlb.h: Re-generate.
645
25a4277f
JB		 6462018-03-08 Jan Beulich <jbeulich@suse.com>
647
648 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
649 and 256-bit templates.
650 * i386-tlb.h: Re-generate.
651
d2224064
JB		 6522018-03-08 Jan Beulich <jbeulich@suse.com>
653
654 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
655 * i386-tlb.h: Re-generate.
656
1b193f0b
JB		 6572018-03-08 Jan Beulich <jbeulich@suse.com>
658
659 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
660 Drop NoAVX.
661 * i386-tlb.h: Re-generate.
662
f2f6a710
JB		 6632018-03-08 Jan Beulich <jbeulich@suse.com>
664
665 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
666 * i386-tlb.h: Re-generate.
667
38e314eb
JB		 6682018-03-08 Jan Beulich <jbeulich@suse.com>
669
670 * i386-gen.c (opcode_modifiers): Delete FloatD.
671 * i386-opc.h (FloatD): Delete.
672 (struct i386_opcode_modifier): Delete floatd.
673 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
674 FloatD by D.
675 * i386-tlb.h: Re-generate.
676
d53e6b98
JB		 6772018-03-08 Jan Beulich <jbeulich@suse.com>
678
679 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
680
2907c2f5
JB		 6812018-03-08 Jan Beulich <jbeulich@suse.com>
682
683 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
684 * i386-tlb.h: Re-generate.
685
73053c1f
JB		 6862018-03-08 Jan Beulich <jbeulich@suse.com>
687
688 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
689 forms.
690 * i386-tlb.h: Re-generate.
691
52fe4420
AM		 6922018-03-07 Alan Modra <amodra@gmail.com>
693
694 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
695 bfd_arch_rs6000.
696 * disassemble.h (print_insn_rs6000): Delete.
697 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
698 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
699 (print_insn_rs6000): Delete.
700
a6743a54
AM		 7012018-03-03 Alan Modra <amodra@gmail.com>
702
703 * sysdep.h (opcodes_error_handler): Define.
704 (_bfd_error_handler): Declare.
705 * Makefile.am: Remove stray #.
706 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
707 EDIT" comment.
708 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
709 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
710 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
711 opcodes_error_handler to print errors. Standardize error messages.
712 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
713 and include opintl.h.
714 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
715 * i386-gen.c: Standardize error messages.
716 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
717 * Makefile.in: Regenerate.
718 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
719 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
720 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
721 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
722 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
723 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
724 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
725 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
726 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
727 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
728 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
729 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
730 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
731
8305403a
L		 7322018-03-01 H.J. Lu <hongjiu.lu@intel.com>
733
734 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
735 vpsub[bwdq] instructions.
736 * i386-tbl.h: Regenerated.
737
e184813f
AM		 7382018-03-01 Alan Modra <amodra@gmail.com>
739
740 * configure.ac (ALL_LINGUAS): Sort.
741 * configure: Regenerate.
742
5b616bef
TP		 7432018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
744
745 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
746 macro by assignements.
747
b6f8c7c4
L		 7482018-02-27 H.J. Lu <hongjiu.lu@intel.com>
749
750 PR gas/22871
751 * i386-gen.c (opcode_modifiers): Add Optimize.
752 * i386-opc.h (Optimize): New enum.
753 (i386_opcode_modifier): Add optimize.
754 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
755 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
756 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
757 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
758 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
759 vpxord and vpxorq.
760 * i386-tbl.h: Regenerated.
761
e95b887f
AM		 7622018-02-26 Alan Modra <amodra@gmail.com>
763
764 * crx-dis.c (getregliststring): Allocate a large enough buffer
765 to silence false positive gcc8 warning.
766
0bccfb29
JW		 7672018-02-22 Shea Levy <shea@shealevy.com>
768
769 * disassemble.c (ARCH_riscv): Define if ARCH_all.
770
6b6b6807
L		 7712018-02-22 H.J. Lu <hongjiu.lu@intel.com>
772
773 * i386-opc.tbl: Add {rex},
774 * i386-tbl.h: Regenerated.
775
75f31665
MR		 7762018-02-20 Maciej W. Rozycki <macro@mips.com>
777
778 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
779 (mips16_opcodes): Replace `M' with `m' for "restore".
780
e207bc53
TP		 7812018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
782
783 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
784
87993319
MR		 7852018-02-13 Maciej W. Rozycki <macro@mips.com>
786
787 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
788 variable to `function_index'.
789
68d20676
NC		 7902018-02-13 Nick Clifton <nickc@redhat.com>
791
792 PR 22823
793 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
794 about truncation of printing.
795
d2159fdc
HW		 7962018-02-12 Henry Wong <henry@stuffedcow.net>
797
798 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
799
f174ef9f
NC		 8002018-02-05 Nick Clifton <nickc@redhat.com>
801
802 * po/pt_BR.po: Updated Brazilian Portuguese translation.
803
be3a8dca
IT		 8042018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
805
806 * i386-dis.c (enum): Add pconfig.
807 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
808 (cpu_flags): Add CpuPCONFIG.
809 * i386-opc.h (enum): Add CpuPCONFIG.
810 (i386_cpu_flags): Add cpupconfig.
811 * i386-opc.tbl: Add PCONFIG instruction.
812 * i386-init.h: Regenerate.
813 * i386-tbl.h: Likewise.
814
3233d7d0
IT		 8152018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
816
817 * i386-dis.c (enum): Add PREFIX_0F09.
818 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
819 (cpu_flags): Add CpuWBNOINVD.
820 * i386-opc.h (enum): Add CpuWBNOINVD.
821 (i386_cpu_flags): Add cpuwbnoinvd.
822 * i386-opc.tbl: Add WBNOINVD instruction.
823 * i386-init.h: Regenerate.
824 * i386-tbl.h: Likewise.
825
e925c834
JW		 8262018-01-17 Jim Wilson <jimw@sifive.com>
827
828 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
829
d777820b
IT		 8302018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
831
832 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
833 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
834 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
835 (cpu_flags): Add CpuIBT, CpuSHSTK.
836 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
837 (i386_cpu_flags): Add cpuibt, cpushstk.
838 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
839 * i386-init.h: Regenerate.
840 * i386-tbl.h: Likewise.
841
f6efed01
NC		 8422018-01-16 Nick Clifton <nickc@redhat.com>
843
844 * po/pt_BR.po: Updated Brazilian Portugese translation.
845 * po/de.po: Updated German translation.
846
2721d702
JW		 8472018-01-15 Jim Wilson <jimw@sifive.com>
848
849 * riscv-opc.c (match_c_nop): New.
850 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
851
616dcb87
NC		 8522018-01-15 Nick Clifton <nickc@redhat.com>
853
854 * po/uk.po: Updated Ukranian translation.
855
3957a496
NC		 8562018-01-13 Nick Clifton <nickc@redhat.com>
857
858 * po/opcodes.pot: Regenerated.
859
769c7ea5
NC		 8602018-01-13 Nick Clifton <nickc@redhat.com>
861
862 * configure: Regenerate.
863
faf766e3
NC		 8642018-01-13 Nick Clifton <nickc@redhat.com>
865
866 2.30 branch created.
867
888a89da
IT		 8682018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
869
870 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
871 * i386-tbl.h: Regenerate.
872
cbda583a
JB		 8732018-01-10 Jan Beulich <jbeulich@suse.com>
874
875 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
876 * i386-tbl.h: Re-generate.
877
c9e92278
JB		 8782018-01-10 Jan Beulich <jbeulich@suse.com>
879
880 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
881 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
882 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
883 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
884 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
885 Disp8MemShift of AVX512VL forms.
886 * i386-tbl.h: Re-generate.
887
35fd2b2b
JW		 8882018-01-09 Jim Wilson <jimw@sifive.com>
889
890 * riscv-dis.c (maybe_print_address): If base_reg is zero,
891 then the hi_addr value is zero.
892
91d8b670
JG		 8932018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
894
895 * arm-dis.c (arm_opcodes): Add csdb.
896 (thumb32_opcodes): Add csdb.
897
be2e7d95
JG		 8982018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
899
900 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
901 * aarch64-asm-2.c: Regenerate.
902 * aarch64-dis-2.c: Regenerate.
903 * aarch64-opc-2.c: Regenerate.
904
704a705d
L		 9052018-01-08 H.J. Lu <hongjiu.lu@intel.com>
906
907 PR gas/22681
908 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
909 Remove AVX512 vmovd with 64-bit operands.
910 * i386-tbl.h: Regenerated.
911
35eeb78f
JW		 9122018-01-05 Jim Wilson <jimw@sifive.com>
913
914 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
915 jalr.
916
219d1afa
AM		 9172018-01-03 Alan Modra <amodra@gmail.com>
918
919 Update year range in copyright notice of all files.
920
1508bbf5
JB		 9212018-01-02 Jan Beulich <jbeulich@suse.com>
922
923 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
924 and OPERAND_TYPE_REGZMM entries.
925
1e563868 926For older changes see ChangeLog-2017
3499769a 927\f
1e563868 928Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 929
930Copying and distribution of this file, with or without modification,
931are permitted in any medium without royalty provided the copyright
932notice and this notice are preserved.
933
934Local Variables:
935mode: change-log
936left-margin: 8
937fill-column: 74
938version-control: never
939End:
A mirror of the official binutils-gdb repository