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RISC-V: Allow 32-bit BFD to handle 64-bit objects
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
a4ddc54e
MR		 12017-05-02 Maciej W. Rozycki <macro@imgtec.com>
2
3 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
4 and branches and not synthetic data instructions.
5
fe50e98c
BE		 62017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
7
8 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
9
126124cc
CZ		 102017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
11
12 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
13 * arc-opc.c (insert_r13el): New function.
14 (R13_EL): Define.
15 * arc-tbl.h: Add new enter/leave variants.
16
be6a24d8
CZ		 172017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
18
19 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
20
0348fd79
MR		 212017-04-25 Maciej W. Rozycki <macro@imgtec.com>
22
23 * mips-dis.c (print_mips_disassembler_options): Add
24 `no-aliases'.
25
6e3d1f07
MR		 262017-04-25 Maciej W. Rozycki <macro@imgtec.com>
27
28 * mips16-opc.c (AL): New macro.
29 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
30 of "ld" and "lw" as aliases.
31
957f6b39
TC		 322017-04-24 Tamar Christina <tamar.christina@arm.com>
33
34 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
35 arguments.
36
a8cc8a54
AM		 372017-04-22 Alexander Fedotov <alfedotov@gmail.com>
38 Alan Modra <amodra@gmail.com>
39
40 * ppc-opc.c (ELEV): Define.
41 (vle_opcodes): Add se_rfgi and e_sc.
42 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
43 for E200Z4.
44
3ab87b68
JM		 452017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
46
47 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
48
792f174f
NC		 492017-04-21 Nick Clifton <nickc@redhat.com>
50
51 PR binutils/21380
52 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
53 LD3R and LD4R.
54
42742084
AM		 552017-04-13 Alan Modra <amodra@gmail.com>
56
57 * epiphany-desc.c: Regenerate.
58 * fr30-desc.c: Regenerate.
59 * frv-desc.c: Regenerate.
60 * ip2k-desc.c: Regenerate.
61 * iq2000-desc.c: Regenerate.
62 * lm32-desc.c: Regenerate.
63 * m32c-desc.c: Regenerate.
64 * m32r-desc.c: Regenerate.
65 * mep-desc.c: Regenerate.
66 * mt-desc.c: Regenerate.
67 * or1k-desc.c: Regenerate.
68 * xc16x-desc.c: Regenerate.
69 * xstormy16-desc.c: Regenerate.
70
9a85b496
AM		 712017-04-11 Alan Modra <amodra@gmail.com>
72
ef85eab0 73 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 74 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
75 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 76 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
77 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 78 (PPCVSX2): Define as PPC_OPCODE_POWER8.
79 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 80 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 81 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 82
62adc510
AM		 832017-04-10 Alan Modra <amodra@gmail.com>
84
85 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
86 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
87 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
88 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
89
aa808707
PC		 902017-04-09 Pip Cet <pipcet@gmail.com>
91
92 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
93 appropriate floating-point precision directly.
94
ac8f0f72
AM		 952017-04-07 Alan Modra <amodra@gmail.com>
96
97 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
98 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
99 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
100 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
101 vector instructions with E6500 not PPCVEC2.
102
62ecb94c
PC		 1032017-04-06 Pip Cet <pipcet@gmail.com>
104
105 * Makefile.am: Add wasm32-dis.c.
106 * configure.ac: Add wasm32-dis.c to wasm32 target.
107 * disassemble.c: Add wasm32 disassembler code.
108 * wasm32-dis.c: New file.
109 * Makefile.in: Regenerate.
110 * configure: Regenerate.
111 * po/POTFILES.in: Regenerate.
112 * po/opcodes.pot: Regenerate.
113
f995bbe8
PA		 1142017-04-05 Pedro Alves <palves@redhat.com>
115
116 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
117 * arm-dis.c (parse_arm_disassembler_options): Constify.
118 * ppc-dis.c (powerpc_init_dialect): Constify local.
119 * vax-dis.c (parse_disassembler_options): Constify.
120
b5292032
PD		 1212017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
122
123 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
124 RISCV_GP_SYMBOL.
125
f96bd6c2
PC		 1262017-03-30 Pip Cet <pipcet@gmail.com>
127
128 * configure.ac: Add (empty) bfd_wasm32_arch target.
129 * configure: Regenerate
130 * po/opcodes.pot: Regenerate.
131
f7c514a3
JM		 1322017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
133
134 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
135 OSA2015.
136 * opcodes/sparc-opc.c (asi_table): New ASIs.
137
52be03fd
AM		 1382017-03-29 Alan Modra <amodra@gmail.com>
139
140 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
141 "raw" option.
142 (lookup_powerpc): Don't special case -1 dialect. Handle
143 PPC_OPCODE_RAW.
144 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
145 lookup_powerpc call, pass it on second.
146
9b753937
AM		 1472017-03-27 Alan Modra <amodra@gmail.com>
148
149 PR 21303
150 * ppc-dis.c (struct ppc_mopt): Comment.
151 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
152
c0c31e91
RZ		 1532017-03-27 Rinat Zelig <rinat@mellanox.com>
154
155 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
156 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
157 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
158 (insert_nps_misc_imm_offset): New function.
159 (extract_nps_misc imm_offset): New function.
160 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
161 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
162
2253c8f0
AK		 1632017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
164
165 * s390-mkopc.c (main): Remove vx2 check.
166 * s390-opc.txt: Remove vx2 instruction flags.
167
645d3342
RZ		 1682017-03-21 Rinat Zelig <rinat@mellanox.com>
169
170 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
171 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
172 (insert_nps_imm_offset): New function.
173 (extract_nps_imm_offset): New function.
174 (insert_nps_imm_entry): New function.
175 (extract_nps_imm_entry): New function.
176
4b94dd2d
AM		 1772017-03-17 Alan Modra <amodra@gmail.com>
178
179 PR 21248
180 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
181 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
182 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
183
b416fe87
KC		 1842017-03-14 Kito Cheng <kito.cheng@gmail.com>
185
186 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
187 <c.andi>: Likewise.
188 <c.addiw> Likewise.
189
03b039a5
KC		 1902017-03-14 Kito Cheng <kito.cheng@gmail.com>
191
192 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
193
2c232b83
AW		 1942017-03-13 Andrew Waterman <andrew@sifive.com>
195
196 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
197 <srl> Likewise.
198 <srai> Likewise.
199 <sra> Likewise.
200
86fa6981
L		 2012017-03-09 H.J. Lu <hongjiu.lu@intel.com>
202
203 * i386-gen.c (opcode_modifiers): Replace S with Load.
204 * i386-opc.h (S): Removed.
205 (Load): New.
206 (i386_opcode_modifier): Replace s with load.
207 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
208 and {evex}. Replace S with Load.
209 * i386-tbl.h: Regenerated.
210
c1fe188b
L		 2112017-03-09 H.J. Lu <hongjiu.lu@intel.com>
212
213 * i386-opc.tbl: Use CpuCET on rdsspq.
214 * i386-tbl.h: Regenerated.
215
4b8b687e
PB		 2162017-03-08 Peter Bergner <bergner@vnet.ibm.com>
217
218 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
219 <vsx>: Do not use PPC_OPCODE_VSX3;
220
1437d063
PB		 2212017-03-08 Peter Bergner <bergner@vnet.ibm.com>
222
223 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
224
603555e5
L		 2252017-03-06 H.J. Lu <hongjiu.lu@intel.com>
226
227 * i386-dis.c (REG_0F1E_MOD_3): New enum.
228 (MOD_0F1E_PREFIX_1): Likewise.
229 (MOD_0F38F5_PREFIX_2): Likewise.
230 (MOD_0F38F6_PREFIX_0): Likewise.
231 (RM_0F1E_MOD_3_REG_7): Likewise.
232 (PREFIX_MOD_0_0F01_REG_5): Likewise.
233 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
234 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
235 (PREFIX_0F1E): Likewise.
236 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
237 (PREFIX_0F38F5): Likewise.
238 (dis386_twobyte): Use PREFIX_0F1E.
239 (reg_table): Add REG_0F1E_MOD_3.
240 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
241 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
242 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
243 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
244 (three_byte_table): Use PREFIX_0F38F5.
245 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
246 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
247 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
248 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
249 PREFIX_MOD_3_0F01_REG_5_RM_2.
250 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
251 (cpu_flags): Add CpuCET.
252 * i386-opc.h (CpuCET): New enum.
253 (CpuUnused): Commented out.
254 (i386_cpu_flags): Add cpucet.
255 * i386-opc.tbl: Add Intel CET instructions.
256 * i386-init.h: Regenerated.
257 * i386-tbl.h: Likewise.
258
73f07bff
AM		 2592017-03-06 Alan Modra <amodra@gmail.com>
260
261 PR 21124
262 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
263 (extract_raq, extract_ras, extract_rbx): New functions.
264 (powerpc_operands): Use opposite corresponding insert function.
265 (Q_MASK): Define.
266 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
267 register restriction.
268
65b48a81
PB		 2692017-02-28 Peter Bergner <bergner@vnet.ibm.com>
270
271 * disassemble.c Include "safe-ctype.h".
272 (disassemble_init_for_target): Handle s390 init.
273 (remove_whitespace_and_extra_commas): New function.
274 (disassembler_options_cmp): Likewise.
275 * arm-dis.c: Include "libiberty.h".
276 (NUM_ELEM): Delete.
277 (regnames): Use long disassembler style names.
278 Add force-thumb and no-force-thumb options.
279 (NUM_ARM_REGNAMES): Rename from this...
280 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
281 (get_arm_regname_num_options): Delete.
282 (set_arm_regname_option): Likewise.
283 (get_arm_regnames): Likewise.
284 (parse_disassembler_options): Likewise.
285 (parse_arm_disassembler_option): Rename from this...
286 (parse_arm_disassembler_options): ...to this. Make static.
287 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
288 (print_insn): Use parse_arm_disassembler_options.
289 (disassembler_options_arm): New function.
290 (print_arm_disassembler_options): Handle updated regnames.
291 * ppc-dis.c: Include "libiberty.h".
292 (ppc_opts): Add "32" and "64" entries.
293 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
294 (powerpc_init_dialect): Add break to switch statement.
295 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
296 (disassembler_options_powerpc): New function.
297 (print_ppc_disassembler_options): Use ARRAY_SIZE.
298 Remove printing of "32" and "64".
299 * s390-dis.c: Include "libiberty.h".
300 (init_flag): Remove unneeded variable.
301 (struct s390_options_t): New structure type.
302 (options): New structure.
303 (init_disasm): Rename from this...
304 (disassemble_init_s390): ...to this. Add initializations for
305 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
306 (print_insn_s390): Delete call to init_disasm.
307 (disassembler_options_s390): New function.
308 (print_s390_disassembler_options): Print using information from
309 struct 'options'.
310 * po/opcodes.pot: Regenerate.
311
15c7c1d8
JB		 3122017-02-28 Jan Beulich <jbeulich@suse.com>
313
314 * i386-dis.c (PCMPESTR_Fixup): New.
315 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
316 (prefix_table): Use PCMPESTR_Fixup.
317 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
318 PCMPESTR_Fixup.
319 (vex_w_table): Delete VPCMPESTR{I,M} entries.
320 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
321 Split 64-bit and non-64-bit variants.
322 * opcodes/i386-tbl.h: Re-generate.
323
582e12bf
RS		 3242017-02-24 Richard Sandiford <richard.sandiford@arm.com>
325
326 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
327 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
328 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
329 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
330 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
331 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
332 (OP_SVE_V_HSD): New macros.
333 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
334 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
335 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
336 (aarch64_opcode_table): Add new SVE instructions.
337 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
338 for rotation operands. Add new SVE operands.
339 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
340 (ins_sve_quad_index): Likewise.
341 (ins_imm_rotate): Split into...
342 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
343 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
344 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
345 functions.
346 (aarch64_ins_sve_addr_ri_s4): New function.
347 (aarch64_ins_sve_quad_index): Likewise.
348 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
349 * aarch64-asm-2.c: Regenerate.
350 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
351 (ext_sve_quad_index): Likewise.
352 (ext_imm_rotate): Split into...
353 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
354 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
355 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
356 functions.
357 (aarch64_ext_sve_addr_ri_s4): New function.
358 (aarch64_ext_sve_quad_index): Likewise.
359 (aarch64_ext_sve_index): Allow quad indices.
360 (do_misc_decoding): Likewise.
361 * aarch64-dis-2.c: Regenerate.
362 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
363 aarch64_field_kinds.
364 (OPD_F_OD_MASK): Widen by one bit.
365 (OPD_F_NO_ZR): Bump accordingly.
366 (get_operand_field_width): New function.
367 * aarch64-opc.c (fields): Add new SVE fields.
368 (operand_general_constraint_met_p): Handle new SVE operands.
369 (aarch64_print_operand): Likewise.
370 * aarch64-opc-2.c: Regenerate.
371
f482d304
RS		 3722017-02-24 Richard Sandiford <richard.sandiford@arm.com>
373
374 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
375 (aarch64_feature_compnum): ...this.
376 (SIMD_V8_3): Replace with...
377 (COMPNUM): ...this.
378 (CNUM_INSN): New macro.
379 (aarch64_opcode_table): Use it for the complex number instructions.
380
7db2c588
JB		 3812017-02-24 Jan Beulich <jbeulich@suse.com>
382
383 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
384
1e9d41d4
SL		 3852017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
386
387 Add support for associating SPARC ASIs with an architecture level.
388 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
389 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
390 decoding of SPARC ASIs.
391
53c4d625
JB		 3922017-02-23 Jan Beulich <jbeulich@suse.com>
393
394 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
395 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
396
11648de5
JB		 3972017-02-21 Jan Beulich <jbeulich@suse.com>
398
399 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
400 1 (instead of to itself). Correct typo.
401
f98d33be
AW		 4022017-02-14 Andrew Waterman <andrew@sifive.com>
403
404 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
405 pseudoinstructions.
406
773fb663
RS		 4072017-02-15 Richard Sandiford <richard.sandiford@arm.com>
408
409 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
410 (aarch64_sys_reg_supported_p): Handle them.
411
cc07cda6
CZ		 4122017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
413
414 * arc-opc.c (UIMM6_20R): Define.
415 (SIMM12_20): Use above.
416 (SIMM12_20R): Define.
417 (SIMM3_5_S): Use above.
418 (UIMM7_A32_11R_S): Define.
419 (UIMM7_9_S): Use above.
420 (UIMM3_13R_S): Define.
421 (SIMM11_A32_7_S): Use above.
422 (SIMM9_8R): Define.
423 (UIMM10_A32_8_S): Use above.
424 (UIMM8_8R_S): Define.
425 (W6): Use above.
426 (arc_relax_opcodes): Use all above defines.
427
66a5a740
VG		 4282017-02-15 Vineet Gupta <vgupta@synopsys.com>
429
430 * arc-regs.h: Distinguish some of the registers different on
431 ARC700 and HS38 cpus.
432
7e0de605
AM		 4332017-02-14 Alan Modra <amodra@gmail.com>
434
435 PR 21118
436 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
437 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
438
54064fdb
AM		 4392017-02-11 Stafford Horne <shorne@gmail.com>
440 Alan Modra <amodra@gmail.com>
441
442 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
443 Use insn_bytes_value and insn_int_value directly instead. Don't
444 free allocated memory until function exit.
445
dce75bf9
NP		 4462017-02-10 Nicholas Piggin <npiggin@gmail.com>
447
448 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
449
1b7e3d2f
NC		 4502017-02-03 Nick Clifton <nickc@redhat.com>
451
452 PR 21096
453 * aarch64-opc.c (print_register_list): Ensure that the register
454 list index will fir into the tb buffer.
455 (print_register_offset_address): Likewise.
456 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
457
8ec5cf65
AD		 4582017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
459
460 PR 21056
461 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
462 instructions when the previous fetch packet ends with a 32-bit
463 instruction.
464
a1aa5e81
DD		 4652017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
466
467 * pru-opc.c: Remove vague reference to a future GDB port.
468
add3afb2
NC		 4692017-01-20 Nick Clifton <nickc@redhat.com>
470
471 * po/ga.po: Updated Irish translation.
472
c13a63b0
SN		 4732017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
474
475 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
476
9608051a
YQ		 4772017-01-13 Yao Qi <yao.qi@linaro.org>
478
479 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
480 if FETCH_DATA returns 0.
481 (m68k_scan_mask): Likewise.
482 (print_insn_m68k): Update code to handle -1 return value.
483
f622ea96
YQ		 4842017-01-13 Yao Qi <yao.qi@linaro.org>
485
486 * m68k-dis.c (enum print_insn_arg_error): New.
487 (NEXTBYTE): Replace -3 with
488 PRINT_INSN_ARG_MEMORY_ERROR.
489 (NEXTULONG): Likewise.
490 (NEXTSINGLE): Likewise.
491 (NEXTDOUBLE): Likewise.
492 (NEXTDOUBLE): Likewise.
493 (NEXTPACKED): Likewise.
494 (FETCH_ARG): Likewise.
495 (FETCH_DATA): Update comments.
496 (print_insn_arg): Update comments. Replace magic numbers with
497 enum.
498 (match_insn_m68k): Likewise.
499
620214f7
IT		 5002017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
501
502 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
503 * i386-dis-evex.h (evex_table): Updated.
504 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
505 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
506 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
507 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
508 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
509 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
510 * i386-init.h: Regenerate.
511 * i386-tbl.h: Ditto.
512
d95014a2
YQ		 5132017-01-12 Yao Qi <yao.qi@linaro.org>
514
515 * msp430-dis.c (msp430_singleoperand): Return -1 if
516 msp430dis_opcode_signed returns false.
517 (msp430_doubleoperand): Likewise.
518 (msp430_branchinstr): Return -1 if
519 msp430dis_opcode_unsigned returns false.
520 (msp430x_calla_instr): Likewise.
521 (print_insn_msp430): Likewise.
522
0ae60c3e
NC		 5232017-01-05 Nick Clifton <nickc@redhat.com>
524
525 PR 20946
526 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
527 could not be matched.
528 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
529 NULL.
530
d74d4880
SN		 5312017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
532
533 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
534 (aarch64_opcode_table): Use RCPC_INSN.
535
cc917fd9
KC		 5362017-01-03 Kito Cheng <kito.cheng@gmail.com>
537
538 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
539 extension.
540 * riscv-opcodes/all-opcodes: Likewise.
541
b52d3cfc
DP		 5422017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
543
544 * riscv-dis.c (print_insn_args): Add fall through comment.
545
f90c58d5
NC		 5462017-01-03 Nick Clifton <nickc@redhat.com>
547
548 * po/sr.po: New Serbian translation.
549 * configure.ac (ALL_LINGUAS): Add sr.
550 * configure: Regenerate.
551
f47b0d4a
AM		 5522017-01-02 Alan Modra <amodra@gmail.com>
553
554 * epiphany-desc.h: Regenerate.
555 * epiphany-opc.h: Regenerate.
556 * fr30-desc.h: Regenerate.
557 * fr30-opc.h: Regenerate.
558 * frv-desc.h: Regenerate.
559 * frv-opc.h: Regenerate.
560 * ip2k-desc.h: Regenerate.
561 * ip2k-opc.h: Regenerate.
562 * iq2000-desc.h: Regenerate.
563 * iq2000-opc.h: Regenerate.
564 * lm32-desc.h: Regenerate.
565 * lm32-opc.h: Regenerate.
566 * m32c-desc.h: Regenerate.
567 * m32c-opc.h: Regenerate.
568 * m32r-desc.h: Regenerate.
569 * m32r-opc.h: Regenerate.
570 * mep-desc.h: Regenerate.
571 * mep-opc.h: Regenerate.
572 * mt-desc.h: Regenerate.
573 * mt-opc.h: Regenerate.
574 * or1k-desc.h: Regenerate.
575 * or1k-opc.h: Regenerate.
576 * xc16x-desc.h: Regenerate.
577 * xc16x-opc.h: Regenerate.
578 * xstormy16-desc.h: Regenerate.
579 * xstormy16-opc.h: Regenerate.
580
2571583a
AM		 5812017-01-02 Alan Modra <amodra@gmail.com>
582
583 Update year range in copyright notice of all files.
584
5c1ad6b5 585For older changes see ChangeLog-2016
3499769a 586\f
5c1ad6b5 587Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 588
589Copying and distribution of this file, with or without modification,
590are permitted in any medium without royalty provided the copyright
591notice and this notice are preserved.
592
593Local Variables:
594mode: change-log
595left-margin: 8
596fill-column: 74
597version-control: never
598End:
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