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S12Z: Move opcode header to public include directory.
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
7ba3ba91
JD		 12018-07-28 John Darrington <john@darrington.wattle.id.au>
2
3 * s12z.h: Delete.
4
1bc60e56
L		 52018-08-14 H.J. Lu <hongjiu.lu@intel.com>
6
7 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
8 address with the addr32 prefix and without base nor index
9 registers.
10
d871f3f4
L		 112018-08-11 H.J. Lu <hongjiu.lu@intel.com>
12
13 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
14 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
15 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
16 (cpu_flags): Add CpuCMOV and CpuFXSR.
17 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
18 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
19 * i386-init.h: Regenerated.
20 * i386-tbl.h: Likewise.
21
b6523c37 222018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
23
24 * arc-regs.h: Update auxiliary registers.
25
e968fc9b
JB		 262018-08-06 Jan Beulich <jbeulich@suse.com>
27
28 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
29 (RegIP, RegIZ): Define.
30 * i386-reg.tbl: Adjust comments.
31 (rip): Use Qword instead of BaseIndex. Use RegIP.
32 (eip): Use Dword instead of BaseIndex. Use RegIP.
33 (riz): Add Qword. Use RegIZ.
34 (eiz): Add Dword. Use RegIZ.
35 * i386-tbl.h: Re-generate.
36
dbf8be89
JB		 372018-08-03 Jan Beulich <jbeulich@suse.com>
38
39 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
40 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
41 vpmovzxdq, vpmovzxwd): Remove NoRex64.
42 * i386-tbl.h: Re-generate.
43
c48dadc9
JB		 442018-08-03 Jan Beulich <jbeulich@suse.com>
45
46 * i386-gen.c (operand_types): Remove Mem field.
47 * i386-opc.h (union i386_operand_type): Remove mem field.
48 * i386-init.h, i386-tbl.h: Re-generate.
49
cb86a42a
AM		 502018-08-01 Alan Modra <amodra@gmail.com>
51
52 * po/POTFILES.in: Regenerate.
53
07cc0450
NC		 542018-07-31 Nick Clifton <nickc@redhat.com>
55
56 * po/sv.po: Updated Swedish translation.
57
1424ad86
JB		 582018-07-31 Jan Beulich <jbeulich@suse.com>
59
60 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
61 * i386-init.h, i386-tbl.h: Re-generate.
62
ae2387fe
JB		 632018-07-31 Jan Beulich <jbeulich@suse.com>
64
65 * i386-opc.h (ZEROING_MASKING) Rename to ...
66 (DYNAMIC_MASKING): ... this. Adjust comment.
67 * i386-opc.tbl (MaskingMorZ): Define.
68 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
69 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
70 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
71 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
72 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
73 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
74 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
75 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
76 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
77
6ff00b5e
JB		 782018-07-31 Jan Beulich <jbeulich@suse.com>
79
80 * i386-opc.tbl: Use element rather than vector size for AVX512*
81 scatter/gather insns.
82 * i386-tbl.h: Re-generate.
83
e951d5ca
JB		 842018-07-31 Jan Beulich <jbeulich@suse.com>
85
86 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
87 (cpu_flags): Drop CpuVREX.
88 * i386-opc.h (CpuVREX): Delete.
89 (union i386_cpu_flags): Remove cpuvrex.
90 * i386-init.h, i386-tbl.h: Re-generate.
91
eb41b248
JW		 922018-07-30 Jim Wilson <jimw@sifive.com>
93
94 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
95 fields.
96 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
97
b8891f8d
AJ		 982018-07-30 Andrew Jenner <andrew@codesourcery.com>
99
100 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
101 * Makefile.in: Regenerated.
102 * configure.ac: Add C-SKY.
103 * configure: Regenerated.
104 * csky-dis.c: New file.
105 * csky-opc.h: New file.
106 * disassemble.c (ARCH_csky): Define.
107 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
108 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
109
16065af1
AM		 1102018-07-27 Alan Modra <amodra@gmail.com>
111
112 * ppc-opc.c (insert_sprbat): Correct function parameter and
113 return type.
114 (extract_sprbat): Likewise, variable too.
115
fa758a70
AC		 1162018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
117 Alan Modra <amodra@gmail.com>
118
119 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
120 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
121 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
122 support disjointed BAT.
123 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
124 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
125 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
126
4a1b91ea
L		 1272018-07-25 H.J. Lu <hongjiu.lu@intel.com>
128 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
129
130 * i386-gen.c (adjust_broadcast_modifier): New function.
131 (process_i386_opcode_modifier): Add an argument for operands.
132 Adjust the Broadcast value based on operands.
133 (output_i386_opcode): Pass operand_types to
134 process_i386_opcode_modifier.
135 (process_i386_opcodes): Pass NULL as operands to
136 process_i386_opcode_modifier.
137 * i386-opc.h (BYTE_BROADCAST): New.
138 (WORD_BROADCAST): Likewise.
139 (DWORD_BROADCAST): Likewise.
140 (QWORD_BROADCAST): Likewise.
141 (i386_opcode_modifier): Expand broadcast to 3 bits.
142 * i386-tbl.h: Regenerated.
143
67ce483b
AM		 1442018-07-24 Alan Modra <amodra@gmail.com>
145
146 PR 23430
147 * or1k-desc.h: Regenerate.
148
4174bfff
JB		 1492018-07-24 Jan Beulich <jbeulich@suse.com>
150
151 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
152 vcvtusi2ss, and vcvtusi2sd.
153 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
154 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
155 * i386-tbl.h: Re-generate.
156
04e65276
CZ		 1572018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
158
159 * arc-opc.c (extract_w6): Fix extending the sign.
160
47e6f81c
CZ		 1612018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
162
163 * arc-tbl.h (vewt): Allow it for ARC EM family.
164
bb71536f
AM		 1652018-07-23 Alan Modra <amodra@gmail.com>
166
167 PR 23419
168 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
169 opcode variants for mtspr/mfspr encodings.
170
8095d2f7
CX		 1712018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
172 Maciej W. Rozycki <macro@mips.com>
173
174 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
175 loongson3a descriptors.
176 (parse_mips_ase_option): Handle -M loongson-mmi option.
177 (print_mips_disassembler_options): Document -M loongson-mmi.
178 * mips-opc.c (LMMI): New macro.
179 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
180 instructions.
181
5f32791e
JB		 1822018-07-19 Jan Beulich <jbeulich@suse.com>
183
184 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
185 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
186 IgnoreSize and [XYZ]MMword where applicable.
187 * i386-tbl.h: Re-generate.
188
625cbd7a
JB		 1892018-07-19 Jan Beulich <jbeulich@suse.com>
190
191 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
192 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
193 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
194 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
195 * i386-tbl.h: Re-generate.
196
86b15c32
JB		 1972018-07-19 Jan Beulich <jbeulich@suse.com>
198
199 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
200 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
201 VPCLMULQDQ templates into their respective AVX512VL counterparts
202 where possible, using Disp8ShiftVL and CheckRegSize instead of
203 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
204 * i386-tbl.h: Re-generate.
205
cf769ed5
JB		 2062018-07-19 Jan Beulich <jbeulich@suse.com>
207
208 * i386-opc.tbl: Fold AVX512DQ templates into their respective
209 AVX512VL counterparts where possible, using Disp8ShiftVL and
210 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
211 IgnoreSize) as appropriate.
212 * i386-tbl.h: Re-generate.
213
8282b7ad
JB		 2142018-07-19 Jan Beulich <jbeulich@suse.com>
215
216 * i386-opc.tbl: Fold AVX512BW templates into their respective
217 AVX512VL counterparts where possible, using Disp8ShiftVL and
218 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
219 IgnoreSize) as appropriate.
220 * i386-tbl.h: Re-generate.
221
755908cc
JB		 2222018-07-19 Jan Beulich <jbeulich@suse.com>
223
224 * i386-opc.tbl: Fold AVX512CD templates into their respective
225 AVX512VL counterparts where possible, using Disp8ShiftVL and
226 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
227 IgnoreSize) as appropriate.
228 * i386-tbl.h: Re-generate.
229
7091c612
JB		 2302018-07-19 Jan Beulich <jbeulich@suse.com>
231
232 * i386-opc.h (DISP8_SHIFT_VL): New.
233 * i386-opc.tbl (Disp8ShiftVL): Define.
234 (various): Fold AVX512VL templates into their respective
235 AVX512F counterparts where possible, using Disp8ShiftVL and
236 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
237 IgnoreSize) as appropriate.
238 * i386-tbl.h: Re-generate.
239
c30be56e
JB		 2402018-07-19 Jan Beulich <jbeulich@suse.com>
241
242 * Makefile.am: Change dependencies and rule for
243 $(srcdir)/i386-init.h.
244 * Makefile.in: Re-generate.
245 * i386-gen.c (process_i386_opcodes): New local variable
246 "marker". Drop opening of input file. Recognize marker and line
247 number directives.
248 * i386-opc.tbl (OPCODE_I386_H): Define.
249 (i386-opc.h): Include it.
250 (None): Undefine.
251
11a322db
L		 2522018-07-18 H.J. Lu <hongjiu.lu@intel.com>
253
254 PR gas/23418
255 * i386-opc.h (Byte): Update comments.
256 (Word): Likewise.
257 (Dword): Likewise.
258 (Fword): Likewise.
259 (Qword): Likewise.
260 (Tbyte): Likewise.
261 (Xmmword): Likewise.
262 (Ymmword): Likewise.
263 (Zmmword): Likewise.
264 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
265 vcvttps2uqq.
266 * i386-tbl.h: Regenerated.
267
cde3679e
NC		 2682018-07-12 Sudakshina Das <sudi.das@arm.com>
269
270 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
271 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
272 * aarch64-asm-2.c: Regenerate.
273 * aarch64-dis-2.c: Regenerate.
274 * aarch64-opc-2.c: Regenerate.
275
45a28947
TC		 2762018-07-12 Tamar Christina <tamar.christina@arm.com>
277
278 PR binutils/23192
279 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
280 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
281 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
282 sqdmulh, sqrdmulh): Use Em16.
283
c597cc3d
SD		 2842018-07-11 Sudakshina Das <sudi.das@arm.com>
285
286 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
287 csdb together with them.
288 (thumb32_opcodes): Likewise.
289
a79eaed6
JB		 2902018-07-11 Jan Beulich <jbeulich@suse.com>
291
292 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
293 requiring 32-bit registers as operands 2 and 3. Improve
294 comments.
295 (mwait, mwaitx): Fold templates. Improve comments.
296 OPERAND_TYPE_INOUTPORTREG.
297 * i386-tbl.h: Re-generate.
298
2fb5be8d
JB		 2992018-07-11 Jan Beulich <jbeulich@suse.com>
300
301 * i386-gen.c (operand_type_init): Remove
302 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
303 OPERAND_TYPE_INOUTPORTREG.
304 * i386-init.h: Re-generate.
305
7f5cad30
JB		 3062018-07-11 Jan Beulich <jbeulich@suse.com>
307
308 * i386-opc.tbl (wrssd, wrussd): Add Dword.
309 (wrssq, wrussq): Add Qword.
310 * i386-tbl.h: Re-generate.
311
f0a85b07
JB		 3122018-07-11 Jan Beulich <jbeulich@suse.com>
313
314 * i386-opc.h: Rename OTMax to OTNum.
315 (OTNumOfUints): Adjust calculation.
316 (OTUnused): Directly alias to OTNum.
317
9dcb0ba4
MR		 3182018-07-09 Maciej W. Rozycki <macro@mips.com>
319
320 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
321 `reg_xys'.
322 (lea_reg_xys): Likewise.
323 (print_insn_loop_primitive): Rename `reg' local variable to
324 `reg_dxy'.
325
f311ba7e
TC		 3262018-07-06 Tamar Christina <tamar.christina@arm.com>
327
328 PR binutils/23242
329 * aarch64-tbl.h (ldarh): Fix disassembly mask.
330
cba05feb
TC		 3312018-07-06 Tamar Christina <tamar.christina@arm.com>
332
333 PR binutils/23369
334 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
335 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
336
471b9d15
MR		 3372018-07-02 Maciej W. Rozycki <macro@mips.com>
338
339 PR tdep/8282
340 * mips-dis.c (mips_option_arg_t): New enumeration.
341 (mips_options): New variable.
342 (disassembler_options_mips): New function.
343 (print_mips_disassembler_options): Reimplement in terms of
344 `disassembler_options_mips'.
345 * arm-dis.c (disassembler_options_arm): Adapt to using the
346 `disasm_options_and_args_t' structure.
347 * ppc-dis.c (disassembler_options_powerpc): Likewise.
348 * s390-dis.c (disassembler_options_s390): Likewise.
349
c0c468d5
TP		 3502018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
351
352 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
353 expected result.
354 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
355 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
356 * testsuite/ld-arm/tls-longplt.d: Likewise.
357
369c9167
TC		 3582018-06-29 Tamar Christina <tamar.christina@arm.com>
359
360 PR binutils/23192
361 * aarch64-asm-2.c: Regenerate.
362 * aarch64-dis-2.c: Likewise.
363 * aarch64-opc-2.c: Likewise.
364 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
365 * aarch64-opc.c (operand_general_constraint_met_p,
366 aarch64_print_operand): Likewise.
367 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
368 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
369 fmlal2, fmlsl2.
370 (AARCH64_OPERANDS): Add Em2.
371
30aa1306
NC		 3722018-06-26 Nick Clifton <nickc@redhat.com>
373
374 * po/uk.po: Updated Ukranian translation.
375 * po/de.po: Updated German translation.
376 * po/pt_BR.po: Updated Brazilian Portuguese translation.
377
eca4b721
NC		 3782018-06-26 Nick Clifton <nickc@redhat.com>
379
380 * nfp-dis.c: Fix spelling mistake.
381
71300e2c
NC		 3822018-06-24 Nick Clifton <nickc@redhat.com>
383
384 * configure: Regenerate.
385 * po/opcodes.pot: Regenerate.
386
719d8288
NC		 3872018-06-24 Nick Clifton <nickc@redhat.com>
388
389 2.31 branch created.
390
514cd3a0
TC		 3912018-06-19 Tamar Christina <tamar.christina@arm.com>
392
393 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
394 * aarch64-asm-2.c: Regenerate.
395 * aarch64-dis-2.c: Likewise.
396
385e4d0f
MR		 3972018-06-21 Maciej W. Rozycki <macro@mips.com>
398
399 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
400 `-M ginv' option description.
401
160d1b3d
SH		 4022018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
403
404 PR gas/23305
405 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
406 la and lla.
407
d0ac1c44
SM		 4082018-06-19 Simon Marchi <simon.marchi@ericsson.com>
409
410 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
411 * configure.ac: Remove AC_PREREQ.
412 * Makefile.in: Re-generate.
413 * aclocal.m4: Re-generate.
414 * configure: Re-generate.
415
6f20c942
FS		 4162018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
417
418 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
419 mips64r6 descriptors.
420 (parse_mips_ase_option): Handle -Mginv option.
421 (print_mips_disassembler_options): Document -Mginv.
422 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
423 (GINV): New macro.
424 (mips_opcodes): Define ginvi and ginvt.
425
730c3174
SE		 4262018-06-13 Scott Egerton <scott.egerton@imgtec.com>
427 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
428
429 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
430 * mips-opc.c (CRC, CRC64): New macros.
431 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
432 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
433 crc32cd for CRC64.
434
cb366992
EB		 4352018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
436
437 PR 20319
438 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
439 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
440
ce72cd46
AM		 4412018-06-06 Alan Modra <amodra@gmail.com>
442
443 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
444 setjmp. Move init for some other vars later too.
445
4b8e28c7
MF		 4462018-06-04 Max Filippov <jcmvbkbc@gmail.com>
447
448 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
449 (dis_private): Add new fields for property section tracking.
450 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
451 (xtensa_instruction_fits): New functions.
452 (fetch_data): Bump minimal fetch size to 4.
453 (print_insn_xtensa): Make struct dis_private static.
454 Load and prepare property table on section change.
455 Don't disassemble literals. Don't disassemble instructions that
456 cross property table boundaries.
457
55e99962
L		 4582018-06-01 H.J. Lu <hongjiu.lu@intel.com>
459
460 * configure: Regenerated.
461
733bd0ab
JB		 4622018-06-01 Jan Beulich <jbeulich@suse.com>
463
464 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
465 * i386-tbl.h: Re-generate.
466
dfd27d41
JB		 4672018-06-01 Jan Beulich <jbeulich@suse.com>
468
469 * i386-opc.tbl (sldt, str): Add NoRex64.
470 * i386-tbl.h: Re-generate.
471
64795710
JB		 4722018-06-01 Jan Beulich <jbeulich@suse.com>
473
474 * i386-opc.tbl (invpcid): Add Oword.
475 * i386-tbl.h: Re-generate.
476
030157d8
AM		 4772018-06-01 Alan Modra <amodra@gmail.com>
478
479 * sysdep.h (_bfd_error_handler): Don't declare.
480 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
481 * rl78-decode.opc: Likewise.
482 * msp430-decode.c: Regenerate.
483 * rl78-decode.c: Regenerate.
484
a9660a6f
AP		 4852018-05-30 Amit Pawar <Amit.Pawar@amd.com>
486
487 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
488 * i386-init.h : Regenerated.
489
277eb7f6
AM		 4902018-05-25 Alan Modra <amodra@gmail.com>
491
492 * Makefile.in: Regenerate.
493 * po/POTFILES.in: Regenerate.
494
98553ad3
PB		 4952018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
496
497 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
498 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
499 (insert_bab, extract_bab, insert_btab, extract_btab,
500 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
501 (BAT, BBA VBA RBS XB6S): Delete macros.
502 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
503 (BB, BD, RBX, XC6): Update for new macros.
504 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
505 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
506 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
507 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
508
7b4ae824
JD		 5092018-05-18 John Darrington <john@darrington.wattle.id.au>
510
511 * Makefile.am: Add support for s12z architecture.
512 * configure.ac: Likewise.
513 * disassemble.c: Likewise.
514 * disassemble.h: Likewise.
515 * Makefile.in: Regenerate.
516 * configure: Regenerate.
517 * s12z-dis.c: New file.
518 * s12z.h: New file.
519
29e0f0a1
AM		 5202018-05-18 Alan Modra <amodra@gmail.com>
521
522 * nfp-dis.c: Don't #include libbfd.h.
523 (init_nfp3200_priv): Use bfd_get_section_contents.
524 (nit_nfp6000_mecsr_sec): Likewise.
525
809276d2
NC		 5262018-05-17 Nick Clifton <nickc@redhat.com>
527
528 * po/zh_CN.po: Updated simplified Chinese translation.
529
ff329288
TC		 5302018-05-16 Tamar Christina <tamar.christina@arm.com>
531
532 PR binutils/23109
533 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
534 * aarch64-dis-2.c: Regenerate.
535
f9830ec1
TC		 5362018-05-15 Tamar Christina <tamar.christina@arm.com>
537
538 PR binutils/21446
539 * aarch64-asm.c (opintl.h): Include.
540 (aarch64_ins_sysreg): Enforce read/write constraints.
541 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
542 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
543 (F_REG_READ, F_REG_WRITE): New.
544 * aarch64-opc.c (aarch64_print_operand): Generate notes for
545 AARCH64_OPND_SYSREG.
546 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
547 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
548 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
549 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
550 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
551 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
552 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
553 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
554 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
555 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
556 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
557 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
558 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
559 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
560 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
561 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
562 msr (F_SYS_WRITE), mrs (F_SYS_READ).
563
7d02540a
TC		 5642018-05-15 Tamar Christina <tamar.christina@arm.com>
565
566 PR binutils/21446
567 * aarch64-dis.c (no_notes: New.
568 (parse_aarch64_dis_option): Support notes.
569 (aarch64_decode_insn, print_operands): Likewise.
570 (print_aarch64_disassembler_options): Document notes.
571 * aarch64-opc.c (aarch64_print_operand): Support notes.
572
561a72d4
TC		 5732018-05-15 Tamar Christina <tamar.christina@arm.com>
574
575 PR binutils/21446
576 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
577 and take error struct.
578 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
579 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
580 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
581 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
582 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
583 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
584 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
585 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
586 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
587 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
588 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
589 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
590 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
591 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
592 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
593 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
594 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
595 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
596 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
597 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
598 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
599 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
600 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
601 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
602 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
603 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
604 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
605 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
606 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
607 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
608 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
609 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
610 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
611 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
612 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
613 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
614 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
615 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
616 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
617 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
618 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
619 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
620 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
621 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
622 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
623 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
624 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
625 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
626 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
627 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
628 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
629 (determine_disassembling_preference, aarch64_decode_insn,
630 print_insn_aarch64_word, print_insn_data): Take errors struct.
631 (print_insn_aarch64): Use errors.
632 * aarch64-asm-2.c: Regenerate.
633 * aarch64-dis-2.c: Regenerate.
634 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
635 boolean in aarch64_insert_operan.
636 (print_operand_extractor): Likewise.
637 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
638
1678bd35
FT		 6392018-05-15 Francois H. Theron <francois.theron@netronome.com>
640
641 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
642
06cfb1c8
L		 6432018-05-09 H.J. Lu <hongjiu.lu@intel.com>
644
645 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
646
84f9f8c3
AM		 6472018-05-09 Sebastian Rasmussen <sebras@gmail.com>
648
649 * cr16-opc.c (cr16_instruction): Comment typo fix.
650 * hppa-dis.c (print_insn_hppa): Likewise.
651
e6f372ba
JW		 6522018-05-08 Jim Wilson <jimw@sifive.com>
653
654 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
655 (match_c_slli64, match_srxi_as_c_srxi): New.
656 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
657 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
658 <c.slli, c.srli, c.srai>: Use match_s_slli.
659 <c.slli64, c.srli64, c.srai64>: New.
660
f413a913
AM		 6612018-05-08 Alan Modra <amodra@gmail.com>
662
663 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
664 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
665 partition opcode space for index lookup.
666
a87a6478
PB		 6672018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
668
669 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
670 <insn_length>: ...with this. Update usage.
671 Remove duplicate call to *info->memory_error_func.
672
c0a30a9f
L		 6732018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
674 H.J. Lu <hongjiu.lu@intel.com>
675
676 * i386-dis.c (Gva): New.
677 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
678 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
679 (prefix_table): New instructions (see prefix above).
680 (mod_table): New instructions (see prefix above).
681 (OP_G): Handle va_mode.
682 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
683 CPU_MOVDIR64B_FLAGS.
684 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
685 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
686 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
687 * i386-opc.tbl: Add movidir{i,64b}.
688 * i386-init.h: Regenerated.
689 * i386-tbl.h: Likewise.
690
75c0a438
L		 6912018-05-07 H.J. Lu <hongjiu.lu@intel.com>
692
693 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
694 AddrPrefixOpReg.
695 * i386-opc.h (AddrPrefixOp0): Renamed to ...
696 (AddrPrefixOpReg): This.
697 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
698 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
699
2ceb7719
PB		 7002018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
701
702 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
703 (vle_num_opcodes): Likewise.
704 (spe2_num_opcodes): Likewise.
705 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
706 initialization loop.
707 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
708 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
709 only once.
710
b3ac5c6c
TC		 7112018-05-01 Tamar Christina <tamar.christina@arm.com>
712
713 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
714
fe944acf
FT		 7152018-04-30 Francois H. Theron <francois.theron@netronome.com>
716
717 Makefile.am: Added nfp-dis.c.
718 configure.ac: Added bfd_nfp_arch.
719 disassemble.h: Added print_insn_nfp prototype.
720 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
721 nfp-dis.c: New, for NFP support.
722 po/POTFILES.in: Added nfp-dis.c to the list.
723 Makefile.in: Regenerate.
724 configure: Regenerate.
725
e2195274
JB		 7262018-04-26 Jan Beulich <jbeulich@suse.com>
727
728 * i386-opc.tbl: Fold various non-memory operand AVX512VL
729 templates into their base ones.
730 * i386-tlb.h: Re-generate.
731
59ef5df4
JB		 7322018-04-26 Jan Beulich <jbeulich@suse.com>
733
734 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
735 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
736 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
737 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
738 * i386-init.h: Re-generate.
739
6e041cf4
JB		 7402018-04-26 Jan Beulich <jbeulich@suse.com>
741
742 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
743 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
744 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
745 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
746 comment.
747 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
748 and CpuRegMask.
749 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
750 CpuRegMask: Delete.
751 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
752 cpuregzmm, and cpuregmask.
753 * i386-init.h: Re-generate.
754 * i386-tbl.h: Re-generate.
755
0e0eea78
JB		 7562018-04-26 Jan Beulich <jbeulich@suse.com>
757
758 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
759 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
760 * i386-init.h: Re-generate.
761
2f1bada2
JB		 7622018-04-26 Jan Beulich <jbeulich@suse.com>
763
764 * i386-gen.c (VexImmExt): Delete.
765 * i386-opc.h (VexImmExt, veximmext): Delete.
766 * i386-opc.tbl: Drop all VexImmExt uses.
767 * i386-tlb.h: Re-generate.
768
bacd1457
JB		 7692018-04-25 Jan Beulich <jbeulich@suse.com>
770
771 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
772 register-only forms.
773 * i386-tlb.h: Re-generate.
774
10bba94b
TC		 7752018-04-25 Tamar Christina <tamar.christina@arm.com>
776
777 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
778
c48935d7
IT		 7792018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
780
781 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
782 PREFIX_0F1C.
783 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
784 (cpu_flags): Add CpuCLDEMOTE.
785 * i386-init.h: Regenerate.
786 * i386-opc.h (enum): Add CpuCLDEMOTE,
787 (i386_cpu_flags): Add cpucldemote.
788 * i386-opc.tbl: Add cldemote.
789 * i386-tbl.h: Regenerate.
790
211dc24b
AM		 7912018-04-16 Alan Modra <amodra@gmail.com>
792
793 * Makefile.am: Remove sh5 and sh64 support.
794 * configure.ac: Likewise.
795 * disassemble.c: Likewise.
796 * disassemble.h: Likewise.
797 * sh-dis.c: Likewise.
798 * sh64-dis.c: Delete.
799 * sh64-opc.c: Delete.
800 * sh64-opc.h: Delete.
801 * Makefile.in: Regenerate.
802 * configure: Regenerate.
803 * po/POTFILES.in: Regenerate.
804
a9a4b302
AM		 8052018-04-16 Alan Modra <amodra@gmail.com>
806
807 * Makefile.am: Remove w65 support.
808 * configure.ac: Likewise.
809 * disassemble.c: Likewise.
810 * disassemble.h: Likewise.
811 * w65-dis.c: Delete.
812 * w65-opc.h: Delete.
813 * Makefile.in: Regenerate.
814 * configure: Regenerate.
815 * po/POTFILES.in: Regenerate.
816
04cb01fd
AM		 8172018-04-16 Alan Modra <amodra@gmail.com>
818
819 * configure.ac: Remove we32k support.
820 * configure: Regenerate.
821
c2bf1eec
AM		 8222018-04-16 Alan Modra <amodra@gmail.com>
823
824 * Makefile.am: Remove m88k support.
825 * configure.ac: Likewise.
826 * disassemble.c: Likewise.
827 * disassemble.h: Likewise.
828 * m88k-dis.c: Delete.
829 * Makefile.in: Regenerate.
830 * configure: Regenerate.
831 * po/POTFILES.in: Regenerate.
832
6793974d
AM		 8332018-04-16 Alan Modra <amodra@gmail.com>
834
835 * Makefile.am: Remove i370 support.
836 * configure.ac: Likewise.
837 * disassemble.c: Likewise.
838 * disassemble.h: Likewise.
839 * i370-dis.c: Delete.
840 * i370-opc.c: Delete.
841 * Makefile.in: Regenerate.
842 * configure: Regenerate.
843 * po/POTFILES.in: Regenerate.
844
e82aa794
AM		 8452018-04-16 Alan Modra <amodra@gmail.com>
846
847 * Makefile.am: Remove h8500 support.
848 * configure.ac: Likewise.
849 * disassemble.c: Likewise.
850 * disassemble.h: Likewise.
851 * h8500-dis.c: Delete.
852 * h8500-opc.h: Delete.
853 * Makefile.in: Regenerate.
854 * configure: Regenerate.
855 * po/POTFILES.in: Regenerate.
856
fceadf09
AM		 8572018-04-16 Alan Modra <amodra@gmail.com>
858
859 * configure.ac: Remove tahoe support.
860 * configure: Regenerate.
861
ae1d3843
L		 8622018-04-15 H.J. Lu <hongjiu.lu@intel.com>
863
864 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
865 umwait.
866 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
867 64-bit mode.
868 * i386-tbl.h: Regenerated.
869
de89d0a3
IT		 8702018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
871
872 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
873 PREFIX_MOD_1_0FAE_REG_6.
874 (va_mode): New.
875 (OP_E_register): Use va_mode.
876 * i386-dis-evex.h (prefix_table):
877 New instructions (see prefixes above).
878 * i386-gen.c (cpu_flag_init): Add WAITPKG.
879 (cpu_flags): Likewise.
880 * i386-opc.h (enum): Likewise.
881 (i386_cpu_flags): Likewise.
882 * i386-opc.tbl: Add umonitor, umwait, tpause.
883 * i386-init.h: Regenerate.
884 * i386-tbl.h: Likewise.
885
a8eb42a8
AM		 8862018-04-11 Alan Modra <amodra@gmail.com>
887
888 * opcodes/i860-dis.c: Delete.
889 * opcodes/i960-dis.c: Delete.
890 * Makefile.am: Remove i860 and i960 support.
891 * configure.ac: Likewise.
892 * disassemble.c: Likewise.
893 * disassemble.h: Likewise.
894 * Makefile.in: Regenerate.
895 * configure: Regenerate.
896 * po/POTFILES.in: Regenerate.
897
caf0678c
L		 8982018-04-04 H.J. Lu <hongjiu.lu@intel.com>
899
900 PR binutils/23025
901 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
902 to 0.
903 (print_insn): Clear vex instead of vex.evex.
904
4fb0d2b9
NC		 9052018-04-04 Nick Clifton <nickc@redhat.com>
906
907 * po/es.po: Updated Spanish translation.
908
c39e5b26
JB		 9092018-03-28 Jan Beulich <jbeulich@suse.com>
910
911 * i386-gen.c (opcode_modifiers): Delete VecESize.
912 * i386-opc.h (VecESize): Delete.
913 (struct i386_opcode_modifier): Delete vecesize.
914 * i386-opc.tbl: Drop VecESize.
915 * i386-tlb.h: Re-generate.
916
8e6e0792
JB		 9172018-03-28 Jan Beulich <jbeulich@suse.com>
918
919 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
920 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
921 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
922 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
923 * i386-tlb.h: Re-generate.
924
9f123b91
JB		 9252018-03-28 Jan Beulich <jbeulich@suse.com>
926
927 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
928 Fold AVX512 forms
929 * i386-tlb.h: Re-generate.
930
9646c87b
JB		 9312018-03-28 Jan Beulich <jbeulich@suse.com>
932
933 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
934 (vex_len_table): Drop Y for vcvt*2si.
935 (putop): Replace plain 'Y' handling by abort().
936
c8d59609
NC		 9372018-03-28 Nick Clifton <nickc@redhat.com>
938
939 PR 22988
940 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
941 instructions with only a base address register.
942 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
943 handle AARHC64_OPND_SVE_ADDR_R.
944 (aarch64_print_operand): Likewise.
945 * aarch64-asm-2.c: Regenerate.
946 * aarch64_dis-2.c: Regenerate.
947 * aarch64-opc-2.c: Regenerate.
948
b8c169f3
JB		 9492018-03-22 Jan Beulich <jbeulich@suse.com>
950
951 * i386-opc.tbl: Drop VecESize from register only insn forms and
952 memory forms not allowing broadcast.
953 * i386-tlb.h: Re-generate.
954
96bc132a
JB		 9552018-03-22 Jan Beulich <jbeulich@suse.com>
956
957 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
958 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
959 sha256*): Drop Disp<N>.
960
9f79e886
JB		 9612018-03-22 Jan Beulich <jbeulich@suse.com>
962
963 * i386-dis.c (EbndS, bnd_swap_mode): New.
964 (prefix_table): Use EbndS.
965 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
966 * i386-opc.tbl (bndmov): Move misplaced Load.
967 * i386-tlb.h: Re-generate.
968
d6793fa1
JB		 9692018-03-22 Jan Beulich <jbeulich@suse.com>
970
971 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
972 templates allowing memory operands and folded ones for register
973 only flavors.
974 * i386-tlb.h: Re-generate.
975
f7768225
JB		 9762018-03-22 Jan Beulich <jbeulich@suse.com>
977
978 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
979 256-bit templates. Drop redundant leftover Disp<N>.
980 * i386-tlb.h: Re-generate.
981
0e35537d
JW		 9822018-03-14 Kito Cheng <kito.cheng@gmail.com>
983
984 * riscv-opc.c (riscv_insn_types): New.
985
b4a3689a
NC		 9862018-03-13 Nick Clifton <nickc@redhat.com>
987
988 * po/pt_BR.po: Updated Brazilian Portuguese translation.
989
d3d50934
L		 9902018-03-08 H.J. Lu <hongjiu.lu@intel.com>
991
992 * i386-opc.tbl: Add Optimize to clr.
993 * i386-tbl.h: Regenerated.
994
bd5dea88
L		 9952018-03-08 H.J. Lu <hongjiu.lu@intel.com>
996
997 * i386-gen.c (opcode_modifiers): Remove OldGcc.
998 * i386-opc.h (OldGcc): Removed.
999 (i386_opcode_modifier): Remove oldgcc.
1000 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1001 instructions for old (<= 2.8.1) versions of gcc.
1002 * i386-tbl.h: Regenerated.
1003
e771e7c9
JB		 10042018-03-08 Jan Beulich <jbeulich@suse.com>
1005
1006 * i386-opc.h (EVEXDYN): New.
1007 * i386-opc.tbl: Fold various AVX512VL templates.
1008 * i386-tlb.h: Re-generate.
1009
ed438a93
JB		 10102018-03-08 Jan Beulich <jbeulich@suse.com>
1011
1012 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1013 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1014 vpexpandd, vpexpandq): Fold AFX512VF templates.
1015 * i386-tlb.h: Re-generate.
1016
454172a9
JB		 10172018-03-08 Jan Beulich <jbeulich@suse.com>
1018
1019 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1020 Fold 128- and 256-bit VEX-encoded templates.
1021 * i386-tlb.h: Re-generate.
1022
36824150
JB		 10232018-03-08 Jan Beulich <jbeulich@suse.com>
1024
1025 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1026 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1027 vpexpandd, vpexpandq): Fold AVX512F templates.
1028 * i386-tlb.h: Re-generate.
1029
e7f5c0a9
JB		 10302018-03-08 Jan Beulich <jbeulich@suse.com>
1031
1032 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1033 64-bit templates. Drop Disp<N>.
1034 * i386-tlb.h: Re-generate.
1035
25a4277f
JB		 10362018-03-08 Jan Beulich <jbeulich@suse.com>
1037
1038 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1039 and 256-bit templates.
1040 * i386-tlb.h: Re-generate.
1041
d2224064
JB		 10422018-03-08 Jan Beulich <jbeulich@suse.com>
1043
1044 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1045 * i386-tlb.h: Re-generate.
1046
1b193f0b
JB		 10472018-03-08 Jan Beulich <jbeulich@suse.com>
1048
1049 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1050 Drop NoAVX.
1051 * i386-tlb.h: Re-generate.
1052
f2f6a710
JB		 10532018-03-08 Jan Beulich <jbeulich@suse.com>
1054
1055 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1056 * i386-tlb.h: Re-generate.
1057
38e314eb
JB		 10582018-03-08 Jan Beulich <jbeulich@suse.com>
1059
1060 * i386-gen.c (opcode_modifiers): Delete FloatD.
1061 * i386-opc.h (FloatD): Delete.
1062 (struct i386_opcode_modifier): Delete floatd.
1063 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1064 FloatD by D.
1065 * i386-tlb.h: Re-generate.
1066
d53e6b98
JB		 10672018-03-08 Jan Beulich <jbeulich@suse.com>
1068
1069 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1070
2907c2f5
JB		 10712018-03-08 Jan Beulich <jbeulich@suse.com>
1072
1073 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1074 * i386-tlb.h: Re-generate.
1075
73053c1f
JB		 10762018-03-08 Jan Beulich <jbeulich@suse.com>
1077
1078 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1079 forms.
1080 * i386-tlb.h: Re-generate.
1081
52fe4420
AM		 10822018-03-07 Alan Modra <amodra@gmail.com>
1083
1084 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1085 bfd_arch_rs6000.
1086 * disassemble.h (print_insn_rs6000): Delete.
1087 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1088 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1089 (print_insn_rs6000): Delete.
1090
a6743a54
AM		 10912018-03-03 Alan Modra <amodra@gmail.com>
1092
1093 * sysdep.h (opcodes_error_handler): Define.
1094 (_bfd_error_handler): Declare.
1095 * Makefile.am: Remove stray #.
1096 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1097 EDIT" comment.
1098 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1099 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1100 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1101 opcodes_error_handler to print errors. Standardize error messages.
1102 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1103 and include opintl.h.
1104 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1105 * i386-gen.c: Standardize error messages.
1106 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1107 * Makefile.in: Regenerate.
1108 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1109 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1110 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1111 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1112 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1113 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1114 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1115 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1116 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1117 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1118 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1119 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1120 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1121
8305403a
L		 11222018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1123
1124 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1125 vpsub[bwdq] instructions.
1126 * i386-tbl.h: Regenerated.
1127
e184813f
AM		 11282018-03-01 Alan Modra <amodra@gmail.com>
1129
1130 * configure.ac (ALL_LINGUAS): Sort.
1131 * configure: Regenerate.
1132
5b616bef
TP		 11332018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1134
1135 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1136 macro by assignements.
1137
b6f8c7c4
L		 11382018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1139
1140 PR gas/22871
1141 * i386-gen.c (opcode_modifiers): Add Optimize.
1142 * i386-opc.h (Optimize): New enum.
1143 (i386_opcode_modifier): Add optimize.
1144 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1145 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1146 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1147 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1148 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1149 vpxord and vpxorq.
1150 * i386-tbl.h: Regenerated.
1151
e95b887f
AM		 11522018-02-26 Alan Modra <amodra@gmail.com>
1153
1154 * crx-dis.c (getregliststring): Allocate a large enough buffer
1155 to silence false positive gcc8 warning.
1156
0bccfb29
JW		 11572018-02-22 Shea Levy <shea@shealevy.com>
1158
1159 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1160
6b6b6807
L		 11612018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1162
1163 * i386-opc.tbl: Add {rex},
1164 * i386-tbl.h: Regenerated.
1165
75f31665
MR		 11662018-02-20 Maciej W. Rozycki <macro@mips.com>
1167
1168 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1169 (mips16_opcodes): Replace `M' with `m' for "restore".
1170
e207bc53
TP		 11712018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1172
1173 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1174
87993319
MR		 11752018-02-13 Maciej W. Rozycki <macro@mips.com>
1176
1177 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1178 variable to `function_index'.
1179
68d20676
NC		 11802018-02-13 Nick Clifton <nickc@redhat.com>
1181
1182 PR 22823
1183 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1184 about truncation of printing.
1185
d2159fdc
HW		 11862018-02-12 Henry Wong <henry@stuffedcow.net>
1187
1188 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1189
f174ef9f
NC		 11902018-02-05 Nick Clifton <nickc@redhat.com>
1191
1192 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1193
be3a8dca
IT		 11942018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1195
1196 * i386-dis.c (enum): Add pconfig.
1197 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1198 (cpu_flags): Add CpuPCONFIG.
1199 * i386-opc.h (enum): Add CpuPCONFIG.
1200 (i386_cpu_flags): Add cpupconfig.
1201 * i386-opc.tbl: Add PCONFIG instruction.
1202 * i386-init.h: Regenerate.
1203 * i386-tbl.h: Likewise.
1204
3233d7d0
IT		 12052018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1206
1207 * i386-dis.c (enum): Add PREFIX_0F09.
1208 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1209 (cpu_flags): Add CpuWBNOINVD.
1210 * i386-opc.h (enum): Add CpuWBNOINVD.
1211 (i386_cpu_flags): Add cpuwbnoinvd.
1212 * i386-opc.tbl: Add WBNOINVD instruction.
1213 * i386-init.h: Regenerate.
1214 * i386-tbl.h: Likewise.
1215
e925c834
JW		 12162018-01-17 Jim Wilson <jimw@sifive.com>
1217
1218 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1219
d777820b
IT		 12202018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1221
1222 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1223 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1224 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1225 (cpu_flags): Add CpuIBT, CpuSHSTK.
1226 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1227 (i386_cpu_flags): Add cpuibt, cpushstk.
1228 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1229 * i386-init.h: Regenerate.
1230 * i386-tbl.h: Likewise.
1231
f6efed01
NC		 12322018-01-16 Nick Clifton <nickc@redhat.com>
1233
1234 * po/pt_BR.po: Updated Brazilian Portugese translation.
1235 * po/de.po: Updated German translation.
1236
2721d702
JW		 12372018-01-15 Jim Wilson <jimw@sifive.com>
1238
1239 * riscv-opc.c (match_c_nop): New.
1240 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1241
616dcb87
NC		 12422018-01-15 Nick Clifton <nickc@redhat.com>
1243
1244 * po/uk.po: Updated Ukranian translation.
1245
3957a496
NC		 12462018-01-13 Nick Clifton <nickc@redhat.com>
1247
1248 * po/opcodes.pot: Regenerated.
1249
769c7ea5
NC		 12502018-01-13 Nick Clifton <nickc@redhat.com>
1251
1252 * configure: Regenerate.
1253
faf766e3
NC		 12542018-01-13 Nick Clifton <nickc@redhat.com>
1255
1256 2.30 branch created.
1257
888a89da
IT		 12582018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1259
1260 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1261 * i386-tbl.h: Regenerate.
1262
cbda583a
JB		 12632018-01-10 Jan Beulich <jbeulich@suse.com>
1264
1265 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1266 * i386-tbl.h: Re-generate.
1267
c9e92278
JB		 12682018-01-10 Jan Beulich <jbeulich@suse.com>
1269
1270 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1271 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1272 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1273 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1274 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1275 Disp8MemShift of AVX512VL forms.
1276 * i386-tbl.h: Re-generate.
1277
35fd2b2b
JW		 12782018-01-09 Jim Wilson <jimw@sifive.com>
1279
1280 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1281 then the hi_addr value is zero.
1282
91d8b670
JG		 12832018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1284
1285 * arm-dis.c (arm_opcodes): Add csdb.
1286 (thumb32_opcodes): Add csdb.
1287
be2e7d95
JG		 12882018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1289
1290 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1291 * aarch64-asm-2.c: Regenerate.
1292 * aarch64-dis-2.c: Regenerate.
1293 * aarch64-opc-2.c: Regenerate.
1294
704a705d
L		 12952018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1296
1297 PR gas/22681
1298 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1299 Remove AVX512 vmovd with 64-bit operands.
1300 * i386-tbl.h: Regenerated.
1301
35eeb78f
JW		 13022018-01-05 Jim Wilson <jimw@sifive.com>
1303
1304 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1305 jalr.
1306
219d1afa
AM		 13072018-01-03 Alan Modra <amodra@gmail.com>
1308
1309 Update year range in copyright notice of all files.
1310
1508bbf5
JB		 13112018-01-02 Jan Beulich <jbeulich@suse.com>
1312
1313 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1314 and OPERAND_TYPE_REGZMM entries.
1315
1e563868 1316For older changes see ChangeLog-2017
3499769a 1317\f
1e563868 1318Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1319
1320Copying and distribution of this file, with or without modification,
1321are permitted in any medium without royalty provided the copyright
1322notice and this notice are preserved.
1323
1324Local Variables:
1325mode: change-log
1326left-margin: 8
1327fill-column: 74
1328version-control: never
1329End:
A mirror of the official binutils-gdb repository