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8944f3c2
AM		 12008-05-14 Alan Modra <amodra@bigpond.net.au>
2
3 * Makefile.am: Run "make dep-am".
4 * Makefile.in: Regenerate.
5
f1f8f695
L		 62008-05-02 H.J. Lu <hongjiu.lu@intel.com>
7
8 * i386-dis.c (MOVBE_Fixup): New.
9 (Mo): Likewise.
10 (PREFIX_0F3880): Likewise.
11 (PREFIX_0F3881): Likewise.
12 (PREFIX_0F38F0): Updated.
13 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
14 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
15 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
16
17 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
18 CPU_EPT_FLAGS.
19 (cpu_flags): Add CpuMovbe and CpuEPT.
20
21 * i386-opc.h (CpuMovbe): New.
22 (CpuEPT): Likewise.
23 (CpuLM): Updated.
24 (i386_cpu_flags): Add cpumovbe and cpuept.
25
26 * i386-opc.tbl: Add entries for movbe and EPT instructions.
27 * i386-init.h: Regenerated.
28 * i386-tbl.h: Likewise.
29
89aa3097
AN		 302008-04-29 Adam Nemet <anemet@caviumnetworks.com>
31
32 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
33 the two drem and the two dremu macros.
34
39c5c168
AN		 352008-04-28 Adam Nemet <anemet@caviumnetworks.com>
36
37 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
38 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
39 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
40 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
41
f04d18b7
DM		 422008-04-25 David S. Miller <davem@davemloft.net>
43
44 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
45 instead of %sys_tick_cmpr, as suggested in architecture manuals.
46
6194aaab
L		 472008-04-23 Paolo Bonzini <bonzini@gnu.org>
48
49 * aclocal.m4: Regenerate.
50 * configure: Regenerate.
51
1a6b486f
DM		 522008-04-23 David S. Miller <davem@davemloft.net>
53
54 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
55 extended values.
56 (prefetch_table): Add missing values.
57
81f8a913
L		 582008-04-22 H.J. Lu <hongjiu.lu@intel.com>
59
60 * i386-gen.c (opcode_modifiers): Add NoAVX.
61
62 * i386-opc.h (NoAVX): New.
63 (OldGcc): Updated.
64 (i386_opcode_modifier): Add noavx.
65
66 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
67 instructions which don't have AVX equivalent.
68 * i386-tbl.h: Regenerated.
69
dae39acc
L		 702008-04-18 H.J. Lu <hongjiu.lu@intel.com>
71
72 * i386-dis.c (OP_VEX_FMA): New.
73 (OP_EX_VexImmW): Likewise.
74 (VexFMA): Likewise.
75 (Vex128FMA): Likewise.
76 (EXVexImmW): Likewise.
77 (get_vex_imm8): Likewise.
78 (OP_EX_VexReg): Likewise.
79 (vex_i4_done): Renamed to ...
80 (vex_w_done): This.
81 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
82 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
83 FMA instructions.
84 (print_insn): Updated.
85 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
86 (OP_REG_VexI4): Check invalid high registers.
87
ce886ab1
DR		 882008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
89 Michael Meissner <michael.meissner@amd.com>
90
91 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
92 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 93
19a6653c
AM		 942008-04-14 Edmar Wienskoski <edmar@freescale.com>
95
96 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
97 accept Power E500MC instructions.
98 (print_ppc_disassembler_options): Document -Me500mc.
99 * ppc-opc.c (DUIS, DUI, T): New.
100 (XRT, XRTRA): Likewise.
101 (E500MC): Likewise.
102 (powerpc_opcodes): Add new Power E500MC instructions.
103
112b7c50
AK		 1042008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
105
106 * s390-dis.c (init_disasm): Evaluate disassembler_options.
107 (print_s390_disassembler_options): New function.
108 * disassemble.c (disassembler_usage): Invoke
109 print_s390_disassembler_options.
110
7ff42648
AK		 1112008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
112
113 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
114 of local variables used for mnemonic parsing: prefix, suffix and
115 number.
116
45a5551e
AK		 1172008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
118
119 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
120 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
121 (s390_crb_extensions): New extensions table.
122 (insertExpandedMnemonic): Handle '$' tag.
123 * s390-opc.txt: Remove conditional jump variants which can now
124 be expanded automatically.
125 Replace '*' tag with '$' in the compare and branch instructions.
126
06c8514a
L		 1272008-04-07 H.J. Lu <hongjiu.lu@intel.com>
128
129 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
130 (PREFIX_VEX_3AXX): Likewis.
131
b122c285
L		 1322008-04-07 H.J. Lu <hongjiu.lu@intel.com>
133
134 * i386-opc.tbl: Remove 4 extra blank lines.
135
594ab6a3
L		 1362008-04-04 H.J. Lu <hongjiu.lu@intel.com>
137
138 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
139 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
140 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
141 * i386-opc.tbl: Likewise.
142
143 * i386-opc.h (CpuCLMUL): Renamed to ...
144 (CpuPCLMUL): This.
145 (CpuFMA): Updated.
146 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
147
148 * i386-init.h: Regenerated.
149
c0f3af97
L		 1502008-04-03 H.J. Lu <hongjiu.lu@intel.com>
151
152 * i386-dis.c (OP_E_register): New.
153 (OP_E_memory): Likewise.
154 (OP_VEX): Likewise.
155 (OP_EX_Vex): Likewise.
156 (OP_EX_VexW): Likewise.
157 (OP_XMM_Vex): Likewise.
158 (OP_XMM_VexW): Likewise.
159 (OP_REG_VexI4): Likewise.
160 (PCLMUL_Fixup): Likewise.
161 (VEXI4_Fixup): Likewise.
162 (VZERO_Fixup): Likewise.
163 (VCMP_Fixup): Likewise.
164 (VPERMIL2_Fixup): Likewise.
165 (rex_original): Likewise.
166 (rex_ignored): Likewise.
167 (Mxmm): Likewise.
168 (XMM): Likewise.
169 (EXxmm): Likewise.
170 (EXxmmq): Likewise.
171 (EXymmq): Likewise.
172 (Vex): Likewise.
173 (Vex128): Likewise.
174 (Vex256): Likewise.
175 (VexI4): Likewise.
176 (EXdVex): Likewise.
177 (EXqVex): Likewise.
178 (EXVexW): Likewise.
179 (EXdVexW): Likewise.
180 (EXqVexW): Likewise.
181 (XMVex): Likewise.
182 (XMVexW): Likewise.
183 (XMVexI4): Likewise.
184 (PCLMUL): Likewise.
185 (VZERO): Likewise.
186 (VCMP): Likewise.
187 (VPERMIL2): Likewise.
188 (xmm_mode): Likewise.
189 (xmmq_mode): Likewise.
190 (ymmq_mode): Likewise.
191 (vex_mode): Likewise.
192 (vex128_mode): Likewise.
193 (vex256_mode): Likewise.
194 (USE_VEX_C4_TABLE): Likewise.
195 (USE_VEX_C5_TABLE): Likewise.
196 (USE_VEX_LEN_TABLE): Likewise.
197 (VEX_C4_TABLE): Likewise.
198 (VEX_C5_TABLE): Likewise.
199 (VEX_LEN_TABLE): Likewise.
200 (REG_VEX_XX): Likewise.
201 (MOD_VEX_XXX): Likewise.
202 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
203 (PREFIX_0F3A44): Likewise.
204 (PREFIX_0F3ADF): Likewise.
205 (PREFIX_VEX_XXX): Likewise.
206 (VEX_OF): Likewise.
207 (VEX_OF38): Likewise.
208 (VEX_OF3A): Likewise.
209 (VEX_LEN_XXX): Likewise.
210 (vex): Likewise.
211 (need_vex): Likewise.
212 (need_vex_reg): Likewise.
213 (vex_i4_done): Likewise.
214 (vex_table): Likewise.
215 (vex_len_table): Likewise.
216 (OP_REG_VexI4): Likewise.
217 (vex_cmp_op): Likewise.
218 (pclmul_op): Likewise.
219 (vpermil2_op): Likewise.
220 (m_mode): Updated.
221 (es_reg): Likewise.
222 (PREFIX_0F38F0): Likewise.
223 (PREFIX_0F3A60): Likewise.
224 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
225 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
226 and PREFIX_VEX_XXX entries.
227 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
228 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
229 PREFIX_0F3ADF.
230 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
231 Add MOD_VEX_XXX entries.
232 (ckprefix): Initialize rex_original and rex_ignored. Store the
233 REX byte in rex_original.
234 (get_valid_dis386): Handle the implicit prefix in VEX prefix
235 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
236 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
237 calling get_valid_dis386. Use rex_original and rex_ignored when
238 printing out REX.
239 (putop): Handle "XY".
240 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
241 ymmq_mode.
242 (OP_E_extended): Updated to use OP_E_register and
243 OP_E_memory.
244 (OP_XMM): Handle VEX.
245 (OP_EX): Likewise.
246 (XMM_Fixup): Likewise.
247 (CMP_Fixup): Use ARRAY_SIZE.
248
249 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
250 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
251 (operand_type_init): Add OPERAND_TYPE_REGYMM and
252 OPERAND_TYPE_VEX_IMM4.
253 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
254 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
255 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
256 VexImmExt and SSE2AVX.
257 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
258
259 * i386-opc.h (CpuAVX): New.
260 (CpuAES): Likewise.
261 (CpuCLMUL): Likewise.
262 (CpuFMA): Likewise.
263 (Vex): Likewise.
264 (Vex256): Likewise.
265 (VexNDS): Likewise.
266 (VexNDD): Likewise.
267 (VexW0): Likewise.
268 (VexW1): Likewise.
269 (Vex0F): Likewise.
270 (Vex0F38): Likewise.
271 (Vex0F3A): Likewise.
272 (Vex3Sources): Likewise.
273 (VexImmExt): Likewise.
274 (SSE2AVX): Likewise.
275 (RegYMM): Likewise.
276 (Ymmword): Likewise.
277 (Vex_Imm4): Likewise.
278 (Implicit1stXmm0): Likewise.
279 (CpuXsave): Updated.
280 (CpuLM): Likewise.
281 (ByteOkIntel): Likewise.
282 (OldGcc): Likewise.
283 (Control): Likewise.
284 (Unspecified): Likewise.
285 (OTMax): Likewise.
286 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
287 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
288 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
289 vex3sources, veximmext and sse2avx.
290 (i386_operand_type): Add regymm, ymmword and vex_imm4.
291
292 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
293
294 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
295
296 * i386-init.h: Regenerated.
297 * i386-tbl.h: Likewise.
298
b21c9cb4
BS		 2992008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
300
301 From Robin Getz <robin.getz@analog.com>
302 * bfin-dis.c (bu32): Typedef.
303 (enum const_forms_t): Add c_uimm32 and c_huimm32.
304 (constant_formats[]): Add uimm32 and huimm16.
305 (fmtconst_val): New.
306 (uimm32): Define.
307 (huimm32): Define.
308 (imm16_val): Define.
309 (luimm16_val): Define.
310 (struct saved_state): Define.
311 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
312 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
313 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
314 (get_allreg): New.
315 (decode_LDIMMhalf_0): Print out the whole register value.
316
ee171c8f
BS		 317 From Jie Zhang <jie.zhang@analog.com>
318 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
319 multiply and multiply-accumulate to data register instruction.
320
086134ec
BS		 321 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
322 c_imm32, c_huimm32e): Define.
323 (constant_formats): Add flags for printing decimal, leading spaces, and
324 exact symbols.
325 (comment, parallel): Add global flags in all disassembly.
326 (fmtconst): Take advantage of new flags, and print default in hex.
327 (fmtconst_val): Likewise.
328 (decode_macfunc): Be consistant with spaces, tabs, comments,
329 capitalization in disassembly, fix minor coding style issues.
330 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
331 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
332 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
333 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
334 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
335 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
336 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
337 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
338 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
339 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
340 _print_insn_bfin, print_insn_bfin): Likewise.
341
58c85be7
RW		 3422008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
343
344 * aclocal.m4: Regenerate.
345 * configure: Likewise.
346 * Makefile.in: Likewise.
347
50e7d84b
AM		 3482008-03-13 Alan Modra <amodra@bigpond.net.au>
349
350 * Makefile.am: Run "make dep-am".
351 * Makefile.in: Regenerate.
352 * configure: Regenerate.
353
de866fcc
AM		 3542008-03-07 Alan Modra <amodra@bigpond.net.au>
355
356 * ppc-opc.c (powerpc_opcodes): Order and format.
357
28dbc079
L		 3582008-03-01 H.J. Lu <hongjiu.lu@intel.com>
359
360 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
361 * i386-tbl.h: Regenerated.
362
849830bd
L		 3632008-02-23 H.J. Lu <hongjiu.lu@intel.com>
364
365 * i386-opc.tbl: Disallow 16-bit near indirect branches for
366 x86-64.
367 * i386-tbl.h: Regenerated.
368
743ddb6b
JB		 3692008-02-21 Jan Beulich <jbeulich@novell.com>
370
371 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
372 and Fword for far indirect jmp. Allow Reg16 and Word for near
373 indirect jmp on x86-64. Disallow Fword for lcall.
374 * i386-tbl.h: Re-generate.
375
796d5313
NC		 3762008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
377
378 * cr16-opc.c (cr16_num_optab): Defined
379
65da13b5
L		 3802008-02-16 H.J. Lu <hongjiu.lu@intel.com>
381
382 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
383 * i386-init.h: Regenerated.
384
0e336180
NC		 3852008-02-14 Nick Clifton <nickc@redhat.com>
386
387 PR binutils/5524
388 * configure.in (SHARED_LIBADD): Select the correct host specific
389 file extension for shared libraries.
390 * configure: Regenerate.
391
b7240065
JB		 3922008-02-13 Jan Beulich <jbeulich@novell.com>
393
394 * i386-opc.h (RegFlat): New.
395 * i386-reg.tbl (flat): Add.
396 * i386-tbl.h: Re-generate.
397
34b772a6
JB		 3982008-02-13 Jan Beulich <jbeulich@novell.com>
399
400 * i386-dis.c (a_mode): New.
401 (cond_jump_mode): Adjust.
402 (Ma): Change to a_mode.
403 (intel_operand_size): Handle a_mode.
404 * i386-opc.tbl: Allow Dword and Qword for bound.
405 * i386-tbl.h: Re-generate.
406
a60de03c
JB		 4072008-02-13 Jan Beulich <jbeulich@novell.com>
408
409 * i386-gen.c (process_i386_registers): Process new fields.
410 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
411 unsigned char. Add dw2_regnum and Dw2Inval.
412 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
413 register names.
414 * i386-tbl.h: Re-generate.
415
f03fe4c1
L		 4162008-02-11 H.J. Lu <hongjiu.lu@intel.com>
417
4b6bc8eb 418 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 419 * i386-init.h: Updated.
420
475a2301
L		 4212008-02-11 H.J. Lu <hongjiu.lu@intel.com>
422
423 * i386-gen.c (cpu_flags): Add CpuXsave.
424
425 * i386-opc.h (CpuXsave): New.
4b6bc8eb 426 (CpuLM): Updated.
475a2301
L		 427 (i386_cpu_flags): Add cpuxsave.
428
429 * i386-dis.c (MOD_0FAE_REG_4): New.
430 (RM_0F01_REG_2): Likewise.
431 (MOD_0FAE_REG_5): Updated.
432 (RM_0F01_REG_3): Likewise.
433 (reg_table): Use MOD_0FAE_REG_4.
434 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
435 for xrstor.
436 (rm_table): Add RM_0F01_REG_2.
437
438 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
439 * i386-init.h: Regenerated.
440 * i386-tbl.h: Likewise.
441
595785c6 4422008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 443
595785c6
JB		 444 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
445 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
446 * i386-tbl.h: Re-generate.
447
bb8541b9
L		 4482008-02-04 H.J. Lu <hongjiu.lu@intel.com>
449
450 PR 5715
451 * configure: Regenerated.
452
57b592a3
AN		 4532008-02-04 Adam Nemet <anemet@caviumnetworks.com>
454
455 * mips-dis.c: Update copyright.
456 (mips_arch_choices): Add Octeon.
457 * mips-opc.c: Update copyright.
458 (IOCT): New macro.
459 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
460
930bb4cf
AM		 4612008-01-29 Alan Modra <amodra@bigpond.net.au>
462
463 * ppc-opc.c: Support optional L form mtmsr.
464
82c18208
L		 4652008-01-24 H.J. Lu <hongjiu.lu@intel.com>
466
467 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
468
599121aa
L		 4692008-01-23 H.J. Lu <hongjiu.lu@intel.com>
470
471 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
472 * i386-init.h: Regenerated.
473
80098f51
TG		 4742008-01-23 Tristan Gingold <gingold@adacore.com>
475
476 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
477 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
478
115c7c25
L		 4792008-01-22 H.J. Lu <hongjiu.lu@intel.com>
480
481 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
482 (cpu_flags): Likewise.
483
484 * i386-opc.h (CpuMMX2): Removed.
485 (CpuSSE): Updated.
486
487 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
488 * i386-init.h: Regenerated.
489 * i386-tbl.h: Likewise.
490
6305a203
L		 4912008-01-22 H.J. Lu <hongjiu.lu@intel.com>
492
493 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
494 CPU_SMX_FLAGS.
495 * i386-init.h: Regenerated.
496
fd07a1c8
L		 4972008-01-15 H.J. Lu <hongjiu.lu@intel.com>
498
499 * i386-opc.tbl: Use Qword on movddup.
500 * i386-tbl.h: Regenerated.
501
321fd21e
L		 5022008-01-15 H.J. Lu <hongjiu.lu@intel.com>
503
504 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
505 * i386-tbl.h: Regenerated.
506
4ee52178
L		 5072008-01-15 H.J. Lu <hongjiu.lu@intel.com>
508
509 * i386-dis.c (Mx): New.
510 (PREFIX_0FC3): Likewise.
511 (PREFIX_0FC7_REG_6): Updated.
512 (dis386_twobyte): Use PREFIX_0FC3.
513 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
514 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
515 movntss.
516
5c07affc
L		 5172008-01-14 H.J. Lu <hongjiu.lu@intel.com>
518
519 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
520 (operand_types): Add Mem.
521
522 * i386-opc.h (IntelSyntax): New.
523 * i386-opc.h (Mem): New.
524 (Byte): Updated.
525 (Opcode_Modifier_Max): Updated.
526 (i386_opcode_modifier): Add intelsyntax.
527 (i386_operand_type): Add mem.
528
529 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
530 instructions.
531
532 * i386-reg.tbl: Add size for accumulator.
533
534 * i386-init.h: Regenerated.
535 * i386-tbl.h: Likewise.
536
0d6a2f58
L		 5372008-01-13 H.J. Lu <hongjiu.lu@intel.com>
538
539 * i386-opc.h (Byte): Fix a typo.
540
7d5e4556
L		 5412008-01-12 H.J. Lu <hongjiu.lu@intel.com>
542
543 PR gas/5534
544 * i386-gen.c (operand_type_init): Add Dword to
545 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
546 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
547 Qword and Xmmword.
548 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
549 Xmmword, Unspecified and Anysize.
550 (set_bitfield): Make Mmword an alias of Qword. Make Oword
551 an alias of Xmmword.
552
553 * i386-opc.h (CheckSize): Removed.
554 (Byte): Updated.
555 (Word): Likewise.
556 (Dword): Likewise.
557 (Qword): Likewise.
558 (Xmmword): Likewise.
559 (FWait): Updated.
560 (OTMax): Likewise.
561 (i386_opcode_modifier): Remove checksize, byte, word, dword,
562 qword and xmmword.
563 (Fword): New.
564 (TBYTE): Likewise.
565 (Unspecified): Likewise.
566 (Anysize): Likewise.
567 (i386_operand_type): Add byte, word, dword, fword, qword,
568 tbyte xmmword, unspecified and anysize.
569
570 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
571 Tbyte, Xmmword, Unspecified and Anysize.
572
573 * i386-reg.tbl: Add size for accumulator.
574
575 * i386-init.h: Regenerated.
576 * i386-tbl.h: Likewise.
577
b5b1fc4f
L		 5782008-01-10 H.J. Lu <hongjiu.lu@intel.com>
579
580 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
581 (REG_0F18): Updated.
582 (reg_table): Updated.
583 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
584 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
585
50e8458f
L		 5862008-01-08 H.J. Lu <hongjiu.lu@intel.com>
587
588 * i386-gen.c (set_bitfield): Use fail () on error.
589
3d4d5afa
L		 5902008-01-08 H.J. Lu <hongjiu.lu@intel.com>
591
592 * i386-gen.c (lineno): New.
593 (filename): Likewise.
594 (set_bitfield): Report filename and line numer on error.
595 (process_i386_opcodes): Set filename and update lineno.
596 (process_i386_registers): Likewise.
597
e1d4d893
L		 5982008-01-05 H.J. Lu <hongjiu.lu@intel.com>
599
600 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
601 ATTSyntax.
602
603 * i386-opc.h (IntelMnemonic): Renamed to ..
604 (ATTSyntax): This
605 (Opcode_Modifier_Max): Updated.
606 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
607 and intelsyntax.
608
8944f3c2 609 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 610 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
611 * i386-tbl.h: Regenerated.
612
6f143e4d
L		 6132008-01-04 H.J. Lu <hongjiu.lu@intel.com>
614
615 * i386-gen.c: Update copyright to 2008.
616 * i386-opc.h: Likewise.
617 * i386-opc.tbl: Likewise.
618
619 * i386-init.h: Regenerated.
620 * i386-tbl.h: Likewise.
621
c6add537
L		 6222008-01-04 H.J. Lu <hongjiu.lu@intel.com>
623
624 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
625 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
626 * i386-tbl.h: Regenerated.
627
3629bb00
L		 6282008-01-03 H.J. Lu <hongjiu.lu@intel.com>
629
630 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
631 CpuSSE4_2_Or_ABM.
632 (cpu_flags): Likewise.
633
634 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
635 (CpuSSE4_2_Or_ABM): Likewise.
636 (CpuLM): Updated.
637 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
638
639 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
640 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
641 and CpuPadLock, respectively.
642 * i386-init.h: Regenerated.
643 * i386-tbl.h: Likewise.
644
24995bd6
L		 6452008-01-03 H.J. Lu <hongjiu.lu@intel.com>
646
647 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
648
649 * i386-opc.h (No_xSuf): Removed.
650 (CheckSize): Updated.
651
652 * i386-tbl.h: Regenerated.
653
e0329a22
L		 6542008-01-02 H.J. Lu <hongjiu.lu@intel.com>
655
656 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
657 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
658 CPU_SSE5_FLAGS.
659 (cpu_flags): Add CpuSSE4_2_Or_ABM.
660
661 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
662 (CpuLM): Updated.
663 (i386_cpu_flags): Add cpusse4_2_or_abm.
664
665 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
666 CpuABM|CpuSSE4_2 on popcnt.
667 * i386-init.h: Regenerated.
668 * i386-tbl.h: Likewise.
669
f2a9c676
L		 6702008-01-02 H.J. Lu <hongjiu.lu@intel.com>
671
672 * i386-opc.h: Update comments.
673
d978b5be
L		 6742008-01-02 H.J. Lu <hongjiu.lu@intel.com>
675
676 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
677 * i386-opc.h: Likewise.
678 * i386-opc.tbl: Likewise.
679
582d5edd
L		 6802008-01-02 H.J. Lu <hongjiu.lu@intel.com>
681
682 PR gas/5534
683 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
684 Byte, Word, Dword, QWord and Xmmword.
685
686 * i386-opc.h (No_xSuf): New.
687 (CheckSize): Likewise.
688 (Byte): Likewise.
689 (Word): Likewise.
690 (Dword): Likewise.
691 (QWord): Likewise.
692 (Xmmword): Likewise.
693 (FWait): Updated.
694 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
695 Dword, QWord and Xmmword.
696
697 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
698 used.
699 * i386-tbl.h: Regenerated.
700
3fe15143
MK		 7012008-01-02 Mark Kettenis <kettenis@gnu.org>
702
703 * m88k-dis.c (instructions): Fix fcvt.* instructions.
704 From Miod Vallat.
705
6c7ac64e 706For older changes see ChangeLog-2007
252b5132
RH		 707\f
708Local Variables:
2f6d2f85
NC		 709mode: change-log
710left-margin: 8
711fill-column: 74
252b5132
RH		 712version-control: never
713End:
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