]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - opcodes/ChangeLog
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Re: Enhance powerpc ld -r --relax
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
4a1b91ea
L		 12018-07-25 H.J. Lu <hongjiu.lu@intel.com>
2 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
3
4 * i386-gen.c (adjust_broadcast_modifier): New function.
5 (process_i386_opcode_modifier): Add an argument for operands.
6 Adjust the Broadcast value based on operands.
7 (output_i386_opcode): Pass operand_types to
8 process_i386_opcode_modifier.
9 (process_i386_opcodes): Pass NULL as operands to
10 process_i386_opcode_modifier.
11 * i386-opc.h (BYTE_BROADCAST): New.
12 (WORD_BROADCAST): Likewise.
13 (DWORD_BROADCAST): Likewise.
14 (QWORD_BROADCAST): Likewise.
15 (i386_opcode_modifier): Expand broadcast to 3 bits.
16 * i386-tbl.h: Regenerated.
17
67ce483b
AM		 182018-07-24 Alan Modra <amodra@gmail.com>
19
20 PR 23430
21 * or1k-desc.h: Regenerate.
22
4174bfff
JB		 232018-07-24 Jan Beulich <jbeulich@suse.com>
24
25 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
26 vcvtusi2ss, and vcvtusi2sd.
27 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
28 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
29 * i386-tbl.h: Re-generate.
30
04e65276
CZ		 312018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
32
33 * arc-opc.c (extract_w6): Fix extending the sign.
34
47e6f81c
CZ		 352018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
36
37 * arc-tbl.h (vewt): Allow it for ARC EM family.
38
bb71536f
AM		 392018-07-23 Alan Modra <amodra@gmail.com>
40
41 PR 23419
42 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
43 opcode variants for mtspr/mfspr encodings.
44
8095d2f7
CX		 452018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
46 Maciej W. Rozycki <macro@mips.com>
47
48 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
49 loongson3a descriptors.
50 (parse_mips_ase_option): Handle -M loongson-mmi option.
51 (print_mips_disassembler_options): Document -M loongson-mmi.
52 * mips-opc.c (LMMI): New macro.
53 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
54 instructions.
55
5f32791e
JB		 562018-07-19 Jan Beulich <jbeulich@suse.com>
57
58 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
59 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
60 IgnoreSize and [XYZ]MMword where applicable.
61 * i386-tbl.h: Re-generate.
62
625cbd7a
JB		 632018-07-19 Jan Beulich <jbeulich@suse.com>
64
65 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
66 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
67 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
68 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
69 * i386-tbl.h: Re-generate.
70
86b15c32
JB		 712018-07-19 Jan Beulich <jbeulich@suse.com>
72
73 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
74 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
75 VPCLMULQDQ templates into their respective AVX512VL counterparts
76 where possible, using Disp8ShiftVL and CheckRegSize instead of
77 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
78 * i386-tbl.h: Re-generate.
79
cf769ed5
JB		 802018-07-19 Jan Beulich <jbeulich@suse.com>
81
82 * i386-opc.tbl: Fold AVX512DQ templates into their respective
83 AVX512VL counterparts where possible, using Disp8ShiftVL and
84 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
85 IgnoreSize) as appropriate.
86 * i386-tbl.h: Re-generate.
87
8282b7ad
JB		 882018-07-19 Jan Beulich <jbeulich@suse.com>
89
90 * i386-opc.tbl: Fold AVX512BW templates into their respective
91 AVX512VL counterparts where possible, using Disp8ShiftVL and
92 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
93 IgnoreSize) as appropriate.
94 * i386-tbl.h: Re-generate.
95
755908cc
JB		 962018-07-19 Jan Beulich <jbeulich@suse.com>
97
98 * i386-opc.tbl: Fold AVX512CD templates into their respective
99 AVX512VL counterparts where possible, using Disp8ShiftVL and
100 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
101 IgnoreSize) as appropriate.
102 * i386-tbl.h: Re-generate.
103
7091c612
JB		 1042018-07-19 Jan Beulich <jbeulich@suse.com>
105
106 * i386-opc.h (DISP8_SHIFT_VL): New.
107 * i386-opc.tbl (Disp8ShiftVL): Define.
108 (various): Fold AVX512VL templates into their respective
109 AVX512F counterparts where possible, using Disp8ShiftVL and
110 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
111 IgnoreSize) as appropriate.
112 * i386-tbl.h: Re-generate.
113
c30be56e
JB		 1142018-07-19 Jan Beulich <jbeulich@suse.com>
115
116 * Makefile.am: Change dependencies and rule for
117 $(srcdir)/i386-init.h.
118 * Makefile.in: Re-generate.
119 * i386-gen.c (process_i386_opcodes): New local variable
120 "marker". Drop opening of input file. Recognize marker and line
121 number directives.
122 * i386-opc.tbl (OPCODE_I386_H): Define.
123 (i386-opc.h): Include it.
124 (None): Undefine.
125
11a322db
L		 1262018-07-18 H.J. Lu <hongjiu.lu@intel.com>
127
128 PR gas/23418
129 * i386-opc.h (Byte): Update comments.
130 (Word): Likewise.
131 (Dword): Likewise.
132 (Fword): Likewise.
133 (Qword): Likewise.
134 (Tbyte): Likewise.
135 (Xmmword): Likewise.
136 (Ymmword): Likewise.
137 (Zmmword): Likewise.
138 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
139 vcvttps2uqq.
140 * i386-tbl.h: Regenerated.
141
cde3679e
NC		 1422018-07-12 Sudakshina Das <sudi.das@arm.com>
143
144 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
145 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
146 * aarch64-asm-2.c: Regenerate.
147 * aarch64-dis-2.c: Regenerate.
148 * aarch64-opc-2.c: Regenerate.
149
45a28947
TC		 1502018-07-12 Tamar Christina <tamar.christina@arm.com>
151
152 PR binutils/23192
153 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
154 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
155 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
156 sqdmulh, sqrdmulh): Use Em16.
157
c597cc3d
SD		 1582018-07-11 Sudakshina Das <sudi.das@arm.com>
159
160 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
161 csdb together with them.
162 (thumb32_opcodes): Likewise.
163
a79eaed6
JB		 1642018-07-11 Jan Beulich <jbeulich@suse.com>
165
166 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
167 requiring 32-bit registers as operands 2 and 3. Improve
168 comments.
169 (mwait, mwaitx): Fold templates. Improve comments.
170 OPERAND_TYPE_INOUTPORTREG.
171 * i386-tbl.h: Re-generate.
172
2fb5be8d
JB		 1732018-07-11 Jan Beulich <jbeulich@suse.com>
174
175 * i386-gen.c (operand_type_init): Remove
176 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
177 OPERAND_TYPE_INOUTPORTREG.
178 * i386-init.h: Re-generate.
179
7f5cad30
JB		 1802018-07-11 Jan Beulich <jbeulich@suse.com>
181
182 * i386-opc.tbl (wrssd, wrussd): Add Dword.
183 (wrssq, wrussq): Add Qword.
184 * i386-tbl.h: Re-generate.
185
f0a85b07
JB		 1862018-07-11 Jan Beulich <jbeulich@suse.com>
187
188 * i386-opc.h: Rename OTMax to OTNum.
189 (OTNumOfUints): Adjust calculation.
190 (OTUnused): Directly alias to OTNum.
191
9dcb0ba4
MR		 1922018-07-09 Maciej W. Rozycki <macro@mips.com>
193
194 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
195 `reg_xys'.
196 (lea_reg_xys): Likewise.
197 (print_insn_loop_primitive): Rename `reg' local variable to
198 `reg_dxy'.
199
f311ba7e
TC		 2002018-07-06 Tamar Christina <tamar.christina@arm.com>
201
202 PR binutils/23242
203 * aarch64-tbl.h (ldarh): Fix disassembly mask.
204
cba05feb
TC		 2052018-07-06 Tamar Christina <tamar.christina@arm.com>
206
207 PR binutils/23369
208 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
209 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
210
471b9d15
MR		 2112018-07-02 Maciej W. Rozycki <macro@mips.com>
212
213 PR tdep/8282
214 * mips-dis.c (mips_option_arg_t): New enumeration.
215 (mips_options): New variable.
216 (disassembler_options_mips): New function.
217 (print_mips_disassembler_options): Reimplement in terms of
218 `disassembler_options_mips'.
219 * arm-dis.c (disassembler_options_arm): Adapt to using the
220 `disasm_options_and_args_t' structure.
221 * ppc-dis.c (disassembler_options_powerpc): Likewise.
222 * s390-dis.c (disassembler_options_s390): Likewise.
223
c0c468d5
TP		 2242018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
225
226 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
227 expected result.
228 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
229 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
230 * testsuite/ld-arm/tls-longplt.d: Likewise.
231
369c9167
TC		 2322018-06-29 Tamar Christina <tamar.christina@arm.com>
233
234 PR binutils/23192
235 * aarch64-asm-2.c: Regenerate.
236 * aarch64-dis-2.c: Likewise.
237 * aarch64-opc-2.c: Likewise.
238 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
239 * aarch64-opc.c (operand_general_constraint_met_p,
240 aarch64_print_operand): Likewise.
241 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
242 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
243 fmlal2, fmlsl2.
244 (AARCH64_OPERANDS): Add Em2.
245
30aa1306
NC		 2462018-06-26 Nick Clifton <nickc@redhat.com>
247
248 * po/uk.po: Updated Ukranian translation.
249 * po/de.po: Updated German translation.
250 * po/pt_BR.po: Updated Brazilian Portuguese translation.
251
eca4b721
NC		 2522018-06-26 Nick Clifton <nickc@redhat.com>
253
254 * nfp-dis.c: Fix spelling mistake.
255
71300e2c
NC		 2562018-06-24 Nick Clifton <nickc@redhat.com>
257
258 * configure: Regenerate.
259 * po/opcodes.pot: Regenerate.
260
719d8288
NC		 2612018-06-24 Nick Clifton <nickc@redhat.com>
262
263 2.31 branch created.
264
514cd3a0
TC		 2652018-06-19 Tamar Christina <tamar.christina@arm.com>
266
267 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
268 * aarch64-asm-2.c: Regenerate.
269 * aarch64-dis-2.c: Likewise.
270
385e4d0f
MR		 2712018-06-21 Maciej W. Rozycki <macro@mips.com>
272
273 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
274 `-M ginv' option description.
275
160d1b3d
SH		 2762018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
277
278 PR gas/23305
279 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
280 la and lla.
281
d0ac1c44
SM		 2822018-06-19 Simon Marchi <simon.marchi@ericsson.com>
283
284 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
285 * configure.ac: Remove AC_PREREQ.
286 * Makefile.in: Re-generate.
287 * aclocal.m4: Re-generate.
288 * configure: Re-generate.
289
6f20c942
FS		 2902018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
291
292 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
293 mips64r6 descriptors.
294 (parse_mips_ase_option): Handle -Mginv option.
295 (print_mips_disassembler_options): Document -Mginv.
296 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
297 (GINV): New macro.
298 (mips_opcodes): Define ginvi and ginvt.
299
730c3174
SE		 3002018-06-13 Scott Egerton <scott.egerton@imgtec.com>
301 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
302
303 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
304 * mips-opc.c (CRC, CRC64): New macros.
305 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
306 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
307 crc32cd for CRC64.
308
cb366992
EB		 3092018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
310
311 PR 20319
312 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
313 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
314
ce72cd46
AM		 3152018-06-06 Alan Modra <amodra@gmail.com>
316
317 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
318 setjmp. Move init for some other vars later too.
319
4b8e28c7
MF		 3202018-06-04 Max Filippov <jcmvbkbc@gmail.com>
321
322 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
323 (dis_private): Add new fields for property section tracking.
324 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
325 (xtensa_instruction_fits): New functions.
326 (fetch_data): Bump minimal fetch size to 4.
327 (print_insn_xtensa): Make struct dis_private static.
328 Load and prepare property table on section change.
329 Don't disassemble literals. Don't disassemble instructions that
330 cross property table boundaries.
331
55e99962
L		 3322018-06-01 H.J. Lu <hongjiu.lu@intel.com>
333
334 * configure: Regenerated.
335
733bd0ab
JB		 3362018-06-01 Jan Beulich <jbeulich@suse.com>
337
338 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
339 * i386-tbl.h: Re-generate.
340
dfd27d41
JB		 3412018-06-01 Jan Beulich <jbeulich@suse.com>
342
343 * i386-opc.tbl (sldt, str): Add NoRex64.
344 * i386-tbl.h: Re-generate.
345
64795710
JB		 3462018-06-01 Jan Beulich <jbeulich@suse.com>
347
348 * i386-opc.tbl (invpcid): Add Oword.
349 * i386-tbl.h: Re-generate.
350
030157d8
AM		 3512018-06-01 Alan Modra <amodra@gmail.com>
352
353 * sysdep.h (_bfd_error_handler): Don't declare.
354 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
355 * rl78-decode.opc: Likewise.
356 * msp430-decode.c: Regenerate.
357 * rl78-decode.c: Regenerate.
358
a9660a6f
AP		 3592018-05-30 Amit Pawar <Amit.Pawar@amd.com>
360
361 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
362 * i386-init.h : Regenerated.
363
277eb7f6
AM		 3642018-05-25 Alan Modra <amodra@gmail.com>
365
366 * Makefile.in: Regenerate.
367 * po/POTFILES.in: Regenerate.
368
98553ad3
PB		 3692018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
370
371 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
372 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
373 (insert_bab, extract_bab, insert_btab, extract_btab,
374 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
375 (BAT, BBA VBA RBS XB6S): Delete macros.
376 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
377 (BB, BD, RBX, XC6): Update for new macros.
378 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
379 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
380 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
381 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
382
7b4ae824
JD		 3832018-05-18 John Darrington <john@darrington.wattle.id.au>
384
385 * Makefile.am: Add support for s12z architecture.
386 * configure.ac: Likewise.
387 * disassemble.c: Likewise.
388 * disassemble.h: Likewise.
389 * Makefile.in: Regenerate.
390 * configure: Regenerate.
391 * s12z-dis.c: New file.
392 * s12z.h: New file.
393
29e0f0a1
AM		 3942018-05-18 Alan Modra <amodra@gmail.com>
395
396 * nfp-dis.c: Don't #include libbfd.h.
397 (init_nfp3200_priv): Use bfd_get_section_contents.
398 (nit_nfp6000_mecsr_sec): Likewise.
399
809276d2
NC		 4002018-05-17 Nick Clifton <nickc@redhat.com>
401
402 * po/zh_CN.po: Updated simplified Chinese translation.
403
ff329288
TC		 4042018-05-16 Tamar Christina <tamar.christina@arm.com>
405
406 PR binutils/23109
407 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
408 * aarch64-dis-2.c: Regenerate.
409
f9830ec1
TC		 4102018-05-15 Tamar Christina <tamar.christina@arm.com>
411
412 PR binutils/21446
413 * aarch64-asm.c (opintl.h): Include.
414 (aarch64_ins_sysreg): Enforce read/write constraints.
415 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
416 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
417 (F_REG_READ, F_REG_WRITE): New.
418 * aarch64-opc.c (aarch64_print_operand): Generate notes for
419 AARCH64_OPND_SYSREG.
420 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
421 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
422 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
423 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
424 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
425 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
426 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
427 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
428 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
429 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
430 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
431 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
432 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
433 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
434 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
435 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
436 msr (F_SYS_WRITE), mrs (F_SYS_READ).
437
7d02540a
TC		 4382018-05-15 Tamar Christina <tamar.christina@arm.com>
439
440 PR binutils/21446
441 * aarch64-dis.c (no_notes: New.
442 (parse_aarch64_dis_option): Support notes.
443 (aarch64_decode_insn, print_operands): Likewise.
444 (print_aarch64_disassembler_options): Document notes.
445 * aarch64-opc.c (aarch64_print_operand): Support notes.
446
561a72d4
TC		 4472018-05-15 Tamar Christina <tamar.christina@arm.com>
448
449 PR binutils/21446
450 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
451 and take error struct.
452 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
453 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
454 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
455 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
456 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
457 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
458 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
459 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
460 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
461 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
462 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
463 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
464 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
465 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
466 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
467 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
468 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
469 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
470 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
471 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
472 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
473 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
474 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
475 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
476 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
477 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
478 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
479 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
480 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
481 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
482 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
483 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
484 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
485 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
486 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
487 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
488 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
489 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
490 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
491 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
492 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
493 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
494 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
495 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
496 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
497 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
498 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
499 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
500 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
501 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
502 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
503 (determine_disassembling_preference, aarch64_decode_insn,
504 print_insn_aarch64_word, print_insn_data): Take errors struct.
505 (print_insn_aarch64): Use errors.
506 * aarch64-asm-2.c: Regenerate.
507 * aarch64-dis-2.c: Regenerate.
508 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
509 boolean in aarch64_insert_operan.
510 (print_operand_extractor): Likewise.
511 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
512
1678bd35
FT		 5132018-05-15 Francois H. Theron <francois.theron@netronome.com>
514
515 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
516
06cfb1c8
L		 5172018-05-09 H.J. Lu <hongjiu.lu@intel.com>
518
519 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
520
84f9f8c3
AM		 5212018-05-09 Sebastian Rasmussen <sebras@gmail.com>
522
523 * cr16-opc.c (cr16_instruction): Comment typo fix.
524 * hppa-dis.c (print_insn_hppa): Likewise.
525
e6f372ba
JW		 5262018-05-08 Jim Wilson <jimw@sifive.com>
527
528 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
529 (match_c_slli64, match_srxi_as_c_srxi): New.
530 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
531 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
532 <c.slli, c.srli, c.srai>: Use match_s_slli.
533 <c.slli64, c.srli64, c.srai64>: New.
534
f413a913
AM		 5352018-05-08 Alan Modra <amodra@gmail.com>
536
537 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
538 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
539 partition opcode space for index lookup.
540
a87a6478
PB		 5412018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
542
543 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
544 <insn_length>: ...with this. Update usage.
545 Remove duplicate call to *info->memory_error_func.
546
c0a30a9f
L		 5472018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
548 H.J. Lu <hongjiu.lu@intel.com>
549
550 * i386-dis.c (Gva): New.
551 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
552 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
553 (prefix_table): New instructions (see prefix above).
554 (mod_table): New instructions (see prefix above).
555 (OP_G): Handle va_mode.
556 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
557 CPU_MOVDIR64B_FLAGS.
558 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
559 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
560 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
561 * i386-opc.tbl: Add movidir{i,64b}.
562 * i386-init.h: Regenerated.
563 * i386-tbl.h: Likewise.
564
75c0a438
L		 5652018-05-07 H.J. Lu <hongjiu.lu@intel.com>
566
567 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
568 AddrPrefixOpReg.
569 * i386-opc.h (AddrPrefixOp0): Renamed to ...
570 (AddrPrefixOpReg): This.
571 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
572 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
573
2ceb7719
PB		 5742018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
575
576 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
577 (vle_num_opcodes): Likewise.
578 (spe2_num_opcodes): Likewise.
579 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
580 initialization loop.
581 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
582 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
583 only once.
584
b3ac5c6c
TC		 5852018-05-01 Tamar Christina <tamar.christina@arm.com>
586
587 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
588
fe944acf
FT		 5892018-04-30 Francois H. Theron <francois.theron@netronome.com>
590
591 Makefile.am: Added nfp-dis.c.
592 configure.ac: Added bfd_nfp_arch.
593 disassemble.h: Added print_insn_nfp prototype.
594 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
595 nfp-dis.c: New, for NFP support.
596 po/POTFILES.in: Added nfp-dis.c to the list.
597 Makefile.in: Regenerate.
598 configure: Regenerate.
599
e2195274
JB		 6002018-04-26 Jan Beulich <jbeulich@suse.com>
601
602 * i386-opc.tbl: Fold various non-memory operand AVX512VL
603 templates into their base ones.
604 * i386-tlb.h: Re-generate.
605
59ef5df4
JB		 6062018-04-26 Jan Beulich <jbeulich@suse.com>
607
608 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
609 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
610 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
611 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
612 * i386-init.h: Re-generate.
613
6e041cf4
JB		 6142018-04-26 Jan Beulich <jbeulich@suse.com>
615
616 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
617 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
618 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
619 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
620 comment.
621 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
622 and CpuRegMask.
623 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
624 CpuRegMask: Delete.
625 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
626 cpuregzmm, and cpuregmask.
627 * i386-init.h: Re-generate.
628 * i386-tbl.h: Re-generate.
629
0e0eea78
JB		 6302018-04-26 Jan Beulich <jbeulich@suse.com>
631
632 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
633 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
634 * i386-init.h: Re-generate.
635
2f1bada2
JB		 6362018-04-26 Jan Beulich <jbeulich@suse.com>
637
638 * i386-gen.c (VexImmExt): Delete.
639 * i386-opc.h (VexImmExt, veximmext): Delete.
640 * i386-opc.tbl: Drop all VexImmExt uses.
641 * i386-tlb.h: Re-generate.
642
bacd1457
JB		 6432018-04-25 Jan Beulich <jbeulich@suse.com>
644
645 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
646 register-only forms.
647 * i386-tlb.h: Re-generate.
648
10bba94b
TC		 6492018-04-25 Tamar Christina <tamar.christina@arm.com>
650
651 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
652
c48935d7
IT		 6532018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
654
655 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
656 PREFIX_0F1C.
657 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
658 (cpu_flags): Add CpuCLDEMOTE.
659 * i386-init.h: Regenerate.
660 * i386-opc.h (enum): Add CpuCLDEMOTE,
661 (i386_cpu_flags): Add cpucldemote.
662 * i386-opc.tbl: Add cldemote.
663 * i386-tbl.h: Regenerate.
664
211dc24b
AM		 6652018-04-16 Alan Modra <amodra@gmail.com>
666
667 * Makefile.am: Remove sh5 and sh64 support.
668 * configure.ac: Likewise.
669 * disassemble.c: Likewise.
670 * disassemble.h: Likewise.
671 * sh-dis.c: Likewise.
672 * sh64-dis.c: Delete.
673 * sh64-opc.c: Delete.
674 * sh64-opc.h: Delete.
675 * Makefile.in: Regenerate.
676 * configure: Regenerate.
677 * po/POTFILES.in: Regenerate.
678
a9a4b302
AM		 6792018-04-16 Alan Modra <amodra@gmail.com>
680
681 * Makefile.am: Remove w65 support.
682 * configure.ac: Likewise.
683 * disassemble.c: Likewise.
684 * disassemble.h: Likewise.
685 * w65-dis.c: Delete.
686 * w65-opc.h: Delete.
687 * Makefile.in: Regenerate.
688 * configure: Regenerate.
689 * po/POTFILES.in: Regenerate.
690
04cb01fd
AM		 6912018-04-16 Alan Modra <amodra@gmail.com>
692
693 * configure.ac: Remove we32k support.
694 * configure: Regenerate.
695
c2bf1eec
AM		 6962018-04-16 Alan Modra <amodra@gmail.com>
697
698 * Makefile.am: Remove m88k support.
699 * configure.ac: Likewise.
700 * disassemble.c: Likewise.
701 * disassemble.h: Likewise.
702 * m88k-dis.c: Delete.
703 * Makefile.in: Regenerate.
704 * configure: Regenerate.
705 * po/POTFILES.in: Regenerate.
706
6793974d
AM		 7072018-04-16 Alan Modra <amodra@gmail.com>
708
709 * Makefile.am: Remove i370 support.
710 * configure.ac: Likewise.
711 * disassemble.c: Likewise.
712 * disassemble.h: Likewise.
713 * i370-dis.c: Delete.
714 * i370-opc.c: Delete.
715 * Makefile.in: Regenerate.
716 * configure: Regenerate.
717 * po/POTFILES.in: Regenerate.
718
e82aa794
AM		 7192018-04-16 Alan Modra <amodra@gmail.com>
720
721 * Makefile.am: Remove h8500 support.
722 * configure.ac: Likewise.
723 * disassemble.c: Likewise.
724 * disassemble.h: Likewise.
725 * h8500-dis.c: Delete.
726 * h8500-opc.h: Delete.
727 * Makefile.in: Regenerate.
728 * configure: Regenerate.
729 * po/POTFILES.in: Regenerate.
730
fceadf09
AM		 7312018-04-16 Alan Modra <amodra@gmail.com>
732
733 * configure.ac: Remove tahoe support.
734 * configure: Regenerate.
735
ae1d3843
L		 7362018-04-15 H.J. Lu <hongjiu.lu@intel.com>
737
738 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
739 umwait.
740 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
741 64-bit mode.
742 * i386-tbl.h: Regenerated.
743
de89d0a3
IT		 7442018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
745
746 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
747 PREFIX_MOD_1_0FAE_REG_6.
748 (va_mode): New.
749 (OP_E_register): Use va_mode.
750 * i386-dis-evex.h (prefix_table):
751 New instructions (see prefixes above).
752 * i386-gen.c (cpu_flag_init): Add WAITPKG.
753 (cpu_flags): Likewise.
754 * i386-opc.h (enum): Likewise.
755 (i386_cpu_flags): Likewise.
756 * i386-opc.tbl: Add umonitor, umwait, tpause.
757 * i386-init.h: Regenerate.
758 * i386-tbl.h: Likewise.
759
a8eb42a8
AM		 7602018-04-11 Alan Modra <amodra@gmail.com>
761
762 * opcodes/i860-dis.c: Delete.
763 * opcodes/i960-dis.c: Delete.
764 * Makefile.am: Remove i860 and i960 support.
765 * configure.ac: Likewise.
766 * disassemble.c: Likewise.
767 * disassemble.h: Likewise.
768 * Makefile.in: Regenerate.
769 * configure: Regenerate.
770 * po/POTFILES.in: Regenerate.
771
caf0678c
L		 7722018-04-04 H.J. Lu <hongjiu.lu@intel.com>
773
774 PR binutils/23025
775 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
776 to 0.
777 (print_insn): Clear vex instead of vex.evex.
778
4fb0d2b9
NC		 7792018-04-04 Nick Clifton <nickc@redhat.com>
780
781 * po/es.po: Updated Spanish translation.
782
c39e5b26
JB		 7832018-03-28 Jan Beulich <jbeulich@suse.com>
784
785 * i386-gen.c (opcode_modifiers): Delete VecESize.
786 * i386-opc.h (VecESize): Delete.
787 (struct i386_opcode_modifier): Delete vecesize.
788 * i386-opc.tbl: Drop VecESize.
789 * i386-tlb.h: Re-generate.
790
8e6e0792
JB		 7912018-03-28 Jan Beulich <jbeulich@suse.com>
792
793 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
794 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
795 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
796 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
797 * i386-tlb.h: Re-generate.
798
9f123b91
JB		 7992018-03-28 Jan Beulich <jbeulich@suse.com>
800
801 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
802 Fold AVX512 forms
803 * i386-tlb.h: Re-generate.
804
9646c87b
JB		 8052018-03-28 Jan Beulich <jbeulich@suse.com>
806
807 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
808 (vex_len_table): Drop Y for vcvt*2si.
809 (putop): Replace plain 'Y' handling by abort().
810
c8d59609
NC		 8112018-03-28 Nick Clifton <nickc@redhat.com>
812
813 PR 22988
814 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
815 instructions with only a base address register.
816 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
817 handle AARHC64_OPND_SVE_ADDR_R.
818 (aarch64_print_operand): Likewise.
819 * aarch64-asm-2.c: Regenerate.
820 * aarch64_dis-2.c: Regenerate.
821 * aarch64-opc-2.c: Regenerate.
822
b8c169f3
JB		 8232018-03-22 Jan Beulich <jbeulich@suse.com>
824
825 * i386-opc.tbl: Drop VecESize from register only insn forms and
826 memory forms not allowing broadcast.
827 * i386-tlb.h: Re-generate.
828
96bc132a
JB		 8292018-03-22 Jan Beulich <jbeulich@suse.com>
830
831 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
832 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
833 sha256*): Drop Disp<N>.
834
9f79e886
JB		 8352018-03-22 Jan Beulich <jbeulich@suse.com>
836
837 * i386-dis.c (EbndS, bnd_swap_mode): New.
838 (prefix_table): Use EbndS.
839 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
840 * i386-opc.tbl (bndmov): Move misplaced Load.
841 * i386-tlb.h: Re-generate.
842
d6793fa1
JB		 8432018-03-22 Jan Beulich <jbeulich@suse.com>
844
845 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
846 templates allowing memory operands and folded ones for register
847 only flavors.
848 * i386-tlb.h: Re-generate.
849
f7768225
JB		 8502018-03-22 Jan Beulich <jbeulich@suse.com>
851
852 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
853 256-bit templates. Drop redundant leftover Disp<N>.
854 * i386-tlb.h: Re-generate.
855
0e35537d
JW		 8562018-03-14 Kito Cheng <kito.cheng@gmail.com>
857
858 * riscv-opc.c (riscv_insn_types): New.
859
b4a3689a
NC		 8602018-03-13 Nick Clifton <nickc@redhat.com>
861
862 * po/pt_BR.po: Updated Brazilian Portuguese translation.
863
d3d50934
L		 8642018-03-08 H.J. Lu <hongjiu.lu@intel.com>
865
866 * i386-opc.tbl: Add Optimize to clr.
867 * i386-tbl.h: Regenerated.
868
bd5dea88
L		 8692018-03-08 H.J. Lu <hongjiu.lu@intel.com>
870
871 * i386-gen.c (opcode_modifiers): Remove OldGcc.
872 * i386-opc.h (OldGcc): Removed.
873 (i386_opcode_modifier): Remove oldgcc.
874 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
875 instructions for old (<= 2.8.1) versions of gcc.
876 * i386-tbl.h: Regenerated.
877
e771e7c9
JB		 8782018-03-08 Jan Beulich <jbeulich@suse.com>
879
880 * i386-opc.h (EVEXDYN): New.
881 * i386-opc.tbl: Fold various AVX512VL templates.
882 * i386-tlb.h: Re-generate.
883
ed438a93
JB		 8842018-03-08 Jan Beulich <jbeulich@suse.com>
885
886 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
887 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
888 vpexpandd, vpexpandq): Fold AFX512VF templates.
889 * i386-tlb.h: Re-generate.
890
454172a9
JB		 8912018-03-08 Jan Beulich <jbeulich@suse.com>
892
893 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
894 Fold 128- and 256-bit VEX-encoded templates.
895 * i386-tlb.h: Re-generate.
896
36824150
JB		 8972018-03-08 Jan Beulich <jbeulich@suse.com>
898
899 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
900 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
901 vpexpandd, vpexpandq): Fold AVX512F templates.
902 * i386-tlb.h: Re-generate.
903
e7f5c0a9
JB		 9042018-03-08 Jan Beulich <jbeulich@suse.com>
905
906 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
907 64-bit templates. Drop Disp<N>.
908 * i386-tlb.h: Re-generate.
909
25a4277f
JB		 9102018-03-08 Jan Beulich <jbeulich@suse.com>
911
912 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
913 and 256-bit templates.
914 * i386-tlb.h: Re-generate.
915
d2224064
JB		 9162018-03-08 Jan Beulich <jbeulich@suse.com>
917
918 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
919 * i386-tlb.h: Re-generate.
920
1b193f0b
JB		 9212018-03-08 Jan Beulich <jbeulich@suse.com>
922
923 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
924 Drop NoAVX.
925 * i386-tlb.h: Re-generate.
926
f2f6a710
JB		 9272018-03-08 Jan Beulich <jbeulich@suse.com>
928
929 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
930 * i386-tlb.h: Re-generate.
931
38e314eb
JB		 9322018-03-08 Jan Beulich <jbeulich@suse.com>
933
934 * i386-gen.c (opcode_modifiers): Delete FloatD.
935 * i386-opc.h (FloatD): Delete.
936 (struct i386_opcode_modifier): Delete floatd.
937 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
938 FloatD by D.
939 * i386-tlb.h: Re-generate.
940
d53e6b98
JB		 9412018-03-08 Jan Beulich <jbeulich@suse.com>
942
943 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
944
2907c2f5
JB		 9452018-03-08 Jan Beulich <jbeulich@suse.com>
946
947 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
948 * i386-tlb.h: Re-generate.
949
73053c1f
JB		 9502018-03-08 Jan Beulich <jbeulich@suse.com>
951
952 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
953 forms.
954 * i386-tlb.h: Re-generate.
955
52fe4420
AM		 9562018-03-07 Alan Modra <amodra@gmail.com>
957
958 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
959 bfd_arch_rs6000.
960 * disassemble.h (print_insn_rs6000): Delete.
961 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
962 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
963 (print_insn_rs6000): Delete.
964
a6743a54
AM		 9652018-03-03 Alan Modra <amodra@gmail.com>
966
967 * sysdep.h (opcodes_error_handler): Define.
968 (_bfd_error_handler): Declare.
969 * Makefile.am: Remove stray #.
970 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
971 EDIT" comment.
972 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
973 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
974 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
975 opcodes_error_handler to print errors. Standardize error messages.
976 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
977 and include opintl.h.
978 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
979 * i386-gen.c: Standardize error messages.
980 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
981 * Makefile.in: Regenerate.
982 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
983 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
984 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
985 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
986 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
987 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
988 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
989 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
990 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
991 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
992 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
993 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
994 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
995
8305403a
L		 9962018-03-01 H.J. Lu <hongjiu.lu@intel.com>
997
998 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
999 vpsub[bwdq] instructions.
1000 * i386-tbl.h: Regenerated.
1001
e184813f
AM		 10022018-03-01 Alan Modra <amodra@gmail.com>
1003
1004 * configure.ac (ALL_LINGUAS): Sort.
1005 * configure: Regenerate.
1006
5b616bef
TP		 10072018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1008
1009 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1010 macro by assignements.
1011
b6f8c7c4
L		 10122018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1013
1014 PR gas/22871
1015 * i386-gen.c (opcode_modifiers): Add Optimize.
1016 * i386-opc.h (Optimize): New enum.
1017 (i386_opcode_modifier): Add optimize.
1018 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1019 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1020 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1021 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1022 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1023 vpxord and vpxorq.
1024 * i386-tbl.h: Regenerated.
1025
e95b887f
AM		 10262018-02-26 Alan Modra <amodra@gmail.com>
1027
1028 * crx-dis.c (getregliststring): Allocate a large enough buffer
1029 to silence false positive gcc8 warning.
1030
0bccfb29
JW		 10312018-02-22 Shea Levy <shea@shealevy.com>
1032
1033 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1034
6b6b6807
L		 10352018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1036
1037 * i386-opc.tbl: Add {rex},
1038 * i386-tbl.h: Regenerated.
1039
75f31665
MR		 10402018-02-20 Maciej W. Rozycki <macro@mips.com>
1041
1042 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1043 (mips16_opcodes): Replace `M' with `m' for "restore".
1044
e207bc53
TP		 10452018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1046
1047 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1048
87993319
MR		 10492018-02-13 Maciej W. Rozycki <macro@mips.com>
1050
1051 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1052 variable to `function_index'.
1053
68d20676
NC		 10542018-02-13 Nick Clifton <nickc@redhat.com>
1055
1056 PR 22823
1057 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1058 about truncation of printing.
1059
d2159fdc
HW		 10602018-02-12 Henry Wong <henry@stuffedcow.net>
1061
1062 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1063
f174ef9f
NC		 10642018-02-05 Nick Clifton <nickc@redhat.com>
1065
1066 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1067
be3a8dca
IT		 10682018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1069
1070 * i386-dis.c (enum): Add pconfig.
1071 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1072 (cpu_flags): Add CpuPCONFIG.
1073 * i386-opc.h (enum): Add CpuPCONFIG.
1074 (i386_cpu_flags): Add cpupconfig.
1075 * i386-opc.tbl: Add PCONFIG instruction.
1076 * i386-init.h: Regenerate.
1077 * i386-tbl.h: Likewise.
1078
3233d7d0
IT		 10792018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1080
1081 * i386-dis.c (enum): Add PREFIX_0F09.
1082 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1083 (cpu_flags): Add CpuWBNOINVD.
1084 * i386-opc.h (enum): Add CpuWBNOINVD.
1085 (i386_cpu_flags): Add cpuwbnoinvd.
1086 * i386-opc.tbl: Add WBNOINVD instruction.
1087 * i386-init.h: Regenerate.
1088 * i386-tbl.h: Likewise.
1089
e925c834
JW		 10902018-01-17 Jim Wilson <jimw@sifive.com>
1091
1092 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1093
d777820b
IT		 10942018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1095
1096 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1097 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1098 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1099 (cpu_flags): Add CpuIBT, CpuSHSTK.
1100 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1101 (i386_cpu_flags): Add cpuibt, cpushstk.
1102 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1103 * i386-init.h: Regenerate.
1104 * i386-tbl.h: Likewise.
1105
f6efed01
NC		 11062018-01-16 Nick Clifton <nickc@redhat.com>
1107
1108 * po/pt_BR.po: Updated Brazilian Portugese translation.
1109 * po/de.po: Updated German translation.
1110
2721d702
JW		 11112018-01-15 Jim Wilson <jimw@sifive.com>
1112
1113 * riscv-opc.c (match_c_nop): New.
1114 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1115
616dcb87
NC		 11162018-01-15 Nick Clifton <nickc@redhat.com>
1117
1118 * po/uk.po: Updated Ukranian translation.
1119
3957a496
NC		 11202018-01-13 Nick Clifton <nickc@redhat.com>
1121
1122 * po/opcodes.pot: Regenerated.
1123
769c7ea5
NC		 11242018-01-13 Nick Clifton <nickc@redhat.com>
1125
1126 * configure: Regenerate.
1127
faf766e3
NC		 11282018-01-13 Nick Clifton <nickc@redhat.com>
1129
1130 2.30 branch created.
1131
888a89da
IT		 11322018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1133
1134 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1135 * i386-tbl.h: Regenerate.
1136
cbda583a
JB		 11372018-01-10 Jan Beulich <jbeulich@suse.com>
1138
1139 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1140 * i386-tbl.h: Re-generate.
1141
c9e92278
JB		 11422018-01-10 Jan Beulich <jbeulich@suse.com>
1143
1144 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1145 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1146 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1147 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1148 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1149 Disp8MemShift of AVX512VL forms.
1150 * i386-tbl.h: Re-generate.
1151
35fd2b2b
JW		 11522018-01-09 Jim Wilson <jimw@sifive.com>
1153
1154 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1155 then the hi_addr value is zero.
1156
91d8b670
JG		 11572018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1158
1159 * arm-dis.c (arm_opcodes): Add csdb.
1160 (thumb32_opcodes): Add csdb.
1161
be2e7d95
JG		 11622018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1163
1164 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1165 * aarch64-asm-2.c: Regenerate.
1166 * aarch64-dis-2.c: Regenerate.
1167 * aarch64-opc-2.c: Regenerate.
1168
704a705d
L		 11692018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1170
1171 PR gas/22681
1172 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1173 Remove AVX512 vmovd with 64-bit operands.
1174 * i386-tbl.h: Regenerated.
1175
35eeb78f
JW		 11762018-01-05 Jim Wilson <jimw@sifive.com>
1177
1178 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1179 jalr.
1180
219d1afa
AM		 11812018-01-03 Alan Modra <amodra@gmail.com>
1182
1183 Update year range in copyright notice of all files.
1184
1508bbf5
JB		 11852018-01-02 Jan Beulich <jbeulich@suse.com>
1186
1187 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1188 and OPERAND_TYPE_REGZMM entries.
1189
1e563868 1190For older changes see ChangeLog-2017
3499769a 1191\f
1e563868 1192Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1193
1194Copying and distribution of this file, with or without modification,
1195are permitted in any medium without royalty provided the copyright
1196notice and this notice are preserved.
1197
1198Local Variables:
1199mode: change-log
1200left-margin: 8
1201fill-column: 74
1202version-control: never
1203End:
A mirror of the official binutils-gdb repository