projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| b933fa4b JB |
1 | 2021-03-23 Jan Beulich <jbeulich@suse.com> |
| 2 | ||
| 3 | * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend | |
| 4 | comment. | |
| 5 | * i386-tbl.h: Re-generate. | |
| 6 | ||
| dac10fb0 JB |
7 | 2021-03-23 Jan Beulich <jbeulich@suse.com> |
| 8 | ||
| 9 | * i386-opc.h (struct insn_template): Move cpu_flags field past | |
| 10 | opcode_modifier one. | |
| 11 | * i386-tbl.h: Re-generate. | |
| 12 | ||
| 441f6aca JB |
13 | 2021-03-23 Jan Beulich <jbeulich@suse.com> |
| 14 | ||
| 15 | * i386-gen.c (opcode_modifiers): New OpcodeSpace element. | |
| 16 | * i386-opc.h (OpcodeSpace): New enumerator. | |
| 17 | (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ... | |
| 18 | (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08, | |
| 19 | SPACE_XOP09, SPACE_XOP0A): ... respectively. | |
| 20 | (struct i386_opcode_modifier): New field opcodespace. Shrink | |
| 21 | opcodeprefix field. | |
| 22 | i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08, | |
| 23 | SpaceXOP09, SpaceXOP0A): Define. Use them to replace | |
| 24 | OpcodePrefix uses. | |
| 25 | * i386-tbl.h: Re-generate. | |
| 26 | ||
| 08dedd66 ML |
27 | 2021-03-22 Martin Liska <mliska@suse.cz> |
| 28 | ||
| 29 | * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith. | |
| 30 | * arc-dis.c (parse_option): Likewise. | |
| 31 | * arm-dis.c (parse_arm_disassembler_options): Likewise. | |
| 32 | * cris-dis.c (print_with_operands): Likewise. | |
| 33 | * h8300-dis.c (bfd_h8_disassemble): Likewise. | |
| 34 | * i386-dis.c (print_insn): Likewise. | |
| 35 | * ia64-gen.c (fetch_insn_class): Likewise. | |
| 36 | (parse_resource_users): Likewise. | |
| 37 | (in_iclass): Likewise. | |
| 38 | (lookup_specifier): Likewise. | |
| 39 | (insert_opcode_dependencies): Likewise. | |
| 40 | * mips-dis.c (parse_mips_ase_option): Likewise. | |
| 41 | (parse_mips_dis_option): Likewise. | |
| 42 | * s390-dis.c (disassemble_init_s390): Likewise. | |
| 43 | * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise. | |
| 44 | ||
| 80d49d6a KLC |
45 | 2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com> |
| 46 | ||
| 47 | * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions. | |
| 48 | ||
| 7fce7ea9 PW |
49 | 2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> |
| 50 | ||
| 51 | * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1, | |
| 52 | icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers. | |
| 53 | ||
| 78c84bf9 AM |
54 | 2021-03-12 Alan Modra <amodra@gmail.com> |
| 55 | ||
| 56 | * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo. | |
| 57 | ||
| fd1fd061 JB |
58 | 2021-03-11 Jan Beulich <jbeulich@suse.com> |
| 59 | ||
| 60 | * i386-dis.c (OP_XMM): Re-order checks. | |
| 61 | ||
| ac7a2311 JB |
62 | 2021-03-11 Jan Beulich <jbeulich@suse.com> |
| 63 | ||
| 64 | * i386-dis.c (putop): Drop need_vex check when also checking | |
| 65 | vex.evex. | |
| 66 | (intel_operand_size, OP_E_memory): Drop vex.evex check when also | |
| 67 | checking vex.b. | |
| 68 | ||
| da944c8a JB |
69 | 2021-03-11 Jan Beulich <jbeulich@suse.com> |
| 70 | ||
| 71 | * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast | |
| 72 | checks. Move case label past broadcast check. | |
| 73 | ||
| b763d508 JB |
74 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
| 75 | ||
| 76 | * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX, | |
| 77 | vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode, | |
| 78 | REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1, | |
| 79 | EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3, | |
| 80 | EVEX_W_0F38C7_M_0_L_2): Delete. | |
| 81 | (REG_EVEX_0F38C7_M_0_L_2): New. | |
| 82 | (intel_operand_size): Handle VEX and EVEX the same for | |
| 83 | vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop | |
| 84 | vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases. | |
| 85 | (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and | |
| 86 | vex_vsib_q_w_d_mode uses. | |
| 87 | * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893, | |
| 88 | 0F38A1, and 0F38A3 entries. | |
| 89 | * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7 | |
| 90 | entry. | |
| 91 | * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries. | |
| 92 | * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and | |
| 93 | 0F38A3 entries. | |
| 94 | ||
| 32e31ad7 JB |
95 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
| 96 | ||
| 97 | * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0, | |
| 98 | REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0, | |
| 99 | MOD_VEX_0FXOP_09_12): Rename to ... | |
| 100 | (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0, | |
| 101 | REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these. | |
| 102 | (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT, | |
| 103 | RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26, | |
| 104 | X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C, | |
| 105 | X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move. | |
| 106 | (reg_table): Adjust comments. | |
| 107 | (x86_64_table): Move X86_64_0F24, X86_64_0F26, | |
| 108 | X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C, | |
| 109 | X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries. | |
| 110 | (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries. | |
| 111 | (vex_len_table): Adjust opcode 0A_12 entry. | |
| 112 | (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, | |
| 113 | MOD_C5_32BIT, and MOD_XOP_09_12 entries. | |
| 114 | (rm_table): Move hreset entry. | |
| 115 | ||
| 85ba7507 JB |
116 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
| 117 | ||
| 118 | * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1, | |
| 119 | EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6, | |
| 120 | EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15, | |
| 121 | EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20, | |
| 122 | EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete. | |
| 123 | (EVEX_LEN_0F3816, EVEX_W_0FD6): New. | |
| 124 | (get_valid_dis386): Also handle 512-bit vector length when | |
| 125 | vectoring into vex_len_table[]. | |
| 126 | * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5, | |
| 127 | 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 | |
| 128 | entries. | |
| 129 | * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6, | |
| 130 | 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries. | |
| 131 | * i386-dis-evex-prefix.h: Adjust 0F7E entry. | |
| 132 | * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21 | |
| 133 | entries. | |
| 134 | ||
| 066f82b9 JB |
135 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
| 136 | ||
| 137 | * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1): | |
| 138 | Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively. | |
| 139 | EVEX_W_0F3A00, EVEX_W_0F3A01): Delete. | |
| 140 | * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01 | |
| 141 | entries. | |
| 142 | * i386-dis-evex-len.h (evex_len_table): Likewise. | |
| 143 | * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries. | |
| 144 | ||
| fc681dd6 JB |
145 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
| 146 | ||
| 147 | * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7, | |
| 148 | MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, | |
| 149 | MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, | |
| 150 | MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1, | |
| 151 | MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, | |
| 152 | MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, | |
| 153 | MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, | |
| 154 | MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6 | |
| 155 | EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1, | |
| 156 | EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0, | |
| 157 | EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0, | |
| 158 | EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0, | |
| 159 | EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0, | |
| 160 | EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0, | |
| 161 | EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0, | |
| 162 | EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1, | |
| 163 | EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1, | |
| 164 | EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1, | |
| 165 | EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1, | |
| 166 | EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0, | |
| 167 | EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1, | |
| 168 | EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0, | |
| 169 | EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1, | |
| 170 | EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0, | |
| 171 | EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1, | |
| 172 | EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819, | |
| 173 | EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B, | |
| 174 | EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0, | |
| 175 | EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0, | |
| 176 | EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B, | |
| 177 | EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A, | |
| 178 | EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete. | |
| 179 | REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0, | |
| 180 | REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A, | |
| 181 | MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B, | |
| 182 | MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819, | |
| 183 | EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0, | |
| 184 | EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0, | |
| 185 | EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0, | |
| 186 | EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A, | |
| 187 | EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38, | |
| 188 | EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B, | |
| 189 | EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n, | |
| 190 | EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n, | |
| 191 | EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2, | |
| 192 | EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2, | |
| 193 | EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n, | |
| 194 | EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2, | |
| 195 | EVEX_W_0F3A43_L_n): New. | |
| 196 | * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A, | |
| 197 | 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, | |
| 198 | 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries. | |
| 199 | * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[] | |
| 200 | for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7, | |
| 201 | 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A, | |
| 202 | 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6. | |
| 203 | * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A, | |
| 204 | 0F385B, 0F38C6, and 0F38C7 entries. | |
| 205 | * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes | |
| 206 | 0F38C6 and 0F38C7. | |
| 207 | * i386-dis-evex-w.h: No longer link to evex_len_table[] for | |
| 208 | opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, | |
| 209 | 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to | |
| 210 | evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B. | |
| 211 | ||
| 13954a31 JB |
212 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
| 213 | ||
| 214 | * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1, | |
| 215 | MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1, | |
| 216 | MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1, | |
| 217 | MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1, | |
| 218 | MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1, | |
| 219 | MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1, | |
| 220 | MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1, | |
| 221 | MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1, | |
| 222 | MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1, | |
| 223 | MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1, | |
| 224 | MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1, | |
| 225 | MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1, | |
| 226 | MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
| 227 | MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
| 228 | MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
| 229 | MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
| 230 | MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0, | |
| 231 | MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0, | |
| 232 | MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, | |
| 233 | MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0, | |
| 234 | MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0, | |
| 235 | MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, | |
| 236 | MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0, | |
| 237 | MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0, | |
| 238 | MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0, | |
| 239 | PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, | |
| 240 | PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, | |
| 241 | PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, | |
| 242 | PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, | |
| 243 | PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0, | |
| 244 | VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2, | |
| 245 | VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0, | |
| 246 | VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2, | |
| 247 | VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0, | |
| 248 | VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2, | |
| 249 | VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0, | |
| 250 | VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2, | |
| 251 | VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2, | |
| 252 | VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2, | |
| 253 | VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1, | |
| 254 | VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1, | |
| 255 | VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0, | |
| 256 | VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1, | |
| 257 | VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1, | |
| 258 | VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1, | |
| 259 | VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1, | |
| 260 | VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, | |
| 261 | VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, | |
| 262 | VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0, | |
| 263 | VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0, | |
| 264 | VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0, | |
| 265 | VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0, | |
| 266 | VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, | |
| 267 | VEX_W_0F99_P_2_LEN_0): Delete. | |
| 268 | MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0, | |
| 269 | MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1, | |
| 270 | MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0, | |
| 271 | MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0, | |
| 272 | MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0, | |
| 273 | PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0, | |
| 274 | PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0, | |
| 275 | PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0, | |
| 276 | PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0, | |
| 277 | PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0, | |
| 278 | PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0, | |
| 279 | PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0, | |
| 280 | PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0, | |
| 281 | PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0, | |
| 282 | PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0, | |
| 283 | PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0, | |
| 284 | PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0, | |
| 285 | PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0, | |
| 286 | PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42, | |
| 287 | VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47, | |
| 288 | VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91, | |
| 289 | VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99, | |
| 290 | VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1, | |
| 291 | VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1, | |
| 292 | VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0, | |
| 293 | VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1, | |
| 294 | VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New. | |
| 295 | (prefix_table): No longer link to vex_len_table[] for opcodes | |
| 296 | 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, | |
| 297 | 0F92, 0F93, 0F98, and 0F99. | |
| 298 | (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42, | |
| 299 | 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, | |
| 300 | 0F98, and 0F99. | |
| 301 | (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42, | |
| 302 | 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, | |
| 303 | 0F98, and 0F99. | |
| 304 | (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42, | |
| 305 | 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, | |
| 306 | 0F98, and 0F99. | |
| 307 | (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42, | |
| 308 | 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, | |
| 309 | 0F98, and 0F99. | |
| 310 | ||
| 14d10c6c JB |
311 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
| 312 | ||
| 313 | * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73): | |
| 314 | Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and | |
| 315 | REG_VEX_0F73_M_0 respectively. | |
| 316 | (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6, | |
| 317 | MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6, | |
| 318 | MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6, | |
| 319 | MOD_VEX_0F73_REG_7): Delete. | |
| 320 | (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New. | |
| 321 | (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7, | |
| 322 | PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0, | |
| 323 | PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0, | |
| 324 | PREFIX_VEX_0F3AF0_L_0 respectively. | |
| 325 | (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3, | |
| 326 | VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3, | |
| 327 | VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1, | |
| 328 | VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete. | |
| 329 | (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6, | |
| 330 | VEX_LEN_0F38F7): New. | |
| 331 | (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0. | |
| 332 | (reg_table): No longer link to mod_table[] for VEX opcodes 0F71, | |
| 333 | 0F72, and 0F73. No longer link to vex_len_table[] for opcode | |
| 334 | 0F38F3. | |
| 335 | (prefix_table): No longer link to vex_len_table[] for opcodes | |
| 336 | 0F38F5, 0F38F6, 0F38F7, and 0F3AF0. | |
| 337 | (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and | |
| 338 | 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5, | |
| 339 | 0F38F6, 0F38F7, and 0F3AF0. | |
| 340 | (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to | |
| 341 | prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0. | |
| 342 | (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and | |
| 343 | 0F73. | |
| 344 | ||
| 00ec1875 JB |
345 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
| 346 | ||
| 347 | * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to | |
| 348 | REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively. | |
| 349 | (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2, | |
| 350 | MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3, | |
| 351 | MOD_0F73_REG_6, MOD_0F73_REG_7): Delete. | |
| 352 | (MOD_0F71, MOD_0F72, MOD_0F73): New. | |
| 353 | (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and | |
| 354 | 73. | |
| 355 | (reg_table): No longer link to mod_table[] for opcodes 0F71, | |
| 356 | 0F72, and 0F73. | |
| 357 | (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and | |
| 358 | 0F73. | |
| 359 | ||
| 31941983 JB |
360 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
| 361 | ||
| 362 | * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5, | |
| 363 | MOD_0F18_REG_6, MOD_0F18_REG_7): Delete. | |
| 364 | (reg_table): Don't link to mod_table[] where not needed. Add | |
| 365 | PREFIX_IGNORED to nop entries. | |
| 366 | (prefix_table): Replace PREFIX_OPCODE in nop entries. | |
| 367 | (mod_table): Add nop entries next to prefetch ones. Drop | |
| 368 | MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and | |
| 369 | MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries. | |
| 370 | (rm_table): Add PREFIX_IGNORED to nop entries. Drop | |
| 371 | PREFIX_OPCODE from endbr* entries. | |
| 372 | (get_valid_dis386): Also consider entry's name when zapping | |
| 373 | vindex. | |
| 374 | (print_insn): Handle PREFIX_IGNORED. | |
| 375 | ||
| 742732c7 JB |
376 | 2021-03-09 Jan Beulich <jbeulich@suse.com> |
| 377 | ||
| 378 | * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk, | |
| 379 | IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk | |
| 380 | element. | |
| 381 | * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone, | |
| 382 | HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete. | |
| 383 | (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack, | |
| 384 | PrefixLock, PrefixHLELock, PrefixHLEAny): Define. | |
| 385 | (struct i386_opcode_modifier): Delete notrackprefixok, | |
| 386 | islockable, hleprefixok, and repprefixok fields. Add prefixok | |
| 387 | field. | |
| 388 | * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny, | |
| 389 | HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define. | |
| 390 | (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg, | |
| 391 | not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b): | |
| 392 | Replace HLEPrefixOk. | |
| 393 | * opcodes/i386-tbl.h: Re-generate. | |
| 394 | ||
| e93a3b27 JB |
395 | 2021-03-09 Jan Beulich <jbeulich@suse.com> |
| 396 | ||
| 397 | * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit. | |
| 398 | * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from | |
| 399 | 64-bit form. | |
| 400 | * opcodes/i386-tbl.h: Re-generate. | |
| 401 | ||
| 75363b6d JB |
402 | 2021-03-03 Jan Beulich <jbeulich@suse.com> |
| 403 | ||
| 404 | * i386-gen.c (output_i386_opcode): Don't get operand count. Look | |
| 405 | for {} instead of {0}. Don't look for '0'. | |
| 406 | * i386-opc.tbl: Drop operand count field. Drop redundant operand | |
| 407 | size specifiers. | |
| 408 | ||
| 5a9f5403 NC |
409 | 2021-02-19 Nelson Chu <nelson.chu@sifive.com> |
| 410 | ||
| 411 | PR 27158 | |
| 412 | * riscv-dis.c (print_insn_args): Updated encoding macros. | |
| 413 | * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. | |
| 414 | (match_c_addi16sp): Updated encoding macros. | |
| 415 | (match_c_lui): Likewise. | |
| 416 | (match_c_lui_with_hint): Likewise. | |
| 417 | (match_c_addi4spn): Likewise. | |
| 418 | (match_c_slli): Likewise. | |
| 419 | (match_slli_as_c_slli): Likewise. | |
| 420 | (match_c_slli64): Likewise. | |
| 421 | (match_srxi_as_c_srxi): Likewise. | |
| 422 | (riscv_insn_types): Added .insn css/cl/cs. | |
| 423 | ||
| 3d73d29e NC |
424 | 2021-02-18 Nelson Chu <nelson.chu@sifive.com> |
| 425 | ||
| 426 | * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h. | |
| 427 | (default_priv_spec): Updated type to riscv_spec_class. | |
| 428 | (parse_riscv_dis_option): Updated. | |
| 429 | * riscv-opc.c: Moved stuff and make the file tidy. | |
| 430 | ||
| b9b204b3 AM |
431 | 2021-02-17 Alan Modra <amodra@gmail.com> |
| 432 | ||
| 433 | * wasm32-dis.c: Include limits.h. | |
| 434 | (CHAR_BIT): Provide backup define. | |
| 435 | (wasm_read_leb128): Use CHAR_BIT to size "result" in bits. | |
| 436 | Correct signed overflow checking. | |
| 437 | ||
| 394ae71f JB |
438 | 2021-02-16 Jan Beulich <jbeulich@suse.com> |
| 439 | ||
| 440 | * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant. | |
| 441 | * i386-tbl.h: Re-generate. | |
| 442 | ||
| b818b220 JB |
443 | 2021-02-16 Jan Beulich <jbeulich@suse.com> |
| 444 | ||
| 445 | * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor | |
| 446 | Oword. | |
| 447 | * i386-opc.tbl (CpuFP, Mmword, Oword): Define. | |
| 448 | ||
| ba2b480f AK |
449 | 2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com> |
| 450 | ||
| 451 | * s390-mkopc.c (main): Accept arch14 as cpu string. | |
| 452 | * s390-opc.txt: Add new arch14 instructions. | |
| 453 | ||
| 95148614 NA |
454 | 2021-02-04 Nick Alcock <nick.alcock@oracle.com> |
| 455 | ||
| 456 | * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in | |
| 457 | favour of LIBINTL. | |
| 458 | * configure: Regenerated. | |
| 459 | ||
| bfd428bc MF |
460 | 2021-02-08 Mike Frysinger <vapier@gentoo.org> |
| 461 | ||
| 462 | * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs. | |
| 463 | * tic54x-opc.c (regs): Rename to ... | |
| 464 | (tic54x_regs): ... this. | |
| 465 | (mmregs): Rename to ... | |
| 466 | (tic54x_mmregs): ... this. | |
| 467 | (condition_codes): Rename to ... | |
| 468 | (tic54x_condition_codes): ... this. | |
| 469 | (cc2_codes): Rename to ... | |
| 470 | (tic54x_cc2_codes): ... this. | |
| 471 | (cc3_codes): Rename to ... | |
| 472 | (tic54x_cc3_codes): ... this. | |
| 473 | (status_bits): Rename to ... | |
| 474 | (tic54x_status_bits): ... this. | |
| 475 | (misc_symbols): Rename to ... | |
| 476 | (tic54x_misc_symbols): ... this. | |
| 477 | ||
| 24075dcc NC |
478 | 2021-02-04 Nelson Chu <nelson.chu@sifive.com> |
| 479 | ||
| 480 | * riscv-opc.c (MASK_RVB_IMM): Removed. | |
| 481 | (riscv_opcodes): Removed zb* instructions. | |
| 482 | (riscv_ext_version_table): Removed versions for zb*. | |
| 483 | ||
| c3ffb8f3 AM |
484 | 2021-01-26 Alan Modra <amodra@gmail.com> |
| 485 | ||
| 486 | * i386-gen.c (parse_template): Ensure entire template_instance | |
| 487 | is initialised. | |
| 488 | ||
| 1942a048 NC |
489 | 2021-01-15 Nelson Chu <nelson.chu@sifive.com> |
| 490 | ||
| 491 | * riscv-opc.c (riscv_gpr_names_abi): Aligned the code. | |
| 492 | (riscv_fpr_names_abi): Likewise. | |
| 493 | (riscv_opcodes): Likewise. | |
| 494 | (riscv_insn_types): Likewise. | |
| 495 | ||
| b800637e NC |
496 | 2021-01-15 Nelson Chu <nelson.chu@sifive.com> |
| 497 | ||
| 498 | * riscv-dis.c (parse_riscv_dis_option): Fix typos of message. | |
| 499 | ||
| dcd709e0 NC |
500 | 2021-01-15 Nelson Chu <nelson.chu@sifive.com> |
| 501 | ||
| 502 | * riscv-dis.c: Comments tidy and improvement. | |
| 503 | * riscv-opc.c: Likewise. | |
| 504 | ||
| 5347ed60 AM |
505 | 2021-01-13 Alan Modra <amodra@gmail.com> |
| 506 | ||
| 507 | * Makefile.in: Regenerate. | |
| 508 | ||
| d546b610 L |
509 | 2021-01-12 H.J. Lu <hongjiu.lu@intel.com> |
| 510 | ||
| 511 | PR binutils/26792 | |
| 512 | * configure.ac: Use GNU_MAKE_JOBSERVER. | |
| 513 | * aclocal.m4: Regenerated. | |
| 514 | * configure: Likewise. | |
| 515 | ||
| 6d104cac NC |
516 | 2021-01-12 Nick Clifton <nickc@redhat.com> |
| 517 | ||
| 518 | * po/sr.po: Updated Serbian translation. | |
| 519 | ||
| 83b33c6c L |
520 | 2021-01-11 H.J. Lu <hongjiu.lu@intel.com> |
| 521 | ||
| 522 | PR ld/27173 | |
| 523 | * configure: Regenerated. | |
| 524 | ||
| 82c70b08 KT |
525 | 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> |
| 526 | ||
| 527 | * aarch64-asm-2.c: Regenerate. | |
| 528 | * aarch64-dis-2.c: Likewise. | |
| 529 | * aarch64-opc-2.c: Likewise. | |
| 530 | * aarch64-opc.c (aarch64_print_operand): | |
| 531 | Delete handling of AARCH64_OPND_CSRE_CSR. | |
| 532 | * aarch64-tbl.h (aarch64_feature_csre): Delete. | |
| 533 | (CSRE): Likewise. | |
| 534 | (_CSRE_INSN): Likewise. | |
| 535 | (aarch64_opcode_table): Delete csr. | |
| 536 | ||
| a8aa72b9 NC |
537 | 2021-01-11 Nick Clifton <nickc@redhat.com> |
| 538 | ||
| 539 | * po/de.po: Updated German translation. | |
| 540 | * po/fr.po: Updated French translation. | |
| 541 | * po/pt_BR.po: Updated Brazilian Portuguese translation. | |
| 542 | * po/sv.po: Updated Swedish translation. | |
| 543 | * po/uk.po: Updated Ukranian translation. | |
| 544 | ||
| a4966cd9 L |
545 | 2021-01-09 H.J. Lu <hongjiu.lu@intel.com> |
| 546 | ||
| 547 | * configure: Regenerated. | |
| 548 | ||
| 573fe3fb NC |
549 | 2021-01-09 Nick Clifton <nickc@redhat.com> |
| 550 | ||
| 551 | * configure: Regenerate. | |
| 552 | * po/opcodes.pot: Regenerate. | |
| 553 | ||
| 055bc77a NC |
554 | 2021-01-09 Nick Clifton <nickc@redhat.com> |
| 555 | ||
| 556 | * 2.36 release branch crated. | |
| 557 | ||
| aae7fcb8 PB |
558 | 2021-01-08 Peter Bergner <bergner@linux.ibm.com> |
| 559 | ||
| 560 | * ppc-opc.c (insert_dw, (extract_dw): New functions. | |
| 561 | (DW, (XRC_MASK): Define. | |
| 562 | (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics. | |
| 563 | ||
| 64307045 AM |
564 | 2021-01-09 Alan Modra <amodra@gmail.com> |
| 565 | ||
| 566 | * configure: Regenerate. | |
| 567 | ||
| ed205222 NC |
568 | 2021-01-08 Nick Clifton <nickc@redhat.com> |
| 569 | ||
| 570 | * po/sv.po: Updated Swedish translation. | |
| 571 | ||
| fb932b57 NC |
572 | 2021-01-08 Nick Clifton <nickc@redhat.com> |
| 573 | ||
| e84c8716 NC |
574 | PR 27129 |
| 575 | * aarch64-dis.c (determine_disassembling_preference): Move call to | |
| 576 | aarch64_match_operands_constraint outside of the assertion. | |
| 577 | * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert. | |
| 578 | Replace with a return of FALSE. | |
| 579 | ||
| fb932b57 NC |
580 | PR 27139 |
| 581 | * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a | |
| 582 | core system register. | |
| 583 | ||
| f4782128 ST |
584 | 2021-01-07 Samuel Thibault <samuel.thibault@gnu.org> |
| 585 | ||
| 586 | * configure: Regenerate. | |
| 587 | ||
| 1b0927db NC |
588 | 2021-01-07 Nick Clifton <nickc@redhat.com> |
| 589 | ||
| 590 | * po/fr.po: Updated French translation. | |
| 591 | ||
| 3b288c8e FN |
592 | 2021-01-07 Fredrik Noring <noring@nocrew.org> |
| 593 | ||
| 594 | * m68k-opc.c (chkl): Change minimum architecture requirement to | |
| 595 | m68020. | |
| 596 | ||
| aa881ecd PT |
597 | 2021-01-07 Philipp Tomsich <prt@gnu.org> |
| 598 | ||
| 599 | * riscv-opc.c (riscv_opcodes): Add pause hint instruction. | |
| 600 | ||
| 2652cfad CXW |
601 | 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com> |
| 602 | Jim Wilson <jimw@sifive.com> | |
| 603 | Andrew Waterman <andrew@sifive.com> | |
| 604 | Maxim Blinov <maxim.blinov@embecosm.com> | |
| 605 | Kito Cheng <kito.cheng@sifive.com> | |
| 606 | Nelson Chu <nelson.chu@sifive.com> | |
| 607 | ||
| 608 | * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions. | |
| 609 | (MASK_RVB_IMM): Used for rev8 and orc.b encoding. | |
| 610 | ||
| 250d07de AM |
611 | 2021-01-01 Alan Modra <amodra@gmail.com> |
| 612 | ||
| 613 | Update year range in copyright notice of all files. | |
| 614 | ||
| c2795844 | 615 | For older changes see ChangeLog-2020 |
| 3499769a | 616 | \f |
| c2795844 | 617 | Copyright (C) 2021 Free Software Foundation, Inc. |
| 3499769a AM |
618 | |
| 619 | Copying and distribution of this file, with or without modification, | |
| 620 | are permitted in any medium without royalty provided the copyright | |
| 621 | notice and this notice are preserved. | |
| 622 | ||
| 623 | Local Variables: | |
| 624 | mode: change-log | |
| 625 | left-margin: 8 | |
| 626 | fill-column: 74 | |
| 627 | version-control: never | |
| 628 | End: |