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[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
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12018-02-26 Alan Modra <amodra@gmail.com>
2
3 * crx-dis.c (getregliststring): Allocate a large enough buffer
4 to silence false positive gcc8 warning.
5
0bccfb29
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62018-02-22 Shea Levy <shea@shealevy.com>
7
8 * disassemble.c (ARCH_riscv): Define if ARCH_all.
9
6b6b6807
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102018-02-22 H.J. Lu <hongjiu.lu@intel.com>
11
12 * i386-opc.tbl: Add {rex},
13 * i386-tbl.h: Regenerated.
14
75f31665
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152018-02-20 Maciej W. Rozycki <macro@mips.com>
16
17 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
18 (mips16_opcodes): Replace `M' with `m' for "restore".
19
e207bc53
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202018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
21
22 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
23
87993319
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242018-02-13 Maciej W. Rozycki <macro@mips.com>
25
26 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
27 variable to `function_index'.
28
68d20676
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292018-02-13 Nick Clifton <nickc@redhat.com>
30
31 PR 22823
32 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
33 about truncation of printing.
34
d2159fdc
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352018-02-12 Henry Wong <henry@stuffedcow.net>
36
37 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
38
f174ef9f
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392018-02-05 Nick Clifton <nickc@redhat.com>
40
41 * po/pt_BR.po: Updated Brazilian Portuguese translation.
42
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432018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
44
45 * i386-dis.c (enum): Add pconfig.
46 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
47 (cpu_flags): Add CpuPCONFIG.
48 * i386-opc.h (enum): Add CpuPCONFIG.
49 (i386_cpu_flags): Add cpupconfig.
50 * i386-opc.tbl: Add PCONFIG instruction.
51 * i386-init.h: Regenerate.
52 * i386-tbl.h: Likewise.
53
3233d7d0
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542018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
55
56 * i386-dis.c (enum): Add PREFIX_0F09.
57 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
58 (cpu_flags): Add CpuWBNOINVD.
59 * i386-opc.h (enum): Add CpuWBNOINVD.
60 (i386_cpu_flags): Add cpuwbnoinvd.
61 * i386-opc.tbl: Add WBNOINVD instruction.
62 * i386-init.h: Regenerate.
63 * i386-tbl.h: Likewise.
64
e925c834
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652018-01-17 Jim Wilson <jimw@sifive.com>
66
67 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
68
d777820b
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692018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
70
71 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
72 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
73 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
74 (cpu_flags): Add CpuIBT, CpuSHSTK.
75 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
76 (i386_cpu_flags): Add cpuibt, cpushstk.
77 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
78 * i386-init.h: Regenerate.
79 * i386-tbl.h: Likewise.
80
f6efed01
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812018-01-16 Nick Clifton <nickc@redhat.com>
82
83 * po/pt_BR.po: Updated Brazilian Portugese translation.
84 * po/de.po: Updated German translation.
85
2721d702
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862018-01-15 Jim Wilson <jimw@sifive.com>
87
88 * riscv-opc.c (match_c_nop): New.
89 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
90
616dcb87
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912018-01-15 Nick Clifton <nickc@redhat.com>
92
93 * po/uk.po: Updated Ukranian translation.
94
3957a496
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952018-01-13 Nick Clifton <nickc@redhat.com>
96
97 * po/opcodes.pot: Regenerated.
98
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992018-01-13 Nick Clifton <nickc@redhat.com>
100
101 * configure: Regenerate.
102
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1032018-01-13 Nick Clifton <nickc@redhat.com>
104
105 2.30 branch created.
106
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1072018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
108
109 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
110 * i386-tbl.h: Regenerate.
111
cbda583a
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1122018-01-10 Jan Beulich <jbeulich@suse.com>
113
114 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
115 * i386-tbl.h: Re-generate.
116
c9e92278
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1172018-01-10 Jan Beulich <jbeulich@suse.com>
118
119 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
120 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
121 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
122 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
123 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
124 Disp8MemShift of AVX512VL forms.
125 * i386-tbl.h: Re-generate.
126
35fd2b2b
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1272018-01-09 Jim Wilson <jimw@sifive.com>
128
129 * riscv-dis.c (maybe_print_address): If base_reg is zero,
130 then the hi_addr value is zero.
131
91d8b670
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1322018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
133
134 * arm-dis.c (arm_opcodes): Add csdb.
135 (thumb32_opcodes): Add csdb.
136
be2e7d95
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1372018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
138
139 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
140 * aarch64-asm-2.c: Regenerate.
141 * aarch64-dis-2.c: Regenerate.
142 * aarch64-opc-2.c: Regenerate.
143
704a705d
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1442018-01-08 H.J. Lu <hongjiu.lu@intel.com>
145
146 PR gas/22681
147 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
148 Remove AVX512 vmovd with 64-bit operands.
149 * i386-tbl.h: Regenerated.
150
35eeb78f
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1512018-01-05 Jim Wilson <jimw@sifive.com>
152
153 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
154 jalr.
155
219d1afa
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1562018-01-03 Alan Modra <amodra@gmail.com>
157
158 Update year range in copyright notice of all files.
159
1508bbf5
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1602018-01-02 Jan Beulich <jbeulich@suse.com>
161
162 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
163 and OPERAND_TYPE_REGZMM entries.
164
1e563868 165For older changes see ChangeLog-2017
3499769a 166\f
1e563868 167Copyright (C) 2018 Free Software Foundation, Inc.
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168
169Copying and distribution of this file, with or without modification,
170are permitted in any medium without royalty provided the copyright
171notice and this notice are preserved.
172
173Local Variables:
174mode: change-log
175left-margin: 8
176fill-column: 74
177version-control: never
178End: