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[MIPS/GAS] Split Loongson EXT Instructions from loongson3a.
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
bdc6c06e
CX		 12018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
2
3 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
4 descriptors.
5 (parse_mips_ase_option): Handle -M loongson-ext option.
6 (print_mips_disassembler_options): Document -M loongson-ext.
7 * mips-opc.c (IL3A): Delete.
8 * mips-opc.c (LEXT): New macro.
9 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
10 instructions.
11
716c08de
CX		 122018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
13
14 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
15 descriptors.
16 (parse_mips_ase_option): Handle -M loongson-cam option.
17 (print_mips_disassembler_options): Document -M loongson-cam.
18 * mips-opc.c (LCAM): New macro.
19 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
20 instructions.
21
9cf7e568
AM		 222018-08-21 Alan Modra <amodra@gmail.com>
23
24 * ppc-dis.c (operand_value_powerpc): Init "invalid".
25 (skip_optional_operands): Count optional operands, and update
26 ppc_optional_operand_value call.
27 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
28 (extract_vlensi): Likewise.
29 (extract_fxm): Return default value for missing optional operand.
30 (extract_ls, extract_raq, extract_tbr): Likewise.
31 (insert_sxl, extract_sxl): New functions.
32 (insert_esync, extract_esync): Remove Power9 handling and simplify.
33 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
34 flag and extra entry.
35 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
36 extract_sxl.
37
d203b41a 382018-08-20 Alan Modra <amodra@gmail.com>
f4107842 39
d203b41a 40 * sh-opc.h (MASK): Simplify.
f4107842 41
08a8fe2f 422018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 43
d203b41a
AM		 44 * s12z-dis.c (bm_decode): Deal with cases where the mode is
45 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 46 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 47
08a8fe2f 482018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 49
50 * s12z.h: Delete.
7ba3ba91 51
1bc60e56
L		 522018-08-14 H.J. Lu <hongjiu.lu@intel.com>
53
54 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
55 address with the addr32 prefix and without base nor index
56 registers.
57
d871f3f4
L		 582018-08-11 H.J. Lu <hongjiu.lu@intel.com>
59
60 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
61 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
62 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
63 (cpu_flags): Add CpuCMOV and CpuFXSR.
64 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
65 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
66 * i386-init.h: Regenerated.
67 * i386-tbl.h: Likewise.
68
b6523c37 692018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
70
71 * arc-regs.h: Update auxiliary registers.
72
e968fc9b
JB		 732018-08-06 Jan Beulich <jbeulich@suse.com>
74
75 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
76 (RegIP, RegIZ): Define.
77 * i386-reg.tbl: Adjust comments.
78 (rip): Use Qword instead of BaseIndex. Use RegIP.
79 (eip): Use Dword instead of BaseIndex. Use RegIP.
80 (riz): Add Qword. Use RegIZ.
81 (eiz): Add Dword. Use RegIZ.
82 * i386-tbl.h: Re-generate.
83
dbf8be89
JB		 842018-08-03 Jan Beulich <jbeulich@suse.com>
85
86 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
87 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
88 vpmovzxdq, vpmovzxwd): Remove NoRex64.
89 * i386-tbl.h: Re-generate.
90
c48dadc9
JB		 912018-08-03 Jan Beulich <jbeulich@suse.com>
92
93 * i386-gen.c (operand_types): Remove Mem field.
94 * i386-opc.h (union i386_operand_type): Remove mem field.
95 * i386-init.h, i386-tbl.h: Re-generate.
96
cb86a42a
AM		 972018-08-01 Alan Modra <amodra@gmail.com>
98
99 * po/POTFILES.in: Regenerate.
100
07cc0450
NC		 1012018-07-31 Nick Clifton <nickc@redhat.com>
102
103 * po/sv.po: Updated Swedish translation.
104
1424ad86
JB		 1052018-07-31 Jan Beulich <jbeulich@suse.com>
106
107 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
108 * i386-init.h, i386-tbl.h: Re-generate.
109
ae2387fe
JB		 1102018-07-31 Jan Beulich <jbeulich@suse.com>
111
112 * i386-opc.h (ZEROING_MASKING) Rename to ...
113 (DYNAMIC_MASKING): ... this. Adjust comment.
114 * i386-opc.tbl (MaskingMorZ): Define.
115 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
116 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
117 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
118 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
119 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
120 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
121 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
122 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
123 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
124
6ff00b5e
JB		 1252018-07-31 Jan Beulich <jbeulich@suse.com>
126
127 * i386-opc.tbl: Use element rather than vector size for AVX512*
128 scatter/gather insns.
129 * i386-tbl.h: Re-generate.
130
e951d5ca
JB		 1312018-07-31 Jan Beulich <jbeulich@suse.com>
132
133 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
134 (cpu_flags): Drop CpuVREX.
135 * i386-opc.h (CpuVREX): Delete.
136 (union i386_cpu_flags): Remove cpuvrex.
137 * i386-init.h, i386-tbl.h: Re-generate.
138
eb41b248
JW		 1392018-07-30 Jim Wilson <jimw@sifive.com>
140
141 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
142 fields.
143 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
144
b8891f8d
AJ		 1452018-07-30 Andrew Jenner <andrew@codesourcery.com>
146
147 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
148 * Makefile.in: Regenerated.
149 * configure.ac: Add C-SKY.
150 * configure: Regenerated.
151 * csky-dis.c: New file.
152 * csky-opc.h: New file.
153 * disassemble.c (ARCH_csky): Define.
154 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
155 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
156
16065af1
AM		 1572018-07-27 Alan Modra <amodra@gmail.com>
158
159 * ppc-opc.c (insert_sprbat): Correct function parameter and
160 return type.
161 (extract_sprbat): Likewise, variable too.
162
fa758a70
AC		 1632018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
164 Alan Modra <amodra@gmail.com>
165
166 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
167 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
168 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
169 support disjointed BAT.
170 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
171 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
172 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
173
4a1b91ea
L		 1742018-07-25 H.J. Lu <hongjiu.lu@intel.com>
175 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
176
177 * i386-gen.c (adjust_broadcast_modifier): New function.
178 (process_i386_opcode_modifier): Add an argument for operands.
179 Adjust the Broadcast value based on operands.
180 (output_i386_opcode): Pass operand_types to
181 process_i386_opcode_modifier.
182 (process_i386_opcodes): Pass NULL as operands to
183 process_i386_opcode_modifier.
184 * i386-opc.h (BYTE_BROADCAST): New.
185 (WORD_BROADCAST): Likewise.
186 (DWORD_BROADCAST): Likewise.
187 (QWORD_BROADCAST): Likewise.
188 (i386_opcode_modifier): Expand broadcast to 3 bits.
189 * i386-tbl.h: Regenerated.
190
67ce483b
AM		 1912018-07-24 Alan Modra <amodra@gmail.com>
192
193 PR 23430
194 * or1k-desc.h: Regenerate.
195
4174bfff
JB		 1962018-07-24 Jan Beulich <jbeulich@suse.com>
197
198 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
199 vcvtusi2ss, and vcvtusi2sd.
200 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
201 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
202 * i386-tbl.h: Re-generate.
203
04e65276
CZ		 2042018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
205
206 * arc-opc.c (extract_w6): Fix extending the sign.
207
47e6f81c
CZ		 2082018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
209
210 * arc-tbl.h (vewt): Allow it for ARC EM family.
211
bb71536f
AM		 2122018-07-23 Alan Modra <amodra@gmail.com>
213
214 PR 23419
215 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
216 opcode variants for mtspr/mfspr encodings.
217
8095d2f7
CX		 2182018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
219 Maciej W. Rozycki <macro@mips.com>
220
221 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
222 loongson3a descriptors.
223 (parse_mips_ase_option): Handle -M loongson-mmi option.
224 (print_mips_disassembler_options): Document -M loongson-mmi.
225 * mips-opc.c (LMMI): New macro.
226 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
227 instructions.
228
5f32791e
JB		 2292018-07-19 Jan Beulich <jbeulich@suse.com>
230
231 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
232 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
233 IgnoreSize and [XYZ]MMword where applicable.
234 * i386-tbl.h: Re-generate.
235
625cbd7a
JB		 2362018-07-19 Jan Beulich <jbeulich@suse.com>
237
238 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
239 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
240 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
241 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
242 * i386-tbl.h: Re-generate.
243
86b15c32
JB		 2442018-07-19 Jan Beulich <jbeulich@suse.com>
245
246 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
247 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
248 VPCLMULQDQ templates into their respective AVX512VL counterparts
249 where possible, using Disp8ShiftVL and CheckRegSize instead of
250 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
251 * i386-tbl.h: Re-generate.
252
cf769ed5
JB		 2532018-07-19 Jan Beulich <jbeulich@suse.com>
254
255 * i386-opc.tbl: Fold AVX512DQ templates into their respective
256 AVX512VL counterparts where possible, using Disp8ShiftVL and
257 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
258 IgnoreSize) as appropriate.
259 * i386-tbl.h: Re-generate.
260
8282b7ad
JB		 2612018-07-19 Jan Beulich <jbeulich@suse.com>
262
263 * i386-opc.tbl: Fold AVX512BW templates into their respective
264 AVX512VL counterparts where possible, using Disp8ShiftVL and
265 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
266 IgnoreSize) as appropriate.
267 * i386-tbl.h: Re-generate.
268
755908cc
JB		 2692018-07-19 Jan Beulich <jbeulich@suse.com>
270
271 * i386-opc.tbl: Fold AVX512CD templates into their respective
272 AVX512VL counterparts where possible, using Disp8ShiftVL and
273 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
274 IgnoreSize) as appropriate.
275 * i386-tbl.h: Re-generate.
276
7091c612
JB		 2772018-07-19 Jan Beulich <jbeulich@suse.com>
278
279 * i386-opc.h (DISP8_SHIFT_VL): New.
280 * i386-opc.tbl (Disp8ShiftVL): Define.
281 (various): Fold AVX512VL templates into their respective
282 AVX512F counterparts where possible, using Disp8ShiftVL and
283 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
284 IgnoreSize) as appropriate.
285 * i386-tbl.h: Re-generate.
286
c30be56e
JB		 2872018-07-19 Jan Beulich <jbeulich@suse.com>
288
289 * Makefile.am: Change dependencies and rule for
290 $(srcdir)/i386-init.h.
291 * Makefile.in: Re-generate.
292 * i386-gen.c (process_i386_opcodes): New local variable
293 "marker". Drop opening of input file. Recognize marker and line
294 number directives.
295 * i386-opc.tbl (OPCODE_I386_H): Define.
296 (i386-opc.h): Include it.
297 (None): Undefine.
298
11a322db
L		 2992018-07-18 H.J. Lu <hongjiu.lu@intel.com>
300
301 PR gas/23418
302 * i386-opc.h (Byte): Update comments.
303 (Word): Likewise.
304 (Dword): Likewise.
305 (Fword): Likewise.
306 (Qword): Likewise.
307 (Tbyte): Likewise.
308 (Xmmword): Likewise.
309 (Ymmword): Likewise.
310 (Zmmword): Likewise.
311 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
312 vcvttps2uqq.
313 * i386-tbl.h: Regenerated.
314
cde3679e
NC		 3152018-07-12 Sudakshina Das <sudi.das@arm.com>
316
317 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
318 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
319 * aarch64-asm-2.c: Regenerate.
320 * aarch64-dis-2.c: Regenerate.
321 * aarch64-opc-2.c: Regenerate.
322
45a28947
TC		 3232018-07-12 Tamar Christina <tamar.christina@arm.com>
324
325 PR binutils/23192
326 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
327 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
328 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
329 sqdmulh, sqrdmulh): Use Em16.
330
c597cc3d
SD		 3312018-07-11 Sudakshina Das <sudi.das@arm.com>
332
333 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
334 csdb together with them.
335 (thumb32_opcodes): Likewise.
336
a79eaed6
JB		 3372018-07-11 Jan Beulich <jbeulich@suse.com>
338
339 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
340 requiring 32-bit registers as operands 2 and 3. Improve
341 comments.
342 (mwait, mwaitx): Fold templates. Improve comments.
343 OPERAND_TYPE_INOUTPORTREG.
344 * i386-tbl.h: Re-generate.
345
2fb5be8d
JB		 3462018-07-11 Jan Beulich <jbeulich@suse.com>
347
348 * i386-gen.c (operand_type_init): Remove
349 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
350 OPERAND_TYPE_INOUTPORTREG.
351 * i386-init.h: Re-generate.
352
7f5cad30
JB		 3532018-07-11 Jan Beulich <jbeulich@suse.com>
354
355 * i386-opc.tbl (wrssd, wrussd): Add Dword.
356 (wrssq, wrussq): Add Qword.
357 * i386-tbl.h: Re-generate.
358
f0a85b07
JB		 3592018-07-11 Jan Beulich <jbeulich@suse.com>
360
361 * i386-opc.h: Rename OTMax to OTNum.
362 (OTNumOfUints): Adjust calculation.
363 (OTUnused): Directly alias to OTNum.
364
9dcb0ba4
MR		 3652018-07-09 Maciej W. Rozycki <macro@mips.com>
366
367 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
368 `reg_xys'.
369 (lea_reg_xys): Likewise.
370 (print_insn_loop_primitive): Rename `reg' local variable to
371 `reg_dxy'.
372
f311ba7e
TC		 3732018-07-06 Tamar Christina <tamar.christina@arm.com>
374
375 PR binutils/23242
376 * aarch64-tbl.h (ldarh): Fix disassembly mask.
377
cba05feb
TC		 3782018-07-06 Tamar Christina <tamar.christina@arm.com>
379
380 PR binutils/23369
381 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
382 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
383
471b9d15
MR		 3842018-07-02 Maciej W. Rozycki <macro@mips.com>
385
386 PR tdep/8282
387 * mips-dis.c (mips_option_arg_t): New enumeration.
388 (mips_options): New variable.
389 (disassembler_options_mips): New function.
390 (print_mips_disassembler_options): Reimplement in terms of
391 `disassembler_options_mips'.
392 * arm-dis.c (disassembler_options_arm): Adapt to using the
393 `disasm_options_and_args_t' structure.
394 * ppc-dis.c (disassembler_options_powerpc): Likewise.
395 * s390-dis.c (disassembler_options_s390): Likewise.
396
c0c468d5
TP		 3972018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
398
399 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
400 expected result.
401 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
402 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
403 * testsuite/ld-arm/tls-longplt.d: Likewise.
404
369c9167
TC		 4052018-06-29 Tamar Christina <tamar.christina@arm.com>
406
407 PR binutils/23192
408 * aarch64-asm-2.c: Regenerate.
409 * aarch64-dis-2.c: Likewise.
410 * aarch64-opc-2.c: Likewise.
411 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
412 * aarch64-opc.c (operand_general_constraint_met_p,
413 aarch64_print_operand): Likewise.
414 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
415 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
416 fmlal2, fmlsl2.
417 (AARCH64_OPERANDS): Add Em2.
418
30aa1306
NC		 4192018-06-26 Nick Clifton <nickc@redhat.com>
420
421 * po/uk.po: Updated Ukranian translation.
422 * po/de.po: Updated German translation.
423 * po/pt_BR.po: Updated Brazilian Portuguese translation.
424
eca4b721
NC		 4252018-06-26 Nick Clifton <nickc@redhat.com>
426
427 * nfp-dis.c: Fix spelling mistake.
428
71300e2c
NC		 4292018-06-24 Nick Clifton <nickc@redhat.com>
430
431 * configure: Regenerate.
432 * po/opcodes.pot: Regenerate.
433
719d8288
NC		 4342018-06-24 Nick Clifton <nickc@redhat.com>
435
436 2.31 branch created.
437
514cd3a0
TC		 4382018-06-19 Tamar Christina <tamar.christina@arm.com>
439
440 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
441 * aarch64-asm-2.c: Regenerate.
442 * aarch64-dis-2.c: Likewise.
443
385e4d0f
MR		 4442018-06-21 Maciej W. Rozycki <macro@mips.com>
445
446 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
447 `-M ginv' option description.
448
160d1b3d
SH		 4492018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
450
451 PR gas/23305
452 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
453 la and lla.
454
d0ac1c44
SM		 4552018-06-19 Simon Marchi <simon.marchi@ericsson.com>
456
457 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
458 * configure.ac: Remove AC_PREREQ.
459 * Makefile.in: Re-generate.
460 * aclocal.m4: Re-generate.
461 * configure: Re-generate.
462
6f20c942
FS		 4632018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
464
465 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
466 mips64r6 descriptors.
467 (parse_mips_ase_option): Handle -Mginv option.
468 (print_mips_disassembler_options): Document -Mginv.
469 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
470 (GINV): New macro.
471 (mips_opcodes): Define ginvi and ginvt.
472
730c3174
SE		 4732018-06-13 Scott Egerton <scott.egerton@imgtec.com>
474 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
475
476 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
477 * mips-opc.c (CRC, CRC64): New macros.
478 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
479 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
480 crc32cd for CRC64.
481
cb366992
EB		 4822018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
483
484 PR 20319
485 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
486 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
487
ce72cd46
AM		 4882018-06-06 Alan Modra <amodra@gmail.com>
489
490 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
491 setjmp. Move init for some other vars later too.
492
4b8e28c7
MF		 4932018-06-04 Max Filippov <jcmvbkbc@gmail.com>
494
495 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
496 (dis_private): Add new fields for property section tracking.
497 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
498 (xtensa_instruction_fits): New functions.
499 (fetch_data): Bump minimal fetch size to 4.
500 (print_insn_xtensa): Make struct dis_private static.
501 Load and prepare property table on section change.
502 Don't disassemble literals. Don't disassemble instructions that
503 cross property table boundaries.
504
55e99962
L		 5052018-06-01 H.J. Lu <hongjiu.lu@intel.com>
506
507 * configure: Regenerated.
508
733bd0ab
JB		 5092018-06-01 Jan Beulich <jbeulich@suse.com>
510
511 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
512 * i386-tbl.h: Re-generate.
513
dfd27d41
JB		 5142018-06-01 Jan Beulich <jbeulich@suse.com>
515
516 * i386-opc.tbl (sldt, str): Add NoRex64.
517 * i386-tbl.h: Re-generate.
518
64795710
JB		 5192018-06-01 Jan Beulich <jbeulich@suse.com>
520
521 * i386-opc.tbl (invpcid): Add Oword.
522 * i386-tbl.h: Re-generate.
523
030157d8
AM		 5242018-06-01 Alan Modra <amodra@gmail.com>
525
526 * sysdep.h (_bfd_error_handler): Don't declare.
527 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
528 * rl78-decode.opc: Likewise.
529 * msp430-decode.c: Regenerate.
530 * rl78-decode.c: Regenerate.
531
a9660a6f
AP		 5322018-05-30 Amit Pawar <Amit.Pawar@amd.com>
533
534 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
535 * i386-init.h : Regenerated.
536
277eb7f6
AM		 5372018-05-25 Alan Modra <amodra@gmail.com>
538
539 * Makefile.in: Regenerate.
540 * po/POTFILES.in: Regenerate.
541
98553ad3
PB		 5422018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
543
544 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
545 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
546 (insert_bab, extract_bab, insert_btab, extract_btab,
547 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
548 (BAT, BBA VBA RBS XB6S): Delete macros.
549 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
550 (BB, BD, RBX, XC6): Update for new macros.
551 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
552 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
553 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
554 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
555
7b4ae824
JD		 5562018-05-18 John Darrington <john@darrington.wattle.id.au>
557
558 * Makefile.am: Add support for s12z architecture.
559 * configure.ac: Likewise.
560 * disassemble.c: Likewise.
561 * disassemble.h: Likewise.
562 * Makefile.in: Regenerate.
563 * configure: Regenerate.
564 * s12z-dis.c: New file.
565 * s12z.h: New file.
566
29e0f0a1
AM		 5672018-05-18 Alan Modra <amodra@gmail.com>
568
569 * nfp-dis.c: Don't #include libbfd.h.
570 (init_nfp3200_priv): Use bfd_get_section_contents.
571 (nit_nfp6000_mecsr_sec): Likewise.
572
809276d2
NC		 5732018-05-17 Nick Clifton <nickc@redhat.com>
574
575 * po/zh_CN.po: Updated simplified Chinese translation.
576
ff329288
TC		 5772018-05-16 Tamar Christina <tamar.christina@arm.com>
578
579 PR binutils/23109
580 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
581 * aarch64-dis-2.c: Regenerate.
582
f9830ec1
TC		 5832018-05-15 Tamar Christina <tamar.christina@arm.com>
584
585 PR binutils/21446
586 * aarch64-asm.c (opintl.h): Include.
587 (aarch64_ins_sysreg): Enforce read/write constraints.
588 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
589 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
590 (F_REG_READ, F_REG_WRITE): New.
591 * aarch64-opc.c (aarch64_print_operand): Generate notes for
592 AARCH64_OPND_SYSREG.
593 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
594 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
595 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
596 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
597 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
598 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
599 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
600 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
601 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
602 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
603 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
604 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
605 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
606 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
607 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
608 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
609 msr (F_SYS_WRITE), mrs (F_SYS_READ).
610
7d02540a
TC		 6112018-05-15 Tamar Christina <tamar.christina@arm.com>
612
613 PR binutils/21446
614 * aarch64-dis.c (no_notes: New.
615 (parse_aarch64_dis_option): Support notes.
616 (aarch64_decode_insn, print_operands): Likewise.
617 (print_aarch64_disassembler_options): Document notes.
618 * aarch64-opc.c (aarch64_print_operand): Support notes.
619
561a72d4
TC		 6202018-05-15 Tamar Christina <tamar.christina@arm.com>
621
622 PR binutils/21446
623 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
624 and take error struct.
625 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
626 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
627 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
628 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
629 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
630 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
631 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
632 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
633 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
634 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
635 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
636 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
637 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
638 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
639 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
640 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
641 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
642 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
643 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
644 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
645 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
646 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
647 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
648 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
649 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
650 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
651 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
652 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
653 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
654 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
655 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
656 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
657 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
658 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
659 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
660 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
661 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
662 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
663 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
664 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
665 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
666 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
667 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
668 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
669 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
670 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
671 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
672 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
673 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
674 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
675 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
676 (determine_disassembling_preference, aarch64_decode_insn,
677 print_insn_aarch64_word, print_insn_data): Take errors struct.
678 (print_insn_aarch64): Use errors.
679 * aarch64-asm-2.c: Regenerate.
680 * aarch64-dis-2.c: Regenerate.
681 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
682 boolean in aarch64_insert_operan.
683 (print_operand_extractor): Likewise.
684 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
685
1678bd35
FT		 6862018-05-15 Francois H. Theron <francois.theron@netronome.com>
687
688 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
689
06cfb1c8
L		 6902018-05-09 H.J. Lu <hongjiu.lu@intel.com>
691
692 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
693
84f9f8c3
AM		 6942018-05-09 Sebastian Rasmussen <sebras@gmail.com>
695
696 * cr16-opc.c (cr16_instruction): Comment typo fix.
697 * hppa-dis.c (print_insn_hppa): Likewise.
698
e6f372ba
JW		 6992018-05-08 Jim Wilson <jimw@sifive.com>
700
701 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
702 (match_c_slli64, match_srxi_as_c_srxi): New.
703 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
704 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
705 <c.slli, c.srli, c.srai>: Use match_s_slli.
706 <c.slli64, c.srli64, c.srai64>: New.
707
f413a913
AM		 7082018-05-08 Alan Modra <amodra@gmail.com>
709
710 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
711 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
712 partition opcode space for index lookup.
713
a87a6478
PB		 7142018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
715
716 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
717 <insn_length>: ...with this. Update usage.
718 Remove duplicate call to *info->memory_error_func.
719
c0a30a9f
L		 7202018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
721 H.J. Lu <hongjiu.lu@intel.com>
722
723 * i386-dis.c (Gva): New.
724 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
725 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
726 (prefix_table): New instructions (see prefix above).
727 (mod_table): New instructions (see prefix above).
728 (OP_G): Handle va_mode.
729 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
730 CPU_MOVDIR64B_FLAGS.
731 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
732 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
733 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
734 * i386-opc.tbl: Add movidir{i,64b}.
735 * i386-init.h: Regenerated.
736 * i386-tbl.h: Likewise.
737
75c0a438
L		 7382018-05-07 H.J. Lu <hongjiu.lu@intel.com>
739
740 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
741 AddrPrefixOpReg.
742 * i386-opc.h (AddrPrefixOp0): Renamed to ...
743 (AddrPrefixOpReg): This.
744 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
745 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
746
2ceb7719
PB		 7472018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
748
749 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
750 (vle_num_opcodes): Likewise.
751 (spe2_num_opcodes): Likewise.
752 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
753 initialization loop.
754 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
755 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
756 only once.
757
b3ac5c6c
TC		 7582018-05-01 Tamar Christina <tamar.christina@arm.com>
759
760 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
761
fe944acf
FT		 7622018-04-30 Francois H. Theron <francois.theron@netronome.com>
763
764 Makefile.am: Added nfp-dis.c.
765 configure.ac: Added bfd_nfp_arch.
766 disassemble.h: Added print_insn_nfp prototype.
767 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
768 nfp-dis.c: New, for NFP support.
769 po/POTFILES.in: Added nfp-dis.c to the list.
770 Makefile.in: Regenerate.
771 configure: Regenerate.
772
e2195274
JB		 7732018-04-26 Jan Beulich <jbeulich@suse.com>
774
775 * i386-opc.tbl: Fold various non-memory operand AVX512VL
776 templates into their base ones.
777 * i386-tlb.h: Re-generate.
778
59ef5df4
JB		 7792018-04-26 Jan Beulich <jbeulich@suse.com>
780
781 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
782 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
783 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
784 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
785 * i386-init.h: Re-generate.
786
6e041cf4
JB		 7872018-04-26 Jan Beulich <jbeulich@suse.com>
788
789 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
790 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
791 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
792 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
793 comment.
794 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
795 and CpuRegMask.
796 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
797 CpuRegMask: Delete.
798 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
799 cpuregzmm, and cpuregmask.
800 * i386-init.h: Re-generate.
801 * i386-tbl.h: Re-generate.
802
0e0eea78
JB		 8032018-04-26 Jan Beulich <jbeulich@suse.com>
804
805 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
806 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
807 * i386-init.h: Re-generate.
808
2f1bada2
JB		 8092018-04-26 Jan Beulich <jbeulich@suse.com>
810
811 * i386-gen.c (VexImmExt): Delete.
812 * i386-opc.h (VexImmExt, veximmext): Delete.
813 * i386-opc.tbl: Drop all VexImmExt uses.
814 * i386-tlb.h: Re-generate.
815
bacd1457
JB		 8162018-04-25 Jan Beulich <jbeulich@suse.com>
817
818 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
819 register-only forms.
820 * i386-tlb.h: Re-generate.
821
10bba94b
TC		 8222018-04-25 Tamar Christina <tamar.christina@arm.com>
823
824 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
825
c48935d7
IT		 8262018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
827
828 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
829 PREFIX_0F1C.
830 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
831 (cpu_flags): Add CpuCLDEMOTE.
832 * i386-init.h: Regenerate.
833 * i386-opc.h (enum): Add CpuCLDEMOTE,
834 (i386_cpu_flags): Add cpucldemote.
835 * i386-opc.tbl: Add cldemote.
836 * i386-tbl.h: Regenerate.
837
211dc24b
AM		 8382018-04-16 Alan Modra <amodra@gmail.com>
839
840 * Makefile.am: Remove sh5 and sh64 support.
841 * configure.ac: Likewise.
842 * disassemble.c: Likewise.
843 * disassemble.h: Likewise.
844 * sh-dis.c: Likewise.
845 * sh64-dis.c: Delete.
846 * sh64-opc.c: Delete.
847 * sh64-opc.h: Delete.
848 * Makefile.in: Regenerate.
849 * configure: Regenerate.
850 * po/POTFILES.in: Regenerate.
851
a9a4b302
AM		 8522018-04-16 Alan Modra <amodra@gmail.com>
853
854 * Makefile.am: Remove w65 support.
855 * configure.ac: Likewise.
856 * disassemble.c: Likewise.
857 * disassemble.h: Likewise.
858 * w65-dis.c: Delete.
859 * w65-opc.h: Delete.
860 * Makefile.in: Regenerate.
861 * configure: Regenerate.
862 * po/POTFILES.in: Regenerate.
863
04cb01fd
AM		 8642018-04-16 Alan Modra <amodra@gmail.com>
865
866 * configure.ac: Remove we32k support.
867 * configure: Regenerate.
868
c2bf1eec
AM		 8692018-04-16 Alan Modra <amodra@gmail.com>
870
871 * Makefile.am: Remove m88k support.
872 * configure.ac: Likewise.
873 * disassemble.c: Likewise.
874 * disassemble.h: Likewise.
875 * m88k-dis.c: Delete.
876 * Makefile.in: Regenerate.
877 * configure: Regenerate.
878 * po/POTFILES.in: Regenerate.
879
6793974d
AM		 8802018-04-16 Alan Modra <amodra@gmail.com>
881
882 * Makefile.am: Remove i370 support.
883 * configure.ac: Likewise.
884 * disassemble.c: Likewise.
885 * disassemble.h: Likewise.
886 * i370-dis.c: Delete.
887 * i370-opc.c: Delete.
888 * Makefile.in: Regenerate.
889 * configure: Regenerate.
890 * po/POTFILES.in: Regenerate.
891
e82aa794
AM		 8922018-04-16 Alan Modra <amodra@gmail.com>
893
894 * Makefile.am: Remove h8500 support.
895 * configure.ac: Likewise.
896 * disassemble.c: Likewise.
897 * disassemble.h: Likewise.
898 * h8500-dis.c: Delete.
899 * h8500-opc.h: Delete.
900 * Makefile.in: Regenerate.
901 * configure: Regenerate.
902 * po/POTFILES.in: Regenerate.
903
fceadf09
AM		 9042018-04-16 Alan Modra <amodra@gmail.com>
905
906 * configure.ac: Remove tahoe support.
907 * configure: Regenerate.
908
ae1d3843
L		 9092018-04-15 H.J. Lu <hongjiu.lu@intel.com>
910
911 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
912 umwait.
913 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
914 64-bit mode.
915 * i386-tbl.h: Regenerated.
916
de89d0a3
IT		 9172018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
918
919 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
920 PREFIX_MOD_1_0FAE_REG_6.
921 (va_mode): New.
922 (OP_E_register): Use va_mode.
923 * i386-dis-evex.h (prefix_table):
924 New instructions (see prefixes above).
925 * i386-gen.c (cpu_flag_init): Add WAITPKG.
926 (cpu_flags): Likewise.
927 * i386-opc.h (enum): Likewise.
928 (i386_cpu_flags): Likewise.
929 * i386-opc.tbl: Add umonitor, umwait, tpause.
930 * i386-init.h: Regenerate.
931 * i386-tbl.h: Likewise.
932
a8eb42a8
AM		 9332018-04-11 Alan Modra <amodra@gmail.com>
934
935 * opcodes/i860-dis.c: Delete.
936 * opcodes/i960-dis.c: Delete.
937 * Makefile.am: Remove i860 and i960 support.
938 * configure.ac: Likewise.
939 * disassemble.c: Likewise.
940 * disassemble.h: Likewise.
941 * Makefile.in: Regenerate.
942 * configure: Regenerate.
943 * po/POTFILES.in: Regenerate.
944
caf0678c
L		 9452018-04-04 H.J. Lu <hongjiu.lu@intel.com>
946
947 PR binutils/23025
948 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
949 to 0.
950 (print_insn): Clear vex instead of vex.evex.
951
4fb0d2b9
NC		 9522018-04-04 Nick Clifton <nickc@redhat.com>
953
954 * po/es.po: Updated Spanish translation.
955
c39e5b26
JB		 9562018-03-28 Jan Beulich <jbeulich@suse.com>
957
958 * i386-gen.c (opcode_modifiers): Delete VecESize.
959 * i386-opc.h (VecESize): Delete.
960 (struct i386_opcode_modifier): Delete vecesize.
961 * i386-opc.tbl: Drop VecESize.
962 * i386-tlb.h: Re-generate.
963
8e6e0792
JB		 9642018-03-28 Jan Beulich <jbeulich@suse.com>
965
966 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
967 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
968 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
969 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
970 * i386-tlb.h: Re-generate.
971
9f123b91
JB		 9722018-03-28 Jan Beulich <jbeulich@suse.com>
973
974 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
975 Fold AVX512 forms
976 * i386-tlb.h: Re-generate.
977
9646c87b
JB		 9782018-03-28 Jan Beulich <jbeulich@suse.com>
979
980 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
981 (vex_len_table): Drop Y for vcvt*2si.
982 (putop): Replace plain 'Y' handling by abort().
983
c8d59609
NC		 9842018-03-28 Nick Clifton <nickc@redhat.com>
985
986 PR 22988
987 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
988 instructions with only a base address register.
989 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
990 handle AARHC64_OPND_SVE_ADDR_R.
991 (aarch64_print_operand): Likewise.
992 * aarch64-asm-2.c: Regenerate.
993 * aarch64_dis-2.c: Regenerate.
994 * aarch64-opc-2.c: Regenerate.
995
b8c169f3
JB		 9962018-03-22 Jan Beulich <jbeulich@suse.com>
997
998 * i386-opc.tbl: Drop VecESize from register only insn forms and
999 memory forms not allowing broadcast.
1000 * i386-tlb.h: Re-generate.
1001
96bc132a
JB		 10022018-03-22 Jan Beulich <jbeulich@suse.com>
1003
1004 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1005 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1006 sha256*): Drop Disp<N>.
1007
9f79e886
JB		 10082018-03-22 Jan Beulich <jbeulich@suse.com>
1009
1010 * i386-dis.c (EbndS, bnd_swap_mode): New.
1011 (prefix_table): Use EbndS.
1012 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1013 * i386-opc.tbl (bndmov): Move misplaced Load.
1014 * i386-tlb.h: Re-generate.
1015
d6793fa1
JB		 10162018-03-22 Jan Beulich <jbeulich@suse.com>
1017
1018 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1019 templates allowing memory operands and folded ones for register
1020 only flavors.
1021 * i386-tlb.h: Re-generate.
1022
f7768225
JB		 10232018-03-22 Jan Beulich <jbeulich@suse.com>
1024
1025 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1026 256-bit templates. Drop redundant leftover Disp<N>.
1027 * i386-tlb.h: Re-generate.
1028
0e35537d
JW		 10292018-03-14 Kito Cheng <kito.cheng@gmail.com>
1030
1031 * riscv-opc.c (riscv_insn_types): New.
1032
b4a3689a
NC		 10332018-03-13 Nick Clifton <nickc@redhat.com>
1034
1035 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1036
d3d50934
L		 10372018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1038
1039 * i386-opc.tbl: Add Optimize to clr.
1040 * i386-tbl.h: Regenerated.
1041
bd5dea88
L		 10422018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1043
1044 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1045 * i386-opc.h (OldGcc): Removed.
1046 (i386_opcode_modifier): Remove oldgcc.
1047 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1048 instructions for old (<= 2.8.1) versions of gcc.
1049 * i386-tbl.h: Regenerated.
1050
e771e7c9
JB		 10512018-03-08 Jan Beulich <jbeulich@suse.com>
1052
1053 * i386-opc.h (EVEXDYN): New.
1054 * i386-opc.tbl: Fold various AVX512VL templates.
1055 * i386-tlb.h: Re-generate.
1056
ed438a93
JB		 10572018-03-08 Jan Beulich <jbeulich@suse.com>
1058
1059 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1060 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1061 vpexpandd, vpexpandq): Fold AFX512VF templates.
1062 * i386-tlb.h: Re-generate.
1063
454172a9
JB		 10642018-03-08 Jan Beulich <jbeulich@suse.com>
1065
1066 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1067 Fold 128- and 256-bit VEX-encoded templates.
1068 * i386-tlb.h: Re-generate.
1069
36824150
JB		 10702018-03-08 Jan Beulich <jbeulich@suse.com>
1071
1072 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1073 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1074 vpexpandd, vpexpandq): Fold AVX512F templates.
1075 * i386-tlb.h: Re-generate.
1076
e7f5c0a9
JB		 10772018-03-08 Jan Beulich <jbeulich@suse.com>
1078
1079 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1080 64-bit templates. Drop Disp<N>.
1081 * i386-tlb.h: Re-generate.
1082
25a4277f
JB		 10832018-03-08 Jan Beulich <jbeulich@suse.com>
1084
1085 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1086 and 256-bit templates.
1087 * i386-tlb.h: Re-generate.
1088
d2224064
JB		 10892018-03-08 Jan Beulich <jbeulich@suse.com>
1090
1091 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1092 * i386-tlb.h: Re-generate.
1093
1b193f0b
JB		 10942018-03-08 Jan Beulich <jbeulich@suse.com>
1095
1096 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1097 Drop NoAVX.
1098 * i386-tlb.h: Re-generate.
1099
f2f6a710
JB		 11002018-03-08 Jan Beulich <jbeulich@suse.com>
1101
1102 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1103 * i386-tlb.h: Re-generate.
1104
38e314eb
JB		 11052018-03-08 Jan Beulich <jbeulich@suse.com>
1106
1107 * i386-gen.c (opcode_modifiers): Delete FloatD.
1108 * i386-opc.h (FloatD): Delete.
1109 (struct i386_opcode_modifier): Delete floatd.
1110 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1111 FloatD by D.
1112 * i386-tlb.h: Re-generate.
1113
d53e6b98
JB		 11142018-03-08 Jan Beulich <jbeulich@suse.com>
1115
1116 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1117
2907c2f5
JB		 11182018-03-08 Jan Beulich <jbeulich@suse.com>
1119
1120 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1121 * i386-tlb.h: Re-generate.
1122
73053c1f
JB		 11232018-03-08 Jan Beulich <jbeulich@suse.com>
1124
1125 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1126 forms.
1127 * i386-tlb.h: Re-generate.
1128
52fe4420
AM		 11292018-03-07 Alan Modra <amodra@gmail.com>
1130
1131 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1132 bfd_arch_rs6000.
1133 * disassemble.h (print_insn_rs6000): Delete.
1134 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1135 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1136 (print_insn_rs6000): Delete.
1137
a6743a54
AM		 11382018-03-03 Alan Modra <amodra@gmail.com>
1139
1140 * sysdep.h (opcodes_error_handler): Define.
1141 (_bfd_error_handler): Declare.
1142 * Makefile.am: Remove stray #.
1143 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1144 EDIT" comment.
1145 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1146 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1147 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1148 opcodes_error_handler to print errors. Standardize error messages.
1149 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1150 and include opintl.h.
1151 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1152 * i386-gen.c: Standardize error messages.
1153 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1154 * Makefile.in: Regenerate.
1155 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1156 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1157 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1158 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1159 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1160 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1161 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1162 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1163 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1164 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1165 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1166 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1167 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1168
8305403a
L		 11692018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1170
1171 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1172 vpsub[bwdq] instructions.
1173 * i386-tbl.h: Regenerated.
1174
e184813f
AM		 11752018-03-01 Alan Modra <amodra@gmail.com>
1176
1177 * configure.ac (ALL_LINGUAS): Sort.
1178 * configure: Regenerate.
1179
5b616bef
TP		 11802018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1181
1182 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1183 macro by assignements.
1184
b6f8c7c4
L		 11852018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1186
1187 PR gas/22871
1188 * i386-gen.c (opcode_modifiers): Add Optimize.
1189 * i386-opc.h (Optimize): New enum.
1190 (i386_opcode_modifier): Add optimize.
1191 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1192 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1193 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1194 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1195 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1196 vpxord and vpxorq.
1197 * i386-tbl.h: Regenerated.
1198
e95b887f
AM		 11992018-02-26 Alan Modra <amodra@gmail.com>
1200
1201 * crx-dis.c (getregliststring): Allocate a large enough buffer
1202 to silence false positive gcc8 warning.
1203
0bccfb29
JW		 12042018-02-22 Shea Levy <shea@shealevy.com>
1205
1206 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1207
6b6b6807
L		 12082018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1209
1210 * i386-opc.tbl: Add {rex},
1211 * i386-tbl.h: Regenerated.
1212
75f31665
MR		 12132018-02-20 Maciej W. Rozycki <macro@mips.com>
1214
1215 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1216 (mips16_opcodes): Replace `M' with `m' for "restore".
1217
e207bc53
TP		 12182018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1219
1220 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1221
87993319
MR		 12222018-02-13 Maciej W. Rozycki <macro@mips.com>
1223
1224 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1225 variable to `function_index'.
1226
68d20676
NC		 12272018-02-13 Nick Clifton <nickc@redhat.com>
1228
1229 PR 22823
1230 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1231 about truncation of printing.
1232
d2159fdc
HW		 12332018-02-12 Henry Wong <henry@stuffedcow.net>
1234
1235 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1236
f174ef9f
NC		 12372018-02-05 Nick Clifton <nickc@redhat.com>
1238
1239 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1240
be3a8dca
IT		 12412018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1242
1243 * i386-dis.c (enum): Add pconfig.
1244 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1245 (cpu_flags): Add CpuPCONFIG.
1246 * i386-opc.h (enum): Add CpuPCONFIG.
1247 (i386_cpu_flags): Add cpupconfig.
1248 * i386-opc.tbl: Add PCONFIG instruction.
1249 * i386-init.h: Regenerate.
1250 * i386-tbl.h: Likewise.
1251
3233d7d0
IT		 12522018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1253
1254 * i386-dis.c (enum): Add PREFIX_0F09.
1255 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1256 (cpu_flags): Add CpuWBNOINVD.
1257 * i386-opc.h (enum): Add CpuWBNOINVD.
1258 (i386_cpu_flags): Add cpuwbnoinvd.
1259 * i386-opc.tbl: Add WBNOINVD instruction.
1260 * i386-init.h: Regenerate.
1261 * i386-tbl.h: Likewise.
1262
e925c834
JW		 12632018-01-17 Jim Wilson <jimw@sifive.com>
1264
1265 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1266
d777820b
IT		 12672018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1268
1269 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1270 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1271 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1272 (cpu_flags): Add CpuIBT, CpuSHSTK.
1273 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1274 (i386_cpu_flags): Add cpuibt, cpushstk.
1275 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1276 * i386-init.h: Regenerate.
1277 * i386-tbl.h: Likewise.
1278
f6efed01
NC		 12792018-01-16 Nick Clifton <nickc@redhat.com>
1280
1281 * po/pt_BR.po: Updated Brazilian Portugese translation.
1282 * po/de.po: Updated German translation.
1283
2721d702
JW		 12842018-01-15 Jim Wilson <jimw@sifive.com>
1285
1286 * riscv-opc.c (match_c_nop): New.
1287 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1288
616dcb87
NC		 12892018-01-15 Nick Clifton <nickc@redhat.com>
1290
1291 * po/uk.po: Updated Ukranian translation.
1292
3957a496
NC		 12932018-01-13 Nick Clifton <nickc@redhat.com>
1294
1295 * po/opcodes.pot: Regenerated.
1296
769c7ea5
NC		 12972018-01-13 Nick Clifton <nickc@redhat.com>
1298
1299 * configure: Regenerate.
1300
faf766e3
NC		 13012018-01-13 Nick Clifton <nickc@redhat.com>
1302
1303 2.30 branch created.
1304
888a89da
IT		 13052018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1306
1307 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1308 * i386-tbl.h: Regenerate.
1309
cbda583a
JB		 13102018-01-10 Jan Beulich <jbeulich@suse.com>
1311
1312 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1313 * i386-tbl.h: Re-generate.
1314
c9e92278
JB		 13152018-01-10 Jan Beulich <jbeulich@suse.com>
1316
1317 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1318 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1319 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1320 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1321 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1322 Disp8MemShift of AVX512VL forms.
1323 * i386-tbl.h: Re-generate.
1324
35fd2b2b
JW		 13252018-01-09 Jim Wilson <jimw@sifive.com>
1326
1327 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1328 then the hi_addr value is zero.
1329
91d8b670
JG		 13302018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1331
1332 * arm-dis.c (arm_opcodes): Add csdb.
1333 (thumb32_opcodes): Add csdb.
1334
be2e7d95
JG		 13352018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1336
1337 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1338 * aarch64-asm-2.c: Regenerate.
1339 * aarch64-dis-2.c: Regenerate.
1340 * aarch64-opc-2.c: Regenerate.
1341
704a705d
L		 13422018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1343
1344 PR gas/22681
1345 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1346 Remove AVX512 vmovd with 64-bit operands.
1347 * i386-tbl.h: Regenerated.
1348
35eeb78f
JW		 13492018-01-05 Jim Wilson <jimw@sifive.com>
1350
1351 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1352 jalr.
1353
219d1afa
AM		 13542018-01-03 Alan Modra <amodra@gmail.com>
1355
1356 Update year range in copyright notice of all files.
1357
1508bbf5
JB		 13582018-01-02 Jan Beulich <jbeulich@suse.com>
1359
1360 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1361 and OPERAND_TYPE_REGZMM entries.
1362
1e563868 1363For older changes see ChangeLog-2017
3499769a 1364\f
1e563868 1365Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1366
1367Copying and distribution of this file, with or without modification,
1368are permitted in any medium without royalty provided the copyright
1369notice and this notice are preserved.
1370
1371Local Variables:
1372mode: change-log
1373left-margin: 8
1374fill-column: 74
1375version-control: never
1376End:
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