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* elf-m10300.c (elf32_mn10300_link_hash_entry): Add value.
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
777b13b9
RS
12006-07-29 Richard Sandiford <richard@codesourcery.com>
2
3 * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
4 "fdaddl" entry.
5
401a54cf
PB
62006-07-19 Paul Brook <paul@codesourcery.com>
7
8 * armd-dis.c (arm_opcodes): Fix rbit opcode.
9
2b516b72
L
102006-07-18 H.J. Lu <hongjiu.lu@intel.com>
11
12 * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
13 "sldt", "str" and "smsw".
14
10505f38
L
152006-07-15 H.J. Lu <hongjiu.lu@intel.com>
16
17 PR binutils/2829
18 * i386-dis.c (GRP11_C6): NEW.
19 (GRP11_C7): Likewise.
20 (GRP12): Updated.
21 (GRP13): Likewise.
22 (GRP14): Likewise.
23 (GRP15): Likewise.
24 (GRP16): Likewise.
25 (GRPAMD): Likewise.
26 (GRPPADLCK1): Likewise.
27 (GRPPADLCK2): Likewise.
28 (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
29 respectively.
30 (grps): Add entries for GRP11_C6 and GRP11_C7.
31
050dfa73
MM
322006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
33 Michael Meissner <michael.meissner@amd.com>
34
35 * i386-dis.c (dis386): Add support for 4 operand instructions. Add
36 support for amdfam10 SSE4a/ABM instructions. Modify all
37 initializer macros to have additional arguments. Disallow REP
38 prefix for non-string instructions.
39 (print_insn): Ditto.
40
41
e8b42ce4
JB
422006-07-05 Julian Brown <julian@codesourcery.com>
43
44 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
45
15965411
L
462006-06-12 H.J. Lu <hongjiu.lu@intel.com>
47
48 * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
49 (twobyte_has_modrm): Set 1 for 0x1f.
50
46e883c5
L
512006-06-12 H.J. Lu <hongjiu.lu@intel.com>
52
53 * i386-dis.c (NOP_Fixup): Removed.
54 (NOP_Fixup1): New.
55 (NOP_Fixup2): Likewise.
56 (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
57
4e9d3b81
JB
582006-06-12 Julian Brown <julian@codesourcery.com>
59
60 * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
61 on 64-bit hosts.
62
b3882df9
L
632006-06-10 H.J. Lu <hongjiu.lu@intel.com>
64
65 * i386.c (GRP10): Renamed to ...
66 (GRP12): This.
67 (GRP11): Renamed to ...
68 (GRP13): This.
69 (GRP12): Renamed to ...
70 (GRP14): This.
71 (GRP13): Renamed to ...
72 (GRP15): This.
73 (GRP14): Renamed to ...
74 (GRP16): This.
75 (dis386_twobyte): Updated.
76 (grps): Likewise.
77
5f4df3dd
NC
782006-06-09 Nick Clifton <nickc@redhat.com>
79
80 * po/fi.po: Updated Finnish translation.
81
6648b7cf
JM
822006-06-07 Joseph S. Myers <joseph@codesourcery.com>
83
84 * po/Make-in (pdf, ps): New dummy targets.
85
c22aaad1
PB
862006-06-06 Paul Brook <paul@codesourcery.com>
87
88 * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
89 instructions.
90 (neon_opcodes): Add conditional execution specifiers.
91 (thumb_opcodes): Ditto.
92 (thumb32_opcodes): Ditto.
93 (arm_conditional): Change 0xe to "al" and add "" to end.
94 (ifthen_state, ifthen_next_state, ifthen_address): New.
95 (IFTHEN_COND): Define.
96 (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
97 (print_insn_arm): Change %c to use new values of arm_conditional.
98 (print_insn_thumb16): Print thumb conditions. Add %I.
99 (print_insn_thumb32): Print thumb conditions.
100 (find_ifthen_state): New function.
101 (print_insn): Track IT block state.
102
9622b051
AM
1032006-06-06 Ben Elliston <bje@au.ibm.com>
104 Anton Blanchard <anton@samba.org>
105 Peter Bergner <bergner@vnet.ibm.com>
106
107 * ppc-dis.c (powerpc_dialect): Handle power6 option.
108 (print_ppc_disassembler_options): Mention power6.
109
65263ce3
TS
1102006-06-06 Thiemo Seufer <ths@mips.com>
111 Chao-ying Fu <fu@mips.com>
112
113 * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
114 * mips-opc.c: Add DSP64 instructions.
115
92ce91bb
AM
1162006-06-06 Alan Modra <amodra@bigpond.net.au>
117
118 * m68hc11-dis.c (print_insn): Warning fix.
119
4cfe2c59
DJ
1202006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
121
122 * po/Make-in (top_builddir): Define.
123
7ff1a5b5
AM
1242006-06-05 Alan Modra <amodra@bigpond.net.au>
125
126 * Makefile.am: Run "make dep-am".
127 * Makefile.in: Regenerate.
128 * config.in: Regenerate.
129
20e95c23
DJ
1302006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
131
132 * Makefile.am (INCLUDES): Use @INCINTL@.
133 * acinclude.m4: Include new gettext macros.
134 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
135 Remove local code for po/Makefile.
136 * Makefile.in, aclocal.m4, configure: Regenerated.
137
eebf07fb
NC
1382006-05-30 Nick Clifton <nickc@redhat.com>
139
140 * po/es.po: Updated Spanish translation.
141
a596001e
RS
1422006-05-25 Richard Sandiford <richard@codesourcery.com>
143
144 * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
145 and fmovem entries. Put register list entries before immediate
146 mask entries. Use "l" rather than "L" in the fmovem entries.
147 * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
148 out from INFO.
149 (m68k_scan_mask): New function, split out from...
150 (print_insn_m68k): ...here. If no architecture has been set,
151 first try printing an m680x0 instruction, then try a Coldfire one.
152
4a4d496a
NC
1532006-05-24 Nick Clifton <nickc@redhat.com>
154
155 * po/ga.po: Updated Irish translation.
156
a854efa3
NC
1572006-05-22 Nick Clifton <nickc@redhat.com>
158
159 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
160
0bd79061
NC
1612006-05-22 Nick Clifton <nickc@redhat.com>
162
163 * po/nl.po: Updated translation.
164
00988f49
AM
1652006-05-18 Alan Modra <amodra@bigpond.net.au>
166
167 * avr-dis.c: Formatting fix.
168
9b3f89ee
TS
1692006-05-14 Thiemo Seufer <ths@mips.com>
170
171 * mips16-opc.c (I1, I32, I64): New shortcut defines.
172 (mips16_opcodes): Change membership of instructions to their
173 lowest baseline ISA.
174
cb6d3433
L
1752006-05-09 H.J. Lu <hongjiu.lu@intel.com>
176
177 * i386-dis.c (grps): Update sgdt/sidt for 64bit.
178
1f3c39b9
JB
1792006-05-05 Julian Brown <julian@codesourcery.com>
180
181 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
182 vldm/vstm.
183
d43b4baf
TS
1842006-05-05 Thiemo Seufer <ths@mips.com>
185 David Ung <davidu@mips.com>
186
187 * mips-opc.c: Add macro for cache instruction.
188
39a7806d
TS
1892006-05-04 Thiemo Seufer <ths@mips.com>
190 Nigel Stephens <nigel@mips.com>
191 David Ung <davidu@mips.com>
192
193 * mips-dis.c (mips_arch_choices): Add smartmips instruction
194 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
195 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
196 MIPS64R2.
197 * mips-opc.c: fix random typos in comments.
198 (INSN_SMARTMIPS): New defines.
199 (mips_builtin_opcodes): Add paired single support for MIPS32R2.
200 Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
201 flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
202 FP_S and FP_D flags to denote single and double register
203 accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
204 Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
205 for MIPS32R2. Add SmartMIPS instructions. Add two-argument
206 variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
207 release 2 ISAs.
208 * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
209
104b4fab
TS
2102006-05-03 Thiemo Seufer <ths@mips.com>
211
212 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
213
022fac6d
TS
2142006-05-02 Thiemo Seufer <ths@mips.com>
215 Nigel Stephens <nigel@mips.com>
216 David Ung <davidu@mips.com>
217
218 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
219 (print_mips16_insn_arg): Force mips16 to odd addresses.
220
9bcd4f99
TS
2212006-04-30 Thiemo Seufer <ths@mips.com>
222 David Ung <davidu@mips.com>
223
224 * mips-opc.c (mips_builtin_opcodes): Add udi instructions
225 "udi0" to "udi15".
226 * mips-dis.c (print_insn_args): Adds udi argument handling.
227
f095b97b
JW
2282006-04-28 James E Wilson <wilson@specifix.com>
229
230 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
231 error message.
232
59c455b3
TS
2332006-04-28 Thiemo Seufer <ths@mips.com>
234 David Ung <davidu@mips.com>
bdb09db1 235 Nigel Stephens <nigel@mips.com>
59c455b3
TS
236
237 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
238 names.
239
cc0ca239 2402006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1 241 Nigel Stephens <nigel@mips.com>
cc0ca239
TS
242 David Ung <davidu@mips.com>
243
244 * mips-dis.c (print_insn_args): Add mips_opcode argument.
245 (print_insn_mips): Adjust print_insn_args call.
246
0d09bfe6 2472006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1 248 Nigel Stephens <nigel@mips.com>
0d09bfe6
TS
249
250 * mips-dis.c (print_insn_args): Print $fcc only for FP
251 instructions, use $cc elsewise.
252
654c225a 2532006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1 254 Nigel Stephens <nigel@mips.com>
654c225a
TS
255
256 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
257 Map MIPS16 registers to O32 names.
258 (print_mips16_insn_arg): Use mips16_reg_names.
259
0dbde4cf
JB
2602006-04-26 Julian Brown <julian@codesourcery.com>
261
262 * arm-dis.c (print_insn_neon): Disassemble floating-point constant
263 VMOV.
264
16980d0b
JB
2652006-04-26 Nathan Sidwell <nathan@codesourcery.com>
266 Julian Brown <julian@codesourcery.com>
267
268 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
269 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
270 Add unified load/store instruction names.
271 (neon_opcode_table): New.
272 (arm_opcodes): Expand meaning of %<bitfield>['`?].
273 (arm_decode_bitfield): New.
274 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
275 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
276 (print_insn_neon): New.
277 (print_insn_arm): Adjust print_insn_coprocessor call. Call
278 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
279 (print_insn_thumb32): Likewise.
280
ec3fcc56
AM
2812006-04-19 Alan Modra <amodra@bigpond.net.au>
282
283 * Makefile.am: Run "make dep-am".
284 * Makefile.in: Regenerate.
285
241a6c40
AM
2862006-04-19 Alan Modra <amodra@bigpond.net.au>
287
7c6646cd
AM
288 * avr-dis.c (avr_operand): Warning fix.
289
241a6c40
AM
290 * configure: Regenerate.
291
e7403566
DJ
2922006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
293
294 * po/POTFILES.in: Regenerated.
295
52f16a0e
NC
2962006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
297
298 PR binutils/2454
299 * avr-dis.c (avr_operand): Arrange for a comment to appear before
300 the symolic form of an address, so that the output of objdump -d
301 can be reassembled.
302
e78efa90
DD
3032006-04-10 DJ Delorie <dj@redhat.com>
304
305 * m32c-asm.c: Regenerate.
306
108a6f8e
CD
3072006-04-06 Carlos O'Donell <carlos@codesourcery.com>
308
309 * Makefile.am: Add install-html target.
310 * Makefile.in: Regenerate.
311
a135cb2c
NC
3122006-04-06 Nick Clifton <nickc@redhat.com>
313
314 * po/vi/po: Updated Vietnamese translation.
315
47426b41
AM
3162006-03-31 Paul Koning <ni1d@arrl.net>
317
318 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
319
331f1cbe
BS
3202006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
321
322 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
323 logic to identify halfword shifts.
324
c16d2bf0
PB
3252006-03-16 Paul Brook <paul@codesourcery.com>
326
327 * arm-dis.c (arm_opcodes): Rename swi to svc.
328 (thumb_opcodes): Ditto.
329
5348b81e
DD
3302006-03-13 DJ Delorie <dj@redhat.com>
331
5398310a
DD
332 * m32c-asm.c: Regenerate.
333 * m32c-desc.c: Likewise.
334 * m32c-desc.h: Likewise.
335 * m32c-dis.c: Likewise.
336 * m32c-ibld.c: Likewise.
5348b81e
DD
337 * m32c-opc.c: Likewise.
338 * m32c-opc.h: Likewise.
339
253d272c
DD
3402006-03-10 DJ Delorie <dj@redhat.com>
341
342 * m32c-desc.c: Regenerate with mul.l, mulu.l.
343 * m32c-opc.c: Likewise.
344 * m32c-opc.h: Likewise.
345
346
f530741d
NC
3472006-03-09 Nick Clifton <nickc@redhat.com>
348
349 * po/sv.po: Updated Swedish translation.
350
35c52694
L
3512006-03-07 H.J. Lu <hongjiu.lu@intel.com>
352
353 PR binutils/2428
354 * i386-dis.c (REP_Fixup): New function.
355 (AL): Remove duplicate.
356 (Xbr): New.
357 (Xvr): Likewise.
358 (Ybr): Likewise.
359 (Yvr): Likewise.
360 (indirDXr): Likewise.
361 (ALr): Likewise.
362 (eAXr): Likewise.
363 (dis386): Updated entries of ins, outs, movs, lods and stos.
364
ed963e2d
NC
3652006-03-05 Nick Clifton <nickc@redhat.com>
366
367 * cgen-ibld.in (insert_normal): Cope with attempts to insert a
368 signed 32-bit value into an unsigned 32-bit field when the host is
369 a 64-bit machine.
370 * fr30-ibld.c: Regenerate.
371 * frv-ibld.c: Regenerate.
372 * ip2k-ibld.c: Regenerate.
373 * iq2000-asm.c: Regenerate.
374 * iq2000-ibld.c: Regenerate.
375 * m32c-ibld.c: Regenerate.
376 * m32r-ibld.c: Regenerate.
377 * openrisc-ibld.c: Regenerate.
378 * xc16x-ibld.c: Regenerate.
379 * xstormy16-ibld.c: Regenerate.
380
c7d41dc5
NC
3812006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
382
383 * xc16x-asm.c: Regenerate.
384 * xc16x-dis.c: Regenerate.
c7d41dc5 385
f7d9e5c3
CD
3862006-02-27 Carlos O'Donell <carlos@codesourcery.com>
387
388 * po/Make-in: Add html target.
389
331d2d0d
L
3902006-02-27 H.J. Lu <hongjiu.lu@intel.com>
391
392 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
393 Intel Merom New Instructions.
394 (THREE_BYTE_0): Likewise.
395 (THREE_BYTE_1): Likewise.
396 (three_byte_table): Likewise.
397 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
398 THREE_BYTE_1 for entry 0x3a.
399 (twobyte_has_modrm): Updated.
400 (twobyte_uses_SSE_prefix): Likewise.
401 (print_insn): Handle 3-byte opcodes used by Intel Merom New
402 Instructions.
403
ff3f9d5b
DM
4042006-02-24 David S. Miller <davem@sunset.davemloft.net>
405
406 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
407 (v9_hpriv_reg_names): New table.
408 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
409 New cases '$' and '%' for read/write hyperprivileged register.
410 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
411 window handling and rdhpr/wrhpr instructions.
412
6772dd07
DD
4132006-02-24 DJ Delorie <dj@redhat.com>
414
415 * m32c-desc.c: Regenerate with linker relaxation attributes.
416 * m32c-desc.h: Likewise.
417 * m32c-dis.c: Likewise.
418 * m32c-opc.c: Likewise.
419
62b3e311
PB
4202006-02-24 Paul Brook <paul@codesourcery.com>
421
422 * arm-dis.c (arm_opcodes): Add V7 instructions.
423 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
424 (print_arm_address): New function.
425 (print_insn_arm): Use it. Add 'P' and 'U' cases.
426 (psr_name): New function.
427 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
428
59cf82fe
L
4292006-02-23 H.J. Lu <hongjiu.lu@intel.com>
430
431 * ia64-opc-i.c (bXc): New.
432 (mXc): Likewise.
433 (OpX2TaTbYaXcC): Likewise.
434 (TF). Likewise.
435 (TFCM). Likewise.
436 (ia64_opcodes_i): Add instructions for tf.
437
438 * ia64-opc.h (IMMU5b): New.
439
440 * ia64-asmtab.c: Regenerated.
441
19a7219f
L
4422006-02-23 H.J. Lu <hongjiu.lu@intel.com>
443
444 * ia64-gen.c: Update copyright years.
445 * ia64-opc-b.c: Likewise.
446
7f3dfb9c
L
4472006-02-22 H.J. Lu <hongjiu.lu@intel.com>
448
449 * ia64-gen.c (lookup_regindex): Handle ".vm".
450 (print_dependency_table): Handle '\"'.
451
452 * ia64-ic.tbl: Updated from SDM 2.2.
453 * ia64-raw.tbl: Likewise.
454 * ia64-waw.tbl: Likewise.
455 * ia64-asmtab.c: Regenerated.
456
457 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
458
d70c5fc7
NC
4592006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
460 Anil Paranjape <anilp1@kpitcummins.com>
461 Shilin Shakti <shilins@kpitcummins.com>
462
463 * xc16x-desc.h: New file
464 * xc16x-desc.c: New file
465 * xc16x-opc.h: New file
466 * xc16x-opc.c: New file
467 * xc16x-ibld.c: New file
468 * xc16x-asm.c: New file
469 * xc16x-dis.c: New file
470 * Makefile.am: Entries for xc16x
471 * Makefile.in: Regenerate
472 * cofigure.in: Add xc16x target information.
473 * configure: Regenerate.
474 * disassemble.c: Add xc16x target information.
475
a1cfb73e
L
4762006-02-11 H.J. Lu <hongjiu.lu@intel.com>
477
478 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
479 moves.
480
6dd5059a
L
4812006-02-11 H.J. Lu <hongjiu.lu@intel.com>
482
483 * i386-dis.c ('Z'): Add a new macro.
484 (dis386_twobyte): Use "movZ" for control register moves.
485
8536c657
NC
4862006-02-10 Nick Clifton <nickc@redhat.com>
487
488 * iq2000-asm.c: Regenerate.
489
266abb8f
NS
4902006-02-07 Nathan Sidwell <nathan@codesourcery.com>
491
492 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
493
f1a64f49
DU
4942006-01-26 David Ung <davidu@mips.com>
495
496 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
497 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
498 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
499 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
500 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
501
9e919b5f
AM
5022006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
503
504 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
505 ld_d_r, pref_xd_cb): Use signed char to hold data to be
506 disassembled.
507 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
508 buffer overflows when disassembling instructions like
509 ld (ix+123),0x23
510 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
511 operand, if the offset is negative.
512
c9021189
AM
5132006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
514
515 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
516 unsigned char to hold data to be disassembled.
517
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5182006-01-17 Andreas Schwab <schwab@suse.de>
519
520 PR binutils/1486
521 * disassemble.c (disassemble_init_for_target): Set
522 disassembler_needs_relocs for bfd_arch_arm.
523
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5242006-01-16 Paul Brook <paul@codesourcery.com>
525
e88d958a 526 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
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527 f?add?, and f?sub? instructions.
528
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5292006-01-16 Nick Clifton <nickc@redhat.com>
530
531 * po/zh_CN.po: New Chinese (simplified) translation.
532 * configure.in (ALL_LINGUAS): Add "zh_CH".
533 * configure: Regenerate.
534
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5352006-01-05 Paul Brook <paul@codesourcery.com>
536
537 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
538
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5392006-01-06 DJ Delorie <dj@redhat.com>
540
541 * m32c-desc.c: Regenerate.
542 * m32c-opc.c: Regenerate.
543 * m32c-opc.h: Regenerate.
544
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5452006-01-03 DJ Delorie <dj@redhat.com>
546
547 * cgen-ibld.in (extract_normal): Avoid memory range errors.
548 * m32c-ibld.c: Regenerated.
549
e88d958a 550For older changes see ChangeLog-2005
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551\f
552Local Variables:
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553mode: change-log
554left-margin: 8
555fill-column: 74
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556version-control: never
557End: