projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| a06ea964 NC |
1 | /* aarch64-tbl.h -- AArch64 opcode description table and instruction |
| 2 | operand description table. | |
| 82704155 | 3 | Copyright (C) 2012-2019 Free Software Foundation, Inc. |
| a06ea964 NC |
4 | |
| 5 | This file is part of the GNU opcodes library. | |
| 6 | ||
| 7 | This library is free software; you can redistribute it and/or modify | |
| 8 | it under the terms of the GNU General Public License as published by | |
| 9 | the Free Software Foundation; either version 3, or (at your option) | |
| 10 | any later version. | |
| 11 | ||
| 12 | It is distributed in the hope that it will be useful, but WITHOUT | |
| 13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 15 | License for more details. | |
| 16 | ||
| 17 | You should have received a copy of the GNU General Public License | |
| 18 | along with this file; see the file COPYING. If not, write to the | |
| 19 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
| 20 | MA 02110-1301, USA. */ | |
| 21 | ||
| 22 | #include "aarch64-opc.h" | |
| 23 | ||
| 20f55f38 SN |
24 | #ifndef VERIFIER |
| 25 | #error VERIFIER must be defined. | |
| 26 | #endif | |
| 27 | ||
| a06ea964 NC |
28 | /* Operand type. */ |
| 29 | ||
| 30 | #define OPND(x) AARCH64_OPND_##x | |
| 31 | #define OP0() {} | |
| 32 | #define OP1(a) {OPND(a)} | |
| 33 | #define OP2(a,b) {OPND(a), OPND(b)} | |
| 34 | #define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)} | |
| 35 | #define OP4(a,b,c,d) {OPND(a), OPND(b), OPND(c), OPND(d)} | |
| 36 | #define OP5(a,b,c,d,e) {OPND(a), OPND(b), OPND(c), OPND(d), OPND(e)} | |
| 37 | ||
| 38 | #define QLF(x) AARCH64_OPND_QLF_##x | |
| 39 | #define QLF1(a) {QLF(a)} | |
| 40 | #define QLF2(a,b) {QLF(a), QLF(b)} | |
| 41 | #define QLF3(a,b,c) {QLF(a), QLF(b), QLF(c)} | |
| 42 | #define QLF4(a,b,c,d) {QLF(a), QLF(b), QLF(c), QLF(d)} | |
| 43 | #define QLF5(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e)} | |
| 44 | ||
| 45 | /* Qualifiers list. */ | |
| 46 | ||
| 47 | /* e.g. MSR <systemreg>, <Xt>. */ | |
| 48 | #define QL_SRC_X \ | |
| 49 | { \ | |
| 50 | QLF2(NIL,X), \ | |
| 51 | } | |
| 52 | ||
| 53 | /* e.g. MRS <Xt>, <systemreg>. */ | |
| 54 | #define QL_DST_X \ | |
| 55 | { \ | |
| 56 | QLF2(X,NIL), \ | |
| 57 | } | |
| 58 | ||
| 59 | /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */ | |
| 60 | #define QL_SYS \ | |
| 61 | { \ | |
| a6a51754 | 62 | QLF5(NIL,CR,CR,NIL,X), \ |
| a06ea964 NC |
63 | } |
| 64 | ||
| 65 | /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */ | |
| 66 | #define QL_SYSL \ | |
| 67 | { \ | |
| a6a51754 | 68 | QLF5(X,NIL,CR,CR,NIL), \ |
| a06ea964 NC |
69 | } |
| 70 | ||
| 71 | /* e.g. ADRP <Xd>, <label>. */ | |
| 72 | #define QL_ADRP \ | |
| 73 | { \ | |
| 74 | QLF2(X,NIL), \ | |
| 75 | } | |
| 76 | ||
| b83b4b13 SD |
77 | /* e.g. TCANCEL #<imm>. */ |
| 78 | #define QL_IMM_NIL \ | |
| 79 | { \ | |
| 80 | QLF1(NIL), \ | |
| 81 | } | |
| 82 | ||
| a06ea964 NC |
83 | /* e.g. B.<cond> <label>. */ |
| 84 | #define QL_PCREL_NIL \ | |
| 85 | { \ | |
| 86 | QLF1(NIL), \ | |
| 87 | } | |
| 88 | ||
| 89 | /* e.g. TBZ <Xt>, #<imm>, <label>. */ | |
| 90 | #define QL_PCREL_14 \ | |
| 91 | { \ | |
| 92 | QLF3(X,imm_0_63,NIL), \ | |
| 93 | } | |
| 94 | ||
| 95 | /* e.g. BL <label>. */ | |
| 96 | #define QL_PCREL_26 \ | |
| 97 | { \ | |
| 98 | QLF1(NIL), \ | |
| 99 | } | |
| 100 | ||
| 101 | /* e.g. LDRSW <Xt>, <label>. */ | |
| 102 | #define QL_X_PCREL \ | |
| 103 | { \ | |
| 104 | QLF2(X,NIL), \ | |
| 105 | } | |
| 106 | ||
| 107 | /* e.g. LDR <Wt>, <label>. */ | |
| 108 | #define QL_R_PCREL \ | |
| 109 | { \ | |
| 110 | QLF2(W,NIL), \ | |
| 111 | QLF2(X,NIL), \ | |
| 112 | } | |
| 113 | ||
| 114 | /* e.g. LDR <Dt>, <label>. */ | |
| 115 | #define QL_FP_PCREL \ | |
| 116 | { \ | |
| 117 | QLF2(S_S,NIL), \ | |
| 118 | QLF2(S_D,NIL), \ | |
| 119 | QLF2(S_Q,NIL), \ | |
| 120 | } | |
| 121 | ||
| 122 | /* e.g. PRFM <prfop>, <label>. */ | |
| 123 | #define QL_PRFM_PCREL \ | |
| 124 | { \ | |
| 125 | QLF2(NIL,NIL), \ | |
| 126 | } | |
| 127 | ||
| 128 | /* e.g. BR <Xn>. */ | |
| 129 | #define QL_I1X \ | |
| 130 | { \ | |
| 131 | QLF1(X), \ | |
| 132 | } | |
| 133 | ||
| bd7ceb8d | 134 | /* e.g. STG <Xt|SP>, [<Xn|SP>, #<imm9>]. */ |
| fb3265b3 SD |
135 | #define QL_LDST_AT \ |
| 136 | { \ | |
| 69105ce4 | 137 | QLF2(X, imm_tag), \ |
| bd7ceb8d | 138 | QLF2(SP, imm_tag), \ |
| fb3265b3 SD |
139 | } |
| 140 | ||
| a06ea964 NC |
141 | /* e.g. RBIT <Wd>, <Wn>. */ |
| 142 | #define QL_I2SAME \ | |
| 143 | { \ | |
| 144 | QLF2(W,W), \ | |
| 145 | QLF2(X,X), \ | |
| 146 | } | |
| 147 | ||
| 148 | /* e.g. CMN <Wn|WSP>, <Wm>{, <extend> {#<amount>}}. */ | |
| 149 | #define QL_I2_EXT \ | |
| 150 | { \ | |
| 151 | QLF2(W,W), \ | |
| 152 | QLF2(X,W), \ | |
| 153 | QLF2(X,X), \ | |
| 154 | } | |
| 155 | ||
| 156 | /* e.g. MOV <Wd|WSP>, <Wn|WSP>, at least one SP. */ | |
| 157 | #define QL_I2SP \ | |
| 158 | { \ | |
| 159 | QLF2(WSP,W), \ | |
| 160 | QLF2(W,WSP), \ | |
| 161 | QLF2(SP,X), \ | |
| 162 | QLF2(X,SP), \ | |
| 163 | } | |
| 164 | ||
| 165 | /* e.g. REV <Wd>, <Wn>. */ | |
| 166 | #define QL_I2SAMEW \ | |
| 167 | { \ | |
| 168 | QLF2(W,W), \ | |
| 169 | } | |
| 170 | ||
| 171 | /* e.g. REV32 <Xd>, <Xn>. */ | |
| 172 | #define QL_I2SAMEX \ | |
| 173 | { \ | |
| 174 | QLF2(X,X), \ | |
| 175 | } | |
| 176 | ||
| 177 | #define QL_I2SAMER \ | |
| 178 | { \ | |
| 179 | QLF2(W,W), \ | |
| 180 | QLF2(X,X), \ | |
| 181 | } | |
| 182 | ||
| e60bb1dd YZ |
183 | /* e.g. CRC32B <Wd>, <Wn>, <Wm>. */ |
| 184 | #define QL_I3SAMEW \ | |
| 185 | { \ | |
| 186 | QLF3(W,W,W), \ | |
| 187 | } | |
| 188 | ||
| a06ea964 NC |
189 | /* e.g. SMULH <Xd>, <Xn>, <Xm>. */ |
| 190 | #define QL_I3SAMEX \ | |
| 191 | { \ | |
| 192 | QLF3(X,X,X), \ | |
| 193 | } | |
| 194 | ||
| e60bb1dd YZ |
195 | /* e.g. CRC32X <Wd>, <Wn>, <Xm>. */ |
| 196 | #define QL_I3WWX \ | |
| 197 | { \ | |
| 198 | QLF3(W,W,X), \ | |
| 199 | } | |
| 200 | ||
| a06ea964 NC |
201 | /* e.g. UDIV <Xd>, <Xn>, <Xm>. */ |
| 202 | #define QL_I3SAMER \ | |
| 203 | { \ | |
| 204 | QLF3(W,W,W), \ | |
| 205 | QLF3(X,X,X), \ | |
| 206 | } | |
| 207 | ||
| 208 | /* e.g. ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}. */ | |
| 209 | #define QL_I3_EXT \ | |
| 210 | { \ | |
| 211 | QLF3(W,W,W), \ | |
| 212 | QLF3(X,X,W), \ | |
| 213 | QLF3(X,X,X), \ | |
| 214 | } | |
| 215 | ||
| 216 | /* e.g. MADD <Xd>, <Xn>, <Xm>, <Xa>. */ | |
| 217 | #define QL_I4SAMER \ | |
| 218 | { \ | |
| 219 | QLF4(W,W,W,W), \ | |
| 220 | QLF4(X,X,X,X), \ | |
| 221 | } | |
| 222 | ||
| 223 | /* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */ | |
| 224 | #define QL_I3SAMEL \ | |
| 225 | { \ | |
| 226 | QLF3(X,W,W), \ | |
| 227 | } | |
| 228 | ||
| 229 | /* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */ | |
| 230 | #define QL_I4SAMEL \ | |
| 231 | { \ | |
| 232 | QLF4(X,W,W,X), \ | |
| 233 | } | |
| 234 | ||
| 235 | /* e.g. CSINC <Xd>, <Xn>, <Xm>, <cond>. */ | |
| 236 | #define QL_CSEL \ | |
| 237 | { \ | |
| 238 | QLF4(W, W, W, NIL), \ | |
| 239 | QLF4(X, X, X, NIL), \ | |
| 240 | } | |
| 241 | ||
| 242 | /* e.g. CSET <Wd>, <cond>. */ | |
| 243 | #define QL_DST_R \ | |
| 244 | { \ | |
| 245 | QLF2(W, NIL), \ | |
| 246 | QLF2(X, NIL), \ | |
| 247 | } | |
| 248 | ||
| 249 | /* e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>. */ | |
| 250 | #define QL_BF \ | |
| 251 | { \ | |
| 252 | QLF4(W,W,imm_0_31,imm_0_31), \ | |
| 253 | QLF4(X,X,imm_0_63,imm_0_63), \ | |
| 254 | } | |
| 255 | ||
| 193614f2 SD |
256 | /* e.g. ADDG <Xd>, <Xn>, #<uimm10>, #<uimm4>. */ |
| 257 | #define QL_ADDG \ | |
| 258 | { \ | |
| 259 | QLF4(X,X,NIL,imm_0_15), \ | |
| 260 | } \ | |
| 261 | ||
| d685192a MW |
262 | /* e.g. BFC <Wd>, #<immr>, #<imms>. */ |
| 263 | #define QL_BF1 \ | |
| 264 | { \ | |
| 265 | QLF3 (W, imm_0_31, imm_1_32), \ | |
| 266 | QLF3 (X, imm_0_63, imm_1_64), \ | |
| 267 | } | |
| 268 | ||
| a06ea964 NC |
269 | /* e.g. UBFIZ <Wd>, <Wn>, #<lsb>, #<width>. */ |
| 270 | #define QL_BF2 \ | |
| 271 | { \ | |
| 272 | QLF4(W,W,imm_0_31,imm_1_32), \ | |
| 273 | QLF4(X,X,imm_0_63,imm_1_64), \ | |
| 274 | } | |
| 275 | ||
| 276 | /* e.g. SCVTF <Sd>, <Xn>, #<fbits>. */ | |
| 277 | #define QL_FIX2FP \ | |
| 278 | { \ | |
| 279 | QLF3(S_D,W,imm_1_32), \ | |
| 280 | QLF3(S_S,W,imm_1_32), \ | |
| 281 | QLF3(S_D,X,imm_1_64), \ | |
| 282 | QLF3(S_S,X,imm_1_64), \ | |
| 283 | } | |
| 284 | ||
| 622b9eb1 MW |
285 | /* e.g. SCVTF <Hd>, <Xn>, #<fbits>. */ |
| 286 | #define QL_FIX2FP_H \ | |
| 287 | { \ | |
| 288 | QLF3 (S_H, W, imm_1_32), \ | |
| 289 | QLF3 (S_H, X, imm_1_64), \ | |
| 290 | } | |
| 291 | ||
| a06ea964 NC |
292 | /* e.g. FCVTZS <Wd>, <Dn>, #<fbits>. */ |
| 293 | #define QL_FP2FIX \ | |
| 294 | { \ | |
| 295 | QLF3(W,S_D,imm_1_32), \ | |
| 296 | QLF3(W,S_S,imm_1_32), \ | |
| 297 | QLF3(X,S_D,imm_1_64), \ | |
| 298 | QLF3(X,S_S,imm_1_64), \ | |
| 299 | } | |
| 300 | ||
| 622b9eb1 MW |
301 | /* e.g. FCVTZS <Wd>, <Hn>, #<fbits>. */ |
| 302 | #define QL_FP2FIX_H \ | |
| 303 | { \ | |
| 304 | QLF3 (W, S_H, imm_1_32), \ | |
| 305 | QLF3 (X, S_H, imm_1_64), \ | |
| 306 | } | |
| 307 | ||
| a06ea964 NC |
308 | /* e.g. SCVTF <Dd>, <Wn>. */ |
| 309 | #define QL_INT2FP \ | |
| 310 | { \ | |
| 311 | QLF2(S_D,W), \ | |
| 312 | QLF2(S_S,W), \ | |
| 313 | QLF2(S_D,X), \ | |
| 314 | QLF2(S_S,X), \ | |
| 315 | } | |
| 316 | ||
| cb366992 EB |
317 | /* e.g. FMOV <Dd>, <Xn>. */ |
| 318 | #define QL_INT2FP_FMOV \ | |
| 319 | { \ | |
| 320 | QLF2(S_S,W), \ | |
| 321 | QLF2(S_D,X), \ | |
| 322 | } | |
| 323 | ||
| 622b9eb1 MW |
324 | /* e.g. SCVTF <Hd>, <Wn>. */ |
| 325 | #define QL_INT2FP_H \ | |
| 326 | { \ | |
| 327 | QLF2 (S_H, W), \ | |
| 328 | QLF2 (S_H, X), \ | |
| 329 | } | |
| 330 | ||
| a06ea964 NC |
331 | /* e.g. FCVTNS <Xd>, <Dn>. */ |
| 332 | #define QL_FP2INT \ | |
| 333 | { \ | |
| 334 | QLF2(W,S_D), \ | |
| 335 | QLF2(W,S_S), \ | |
| 336 | QLF2(X,S_D), \ | |
| 337 | QLF2(X,S_S), \ | |
| 338 | } | |
| 339 | ||
| cb366992 EB |
340 | /* e.g. FMOV <Xd>, <Dn>. */ |
| 341 | #define QL_FP2INT_FMOV \ | |
| 342 | { \ | |
| 343 | QLF2(W,S_S), \ | |
| 344 | QLF2(X,S_D), \ | |
| 345 | } | |
| 346 | ||
| 622b9eb1 MW |
347 | /* e.g. FCVTNS <Hd>, <Wn>. */ |
| 348 | #define QL_FP2INT_H \ | |
| 349 | { \ | |
| 350 | QLF2 (W, S_H), \ | |
| 351 | QLF2 (X, S_H), \ | |
| 352 | } | |
| 353 | ||
| ccfc90a3 SN |
354 | /* e.g. FJCVTZS <Wd>, <Dn>. */ |
| 355 | #define QL_FP2INT_W_D \ | |
| 356 | { \ | |
| 357 | QLF2 (W, S_D), \ | |
| 358 | } | |
| 359 | ||
| a06ea964 NC |
360 | /* e.g. FMOV <Xd>, <Vn>.D[1]. */ |
| 361 | #define QL_XVD1 \ | |
| 362 | { \ | |
| 363 | QLF2(X,S_D), \ | |
| 364 | } | |
| 365 | ||
| 366 | /* e.g. FMOV <Vd>.D[1], <Xn>. */ | |
| 367 | #define QL_VD1X \ | |
| 368 | { \ | |
| 369 | QLF2(S_D,X), \ | |
| 370 | } | |
| 371 | ||
| 372 | /* e.g. EXTR <Xd>, <Xn>, <Xm>, #<lsb>. */ | |
| 373 | #define QL_EXTR \ | |
| 374 | { \ | |
| 375 | QLF4(W,W,W,imm_0_31), \ | |
| 376 | QLF4(X,X,X,imm_0_63), \ | |
| 377 | } | |
| 378 | ||
| 379 | /* e.g. LSL <Wd>, <Wn>, #<uimm>. */ | |
| 380 | #define QL_SHIFT \ | |
| 381 | { \ | |
| 382 | QLF3(W,W,imm_0_31), \ | |
| 383 | QLF3(X,X,imm_0_63), \ | |
| 384 | } | |
| 385 | ||
| 386 | /* e.g. UXTH <Xd>, <Wn>. */ | |
| 387 | #define QL_EXT \ | |
| 388 | { \ | |
| 389 | QLF2(W,W), \ | |
| 390 | QLF2(X,W), \ | |
| 391 | } | |
| 392 | ||
| 393 | /* e.g. UXTW <Xd>, <Wn>. */ | |
| 394 | #define QL_EXT_W \ | |
| 395 | { \ | |
| 396 | QLF2(X,W), \ | |
| 397 | } | |
| 398 | ||
| 399 | /* e.g. SQSHL <V><d>, <V><n>, #<shift>. */ | |
| 400 | #define QL_SSHIFT \ | |
| 401 | { \ | |
| 402 | QLF3(S_B , S_B , S_B ), \ | |
| 403 | QLF3(S_H , S_H , S_H ), \ | |
| 404 | QLF3(S_S , S_S , S_S ), \ | |
| 405 | QLF3(S_D , S_D , S_D ) \ | |
| 406 | } | |
| 407 | ||
| 408 | /* e.g. SSHR <V><d>, <V><n>, #<shift>. */ | |
| 409 | #define QL_SSHIFT_D \ | |
| 410 | { \ | |
| 411 | QLF3(S_D , S_D , S_D ) \ | |
| 412 | } | |
| 413 | ||
| 414 | /* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ | |
| 415 | #define QL_SSHIFT_SD \ | |
| 416 | { \ | |
| 417 | QLF3(S_S , S_S , S_S ), \ | |
| 418 | QLF3(S_D , S_D , S_D ) \ | |
| 419 | } | |
| 420 | ||
| 4fd0a9fd MW |
421 | /* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ |
| 422 | #define QL_SSHIFT_H \ | |
| 423 | { \ | |
| 424 | QLF3 (S_H, S_H, S_H) \ | |
| 425 | } | |
| 426 | ||
| a06ea964 NC |
427 | /* e.g. SQSHRUN <Vb><d>, <Va><n>, #<shift>. */ |
| 428 | #define QL_SSHIFTN \ | |
| 429 | { \ | |
| 430 | QLF3(S_B , S_H , S_B ), \ | |
| 431 | QLF3(S_H , S_S , S_H ), \ | |
| 432 | QLF3(S_S , S_D , S_S ), \ | |
| 433 | } | |
| 434 | ||
| 435 | /* e.g. SSHR <Vd>.<T>, <Vn>.<T>, #<shift>. | |
| 436 | The register operand variant qualifiers are deliberately used for the | |
| 437 | immediate operand to ease the operand encoding/decoding and qualifier | |
| 438 | sequence matching. */ | |
| 439 | #define QL_VSHIFT \ | |
| 440 | { \ | |
| 441 | QLF3(V_8B , V_8B , V_8B ), \ | |
| 442 | QLF3(V_16B, V_16B, V_16B), \ | |
| 443 | QLF3(V_4H , V_4H , V_4H ), \ | |
| 444 | QLF3(V_8H , V_8H , V_8H ), \ | |
| 445 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 446 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 447 | QLF3(V_2D , V_2D , V_2D ) \ | |
| 448 | } | |
| 449 | ||
| 450 | /* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ | |
| 451 | #define QL_VSHIFT_SD \ | |
| 452 | { \ | |
| 453 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 454 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 455 | QLF3(V_2D , V_2D , V_2D ) \ | |
| 456 | } | |
| 457 | ||
| b5b0f34c MW |
458 | /* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ |
| 459 | #define QL_VSHIFT_H \ | |
| 460 | { \ | |
| 461 | QLF3 (V_4H, V_4H, V_4H), \ | |
| 462 | QLF3 (V_8H, V_8H, V_8H) \ | |
| 463 | } | |
| 464 | ||
| a06ea964 NC |
465 | /* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */ |
| 466 | #define QL_VSHIFTN \ | |
| 467 | { \ | |
| 468 | QLF3(V_8B , V_8H , V_8B ), \ | |
| 469 | QLF3(V_4H , V_4S , V_4H ), \ | |
| 470 | QLF3(V_2S , V_2D , V_2S ), \ | |
| 471 | } | |
| 472 | ||
| 473 | /* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */ | |
| 474 | #define QL_VSHIFTN2 \ | |
| 475 | { \ | |
| 476 | QLF3(V_16B, V_8H, V_16B), \ | |
| 477 | QLF3(V_8H , V_4S , V_8H ), \ | |
| 478 | QLF3(V_4S , V_2D , V_4S ), \ | |
| 479 | } | |
| 480 | ||
| 481 | /* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. | |
| 482 | the 3rd qualifier is used to help the encoding. */ | |
| 483 | #define QL_VSHIFTL \ | |
| 484 | { \ | |
| 485 | QLF3(V_8H , V_8B , V_8B ), \ | |
| 486 | QLF3(V_4S , V_4H , V_4H ), \ | |
| 487 | QLF3(V_2D , V_2S , V_2S ), \ | |
| 488 | } | |
| 489 | ||
| 490 | /* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ | |
| 491 | #define QL_VSHIFTL2 \ | |
| 492 | { \ | |
| 493 | QLF3(V_8H , V_16B, V_16B), \ | |
| 494 | QLF3(V_4S , V_8H , V_8H ), \ | |
| 495 | QLF3(V_2D , V_4S , V_4S ), \ | |
| 496 | } | |
| 497 | ||
| 498 | /* e.g. TBL. */ | |
| 499 | #define QL_TABLE \ | |
| 500 | { \ | |
| 501 | QLF3(V_8B , V_16B, V_8B ), \ | |
| 502 | QLF3(V_16B, V_16B, V_16B), \ | |
| 503 | } | |
| 504 | ||
| 505 | /* e.g. SHA1H. */ | |
| 506 | #define QL_2SAMES \ | |
| 507 | { \ | |
| 508 | QLF2(S_S, S_S), \ | |
| 509 | } | |
| 510 | ||
| 511 | /* e.g. ABS <V><d>, <V><n>. */ | |
| 512 | #define QL_2SAMED \ | |
| 513 | { \ | |
| 514 | QLF2(S_D, S_D), \ | |
| 515 | } | |
| 516 | ||
| 517 | /* e.g. CMGT <V><d>, <V><n>, #0. */ | |
| 518 | #define QL_SISD_CMP_0 \ | |
| 519 | { \ | |
| 520 | QLF3(S_D, S_D, NIL), \ | |
| 521 | } | |
| 522 | ||
| 523 | /* e.g. FCMEQ <V><d>, <V><n>, #0. */ | |
| 524 | #define QL_SISD_FCMP_0 \ | |
| 525 | { \ | |
| 526 | QLF3(S_S, S_S, NIL), \ | |
| 527 | QLF3(S_D, S_D, NIL), \ | |
| 528 | } | |
| 529 | ||
| 80776b29 MW |
530 | /* e.g. FCMEQ <V><d>, <V><n>, #0. */ |
| 531 | #define QL_SISD_FCMP_H_0 \ | |
| 532 | { \ | |
| 533 | QLF3 (S_H, S_H, NIL), \ | |
| 534 | } | |
| 535 | ||
| a06ea964 NC |
536 | /* e.g. FMAXNMP <V><d>, <Vn>.<T>. */ |
| 537 | #define QL_SISD_PAIR \ | |
| 538 | { \ | |
| 539 | QLF2(S_S, V_2S), \ | |
| 540 | QLF2(S_D, V_2D), \ | |
| 541 | } | |
| 542 | ||
| b195470d MW |
543 | /* e.g. FMAXNMP <V><d>, <Vn>.<T>. */ |
| 544 | #define QL_SISD_PAIR_H \ | |
| 545 | { \ | |
| 546 | QLF2 (S_H, V_2H), \ | |
| 547 | } | |
| 548 | ||
| a06ea964 NC |
549 | /* e.g. ADDP <V><d>, <Vn>.<T>. */ |
| 550 | #define QL_SISD_PAIR_D \ | |
| 551 | { \ | |
| 552 | QLF2(S_D, V_2D), \ | |
| 553 | } | |
| 554 | ||
| 555 | /* e.g. DUP <V><d>, <Vn>.<T>[<index>]. */ | |
| 556 | #define QL_S_2SAME \ | |
| 557 | { \ | |
| 558 | QLF2(S_B, S_B), \ | |
| 559 | QLF2(S_H, S_H), \ | |
| 560 | QLF2(S_S, S_S), \ | |
| 561 | QLF2(S_D, S_D), \ | |
| 562 | } | |
| 563 | ||
| 564 | /* e.g. FCVTNS <V><d>, <V><n>. */ | |
| 565 | #define QL_S_2SAMESD \ | |
| 566 | { \ | |
| 567 | QLF2(S_S, S_S), \ | |
| 568 | QLF2(S_D, S_D), \ | |
| 569 | } | |
| 570 | ||
| 80776b29 MW |
571 | /* e.g. FCVTNS <V><d>, <V><n>. */ |
| 572 | #define QL_S_2SAMEH \ | |
| 573 | { \ | |
| 574 | QLF2 (S_H, S_H), \ | |
| 575 | } | |
| 576 | ||
| a06ea964 NC |
577 | /* e.g. SQXTN <Vb><d>, <Va><n>. */ |
| 578 | #define QL_SISD_NARROW \ | |
| 579 | { \ | |
| 580 | QLF2(S_B, S_H), \ | |
| 581 | QLF2(S_H, S_S), \ | |
| 582 | QLF2(S_S, S_D), \ | |
| 583 | } | |
| 584 | ||
| 585 | /* e.g. FCVTXN <Vb><d>, <Va><n>. */ | |
| 586 | #define QL_SISD_NARROW_S \ | |
| 587 | { \ | |
| 588 | QLF2(S_S, S_D), \ | |
| 589 | } | |
| 590 | ||
| 591 | /* e.g. FCVT. */ | |
| 592 | #define QL_FCVT \ | |
| 593 | { \ | |
| 594 | QLF2(S_S, S_H), \ | |
| 595 | QLF2(S_S, S_D), \ | |
| 596 | QLF2(S_D, S_H), \ | |
| 597 | QLF2(S_D, S_S), \ | |
| 598 | QLF2(S_H, S_S), \ | |
| 599 | QLF2(S_H, S_D), \ | |
| 600 | } | |
| 601 | ||
| 602 | /* FMOV <Dd>, <Dn>. */ | |
| 603 | #define QL_FP2 \ | |
| 604 | { \ | |
| 605 | QLF2(S_S, S_S), \ | |
| 606 | QLF2(S_D, S_D), \ | |
| 607 | } | |
| 608 | ||
| 622b9eb1 MW |
609 | /* FMOV <Hd>, <Hn>. */ |
| 610 | #define QL_FP2_H \ | |
| 611 | { \ | |
| 612 | QLF2 (S_H, S_H), \ | |
| 613 | } | |
| 614 | ||
| a06ea964 NC |
615 | /* e.g. SQADD <V><d>, <V><n>, <V><m>. */ |
| 616 | #define QL_S_3SAME \ | |
| 617 | { \ | |
| 618 | QLF3(S_B, S_B, S_B), \ | |
| 619 | QLF3(S_H, S_H, S_H), \ | |
| 620 | QLF3(S_S, S_S, S_S), \ | |
| 621 | QLF3(S_D, S_D, S_D), \ | |
| 622 | } | |
| 623 | ||
| 624 | /* e.g. CMGE <V><d>, <V><n>, <V><m>. */ | |
| 625 | #define QL_S_3SAMED \ | |
| 626 | { \ | |
| 627 | QLF3(S_D, S_D, S_D), \ | |
| 628 | } | |
| 629 | ||
| 630 | /* e.g. SQDMULH <V><d>, <V><n>, <V><m>. */ | |
| 631 | #define QL_SISD_HS \ | |
| 632 | { \ | |
| 633 | QLF3(S_H, S_H, S_H), \ | |
| 634 | QLF3(S_S, S_S, S_S), \ | |
| 635 | } | |
| 636 | ||
| 637 | /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vb><m>. */ | |
| 638 | #define QL_SISDL_HS \ | |
| 639 | { \ | |
| 640 | QLF3(S_S, S_H, S_H), \ | |
| 641 | QLF3(S_D, S_S, S_S), \ | |
| 642 | } | |
| 643 | ||
| 644 | /* FMUL <Sd>, <Sn>, <Sm>. */ | |
| 645 | #define QL_FP3 \ | |
| 646 | { \ | |
| 647 | QLF3(S_S, S_S, S_S), \ | |
| 648 | QLF3(S_D, S_D, S_D), \ | |
| 649 | } | |
| 650 | ||
| 622b9eb1 MW |
651 | /* FMUL <Hd>, <Hn>, <Hm>. */ |
| 652 | #define QL_FP3_H \ | |
| 653 | { \ | |
| 654 | QLF3 (S_H, S_H, S_H), \ | |
| 655 | } | |
| 656 | ||
| a06ea964 NC |
657 | /* FMADD <Dd>, <Dn>, <Dm>, <Da>. */ |
| 658 | #define QL_FP4 \ | |
| 659 | { \ | |
| 660 | QLF4(S_S, S_S, S_S, S_S), \ | |
| 661 | QLF4(S_D, S_D, S_D, S_D), \ | |
| 662 | } | |
| 663 | ||
| 622b9eb1 MW |
664 | /* FMADD <Hd>, <Hn>, <Hm>, <Ha>. */ |
| 665 | #define QL_FP4_H \ | |
| 666 | { \ | |
| 667 | QLF4 (S_H, S_H, S_H, S_H), \ | |
| 668 | } | |
| 669 | ||
| a06ea964 NC |
670 | /* e.g. FCMP <Dn>, #0.0. */ |
| 671 | #define QL_DST_SD \ | |
| 672 | { \ | |
| 673 | QLF2(S_S, NIL), \ | |
| 674 | QLF2(S_D, NIL), \ | |
| 675 | } | |
| 676 | ||
| 622b9eb1 MW |
677 | /* e.g. FCMP <Hn>, #0.0. */ |
| 678 | #define QL_DST_H \ | |
| 679 | { \ | |
| 680 | QLF2 (S_H, NIL), \ | |
| 681 | } | |
| 682 | ||
| a06ea964 NC |
683 | /* FCSEL <Sd>, <Sn>, <Sm>, <cond>. */ |
| 684 | #define QL_FP_COND \ | |
| 685 | { \ | |
| 686 | QLF4(S_S, S_S, S_S, NIL), \ | |
| 687 | QLF4(S_D, S_D, S_D, NIL), \ | |
| 688 | } | |
| 689 | ||
| 622b9eb1 MW |
690 | /* FCSEL <Hd>, <Hn>, <Hm>, <cond>. */ |
| 691 | #define QL_FP_COND_H \ | |
| 692 | { \ | |
| 693 | QLF4 (S_H, S_H, S_H, NIL), \ | |
| 694 | } | |
| 695 | ||
| a06ea964 NC |
696 | /* e.g. CCMN <Xn>, <Xm>, #<nzcv>, <cond>. */ |
| 697 | #define QL_CCMP \ | |
| 698 | { \ | |
| 699 | QLF4(W, W, NIL, NIL), \ | |
| 700 | QLF4(X, X, NIL, NIL), \ | |
| 701 | } | |
| 702 | ||
| 703 | /* e.g. CCMN <Xn>, #<imm>, #<nzcv>, <cond>, */ | |
| 704 | #define QL_CCMP_IMM \ | |
| 705 | { \ | |
| 706 | QLF4(W, NIL, NIL, NIL), \ | |
| 707 | QLF4(X, NIL, NIL, NIL), \ | |
| 708 | } | |
| 709 | ||
| 710 | /* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */ | |
| 711 | #define QL_FCCMP \ | |
| 712 | { \ | |
| 713 | QLF4(S_S, S_S, NIL, NIL), \ | |
| 714 | QLF4(S_D, S_D, NIL, NIL), \ | |
| 715 | } | |
| 716 | ||
| 622b9eb1 MW |
717 | /* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */ |
| 718 | #define QL_FCCMP_H \ | |
| 719 | { \ | |
| 720 | QLF4 (S_H, S_H, NIL, NIL), \ | |
| 721 | } | |
| 722 | ||
| a06ea964 NC |
723 | /* e.g. DUP <Vd>.<T>, <Vn>.<Ts>[<index>]. */ |
| 724 | #define QL_DUP_VX \ | |
| 725 | { \ | |
| 726 | QLF2(V_8B , S_B ), \ | |
| 727 | QLF2(V_16B, S_B ), \ | |
| 728 | QLF2(V_4H , S_H ), \ | |
| 729 | QLF2(V_8H , S_H ), \ | |
| 730 | QLF2(V_2S , S_S ), \ | |
| 731 | QLF2(V_4S , S_S ), \ | |
| 732 | QLF2(V_2D , S_D ), \ | |
| 733 | } | |
| 734 | ||
| 735 | /* e.g. DUP <Vd>.<T>, <Wn>. */ | |
| 736 | #define QL_DUP_VR \ | |
| 737 | { \ | |
| 738 | QLF2(V_8B , W ), \ | |
| 739 | QLF2(V_16B, W ), \ | |
| 740 | QLF2(V_4H , W ), \ | |
| 741 | QLF2(V_8H , W ), \ | |
| 742 | QLF2(V_2S , W ), \ | |
| 743 | QLF2(V_4S , W ), \ | |
| 744 | QLF2(V_2D , X ), \ | |
| 745 | } | |
| 746 | ||
| 747 | /* e.g. INS <Vd>.<Ts>[<index>], <Wn>. */ | |
| 748 | #define QL_INS_XR \ | |
| 749 | { \ | |
| 750 | QLF2(S_H , W ), \ | |
| 751 | QLF2(S_S , W ), \ | |
| 752 | QLF2(S_D , X ), \ | |
| 753 | QLF2(S_B , W ), \ | |
| 754 | } | |
| 755 | ||
| 756 | /* e.g. SMOV <Wd>, <Vn>.<Ts>[<index>]. */ | |
| 757 | #define QL_SMOV \ | |
| 758 | { \ | |
| 759 | QLF2(W , S_H), \ | |
| 760 | QLF2(X , S_H), \ | |
| 761 | QLF2(X , S_S), \ | |
| 762 | QLF2(W , S_B), \ | |
| 763 | QLF2(X , S_B), \ | |
| 764 | } | |
| 765 | ||
| 766 | /* e.g. UMOV <Wd>, <Vn>.<Ts>[<index>]. */ | |
| 767 | #define QL_UMOV \ | |
| 768 | { \ | |
| 769 | QLF2(W , S_H), \ | |
| 770 | QLF2(W , S_S), \ | |
| 771 | QLF2(X , S_D), \ | |
| 772 | QLF2(W , S_B), \ | |
| 773 | } | |
| 774 | ||
| 775 | /* e.g. MOV <Wd>, <Vn>.<Ts>[<index>]. */ | |
| 776 | #define QL_MOV \ | |
| 777 | { \ | |
| 778 | QLF2(W , S_S), \ | |
| 779 | QLF2(X , S_D), \ | |
| 780 | } | |
| 781 | ||
| 782 | /* e.g. SUQADD <Vd>.<T>, <Vn>.<T>. */ | |
| 783 | #define QL_V2SAME \ | |
| 784 | { \ | |
| 785 | QLF2(V_8B , V_8B ), \ | |
| 786 | QLF2(V_16B, V_16B), \ | |
| 787 | QLF2(V_4H , V_4H ), \ | |
| 788 | QLF2(V_8H , V_8H ), \ | |
| 789 | QLF2(V_2S , V_2S ), \ | |
| 790 | QLF2(V_4S , V_4S ), \ | |
| 791 | QLF2(V_2D , V_2D ), \ | |
| 792 | } | |
| 793 | ||
| 794 | /* e.g. URSQRTE <Vd>.<T>, <Vn>.<T>. */ | |
| 795 | #define QL_V2SAMES \ | |
| 796 | { \ | |
| 797 | QLF2(V_2S , V_2S ), \ | |
| 798 | QLF2(V_4S , V_4S ), \ | |
| 799 | } | |
| 800 | ||
| 801 | /* e.g. REV32 <Vd>.<T>, <Vn>.<T>. */ | |
| 802 | #define QL_V2SAMEBH \ | |
| 803 | { \ | |
| 804 | QLF2(V_8B , V_8B ), \ | |
| 805 | QLF2(V_16B, V_16B), \ | |
| 806 | QLF2(V_4H , V_4H ), \ | |
| 807 | QLF2(V_8H , V_8H ), \ | |
| 808 | } | |
| 809 | ||
| 810 | /* e.g. FRINTN <Vd>.<T>, <Vn>.<T>. */ | |
| 811 | #define QL_V2SAMESD \ | |
| 812 | { \ | |
| 813 | QLF2(V_2S , V_2S ), \ | |
| 814 | QLF2(V_4S , V_4S ), \ | |
| 815 | QLF2(V_2D , V_2D ), \ | |
| 816 | } | |
| 817 | ||
| 818 | /* e.g. REV64 <Vd>.<T>, <Vn>.<T>. */ | |
| 819 | #define QL_V2SAMEBHS \ | |
| 820 | { \ | |
| 821 | QLF2(V_8B , V_8B ), \ | |
| 822 | QLF2(V_16B, V_16B), \ | |
| 823 | QLF2(V_4H , V_4H ), \ | |
| 824 | QLF2(V_8H , V_8H ), \ | |
| 825 | QLF2(V_2S , V_2S ), \ | |
| 826 | QLF2(V_4S , V_4S ), \ | |
| 827 | } | |
| 828 | ||
| f3aa142b MW |
829 | /* e.g. FCMGT <Vd>.<T>, <Vd>.<T>>, #0.0. */ |
| 830 | #define QL_V2SAMEH \ | |
| 831 | { \ | |
| 832 | QLF2 (V_4H, V_4H), \ | |
| 833 | QLF2 (V_8H, V_8H), \ | |
| 834 | } | |
| 835 | ||
| a06ea964 NC |
836 | /* e.g. REV16 <Vd>.<T>, <Vn>.<T>. */ |
| 837 | #define QL_V2SAMEB \ | |
| 838 | { \ | |
| 839 | QLF2(V_8B , V_8B ), \ | |
| 840 | QLF2(V_16B, V_16B), \ | |
| 841 | } | |
| 842 | ||
| 843 | /* e.g. SADDLP <Vd>.<Ta>, <Vn>.<Tb>. */ | |
| 844 | #define QL_V2PAIRWISELONGBHS \ | |
| 845 | { \ | |
| 846 | QLF2(V_4H , V_8B ), \ | |
| 847 | QLF2(V_8H , V_16B), \ | |
| 848 | QLF2(V_2S , V_4H ), \ | |
| 849 | QLF2(V_4S , V_8H ), \ | |
| 850 | QLF2(V_1D , V_2S ), \ | |
| 851 | QLF2(V_2D , V_4S ), \ | |
| 852 | } | |
| 853 | ||
| 854 | /* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ | |
| 855 | #define QL_V2LONGBHS \ | |
| 856 | { \ | |
| 857 | QLF2(V_8H , V_8B ), \ | |
| 858 | QLF2(V_4S , V_4H ), \ | |
| 859 | QLF2(V_2D , V_2S ), \ | |
| 860 | } | |
| 861 | ||
| 862 | /* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ | |
| 863 | #define QL_V2LONGBHS2 \ | |
| 864 | { \ | |
| 865 | QLF2(V_8H , V_16B), \ | |
| 866 | QLF2(V_4S , V_8H ), \ | |
| 867 | QLF2(V_2D , V_4S ), \ | |
| 868 | } | |
| 869 | ||
| 870 | /* */ | |
| 871 | #define QL_V3SAME \ | |
| 872 | { \ | |
| 873 | QLF3(V_8B , V_8B , V_8B ), \ | |
| 874 | QLF3(V_16B, V_16B, V_16B), \ | |
| 875 | QLF3(V_4H , V_4H , V_4H ), \ | |
| 876 | QLF3(V_8H , V_8H , V_8H ), \ | |
| 877 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 878 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 879 | QLF3(V_2D , V_2D , V_2D ) \ | |
| 880 | } | |
| 881 | ||
| 882 | /* e.g. SHADD. */ | |
| 883 | #define QL_V3SAMEBHS \ | |
| 884 | { \ | |
| 885 | QLF3(V_8B , V_8B , V_8B ), \ | |
| 886 | QLF3(V_16B, V_16B, V_16B), \ | |
| 887 | QLF3(V_4H , V_4H , V_4H ), \ | |
| 888 | QLF3(V_8H , V_8H , V_8H ), \ | |
| 889 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 890 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 891 | } | |
| 892 | ||
| 893 | /* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 894 | #define QL_V2NARRS \ | |
| 895 | { \ | |
| 896 | QLF2(V_2S , V_2D ), \ | |
| 897 | } | |
| 898 | ||
| 899 | /* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 900 | #define QL_V2NARRS2 \ | |
| 901 | { \ | |
| 902 | QLF2(V_4S , V_2D ), \ | |
| 903 | } | |
| 904 | ||
| 905 | /* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 906 | #define QL_V2NARRHS \ | |
| 907 | { \ | |
| 908 | QLF2(V_4H , V_4S ), \ | |
| 909 | QLF2(V_2S , V_2D ), \ | |
| 910 | } | |
| 911 | ||
| 912 | /* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 913 | #define QL_V2NARRHS2 \ | |
| 914 | { \ | |
| 915 | QLF2(V_8H , V_4S ), \ | |
| 916 | QLF2(V_4S , V_2D ), \ | |
| 917 | } | |
| 918 | ||
| 919 | /* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */ | |
| 920 | #define QL_V2LONGHS \ | |
| 921 | { \ | |
| 922 | QLF2(V_4S , V_4H ), \ | |
| 923 | QLF2(V_2D , V_2S ), \ | |
| 924 | } | |
| 925 | ||
| 926 | /* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */ | |
| 927 | #define QL_V2LONGHS2 \ | |
| 928 | { \ | |
| 929 | QLF2(V_4S , V_8H ), \ | |
| 930 | QLF2(V_2D , V_4S ), \ | |
| 931 | } | |
| 932 | ||
| 933 | /* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 934 | #define QL_V2NARRBHS \ | |
| 935 | { \ | |
| 936 | QLF2(V_8B , V_8H ), \ | |
| 937 | QLF2(V_4H , V_4S ), \ | |
| 938 | QLF2(V_2S , V_2D ), \ | |
| 939 | } | |
| 940 | ||
| 941 | /* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
| 942 | #define QL_V2NARRBHS2 \ | |
| 943 | { \ | |
| 944 | QLF2(V_16B, V_8H ), \ | |
| 945 | QLF2(V_8H , V_4S ), \ | |
| 946 | QLF2(V_4S , V_2D ), \ | |
| 947 | } | |
| 948 | ||
| 949 | /* e.g. ORR. */ | |
| 950 | #define QL_V2SAMEB \ | |
| 951 | { \ | |
| 952 | QLF2(V_8B , V_8B ), \ | |
| 953 | QLF2(V_16B, V_16B), \ | |
| 954 | } | |
| 955 | ||
| 956 | /* e.g. AESE. */ | |
| 957 | #define QL_V2SAME16B \ | |
| 958 | { \ | |
| 959 | QLF2(V_16B, V_16B), \ | |
| 960 | } | |
| 961 | ||
| 962 | /* e.g. SHA1SU1. */ | |
| 963 | #define QL_V2SAME4S \ | |
| 964 | { \ | |
| 965 | QLF2(V_4S, V_4S), \ | |
| 966 | } | |
| 967 | ||
| 968 | /* e.g. SHA1SU0. */ | |
| 969 | #define QL_V3SAME4S \ | |
| 970 | { \ | |
| 971 | QLF3(V_4S, V_4S, V_4S), \ | |
| 972 | } | |
| 973 | ||
| 974 | /* e.g. SHADD. */ | |
| 975 | #define QL_V3SAMEB \ | |
| 976 | { \ | |
| 977 | QLF3(V_8B , V_8B , V_8B ), \ | |
| 978 | QLF3(V_16B, V_16B, V_16B), \ | |
| 979 | } | |
| 980 | ||
| 981 | /* e.g. EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>. */ | |
| 982 | #define QL_VEXT \ | |
| 983 | { \ | |
| 984 | QLF4(V_8B , V_8B , V_8B , imm_0_7), \ | |
| 985 | QLF4(V_16B, V_16B, V_16B, imm_0_15), \ | |
| 986 | } | |
| 987 | ||
| 988 | /* e.g. . */ | |
| 989 | #define QL_V3SAMEHS \ | |
| 990 | { \ | |
| 991 | QLF3(V_4H , V_4H , V_4H ), \ | |
| 992 | QLF3(V_8H , V_8H , V_8H ), \ | |
| 993 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 994 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 995 | } | |
| 996 | ||
| 997 | /* */ | |
| 998 | #define QL_V3SAMESD \ | |
| 999 | { \ | |
| 1000 | QLF3(V_2S , V_2S , V_2S ), \ | |
| 1001 | QLF3(V_4S , V_4S , V_4S ), \ | |
| 1002 | QLF3(V_2D , V_2D , V_2D ) \ | |
| 1003 | } | |
| 1004 | ||
| c2c4ff8d SN |
1005 | /* e.g. FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate>. */ |
| 1006 | #define QL_V3SAMEHSD_ROT \ | |
| 1007 | { \ | |
| 1008 | QLF4 (V_4H, V_4H, V_4H, NIL), \ | |
| 1009 | QLF4 (V_8H, V_8H, V_8H, NIL), \ | |
| 1010 | QLF4 (V_2S, V_2S, V_2S, NIL), \ | |
| 1011 | QLF4 (V_4S, V_4S, V_4S, NIL), \ | |
| 1012 | QLF4 (V_2D, V_2D, V_2D, NIL), \ | |
| 1013 | } | |
| 1014 | ||
| 51d543ed MW |
1015 | /* e.g. FMAXNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>. */ |
| 1016 | #define QL_V3SAMEH \ | |
| 1017 | { \ | |
| 1018 | QLF3 (V_4H , V_4H , V_4H ), \ | |
| 1019 | QLF3 (V_8H , V_8H , V_8H ), \ | |
| 1020 | } | |
| 1021 | ||
| a06ea964 NC |
1022 | /* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ |
| 1023 | #define QL_V3LONGHS \ | |
| 1024 | { \ | |
| 1025 | QLF3(V_4S , V_4H , V_4H ), \ | |
| 1026 | QLF3(V_2D , V_2S , V_2S ), \ | |
| 1027 | } | |
| 1028 | ||
| 1029 | /* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ | |
| 1030 | #define QL_V3LONGHS2 \ | |
| 1031 | { \ | |
| 1032 | QLF3(V_4S , V_8H , V_8H ), \ | |
| 1033 | QLF3(V_2D , V_4S , V_4S ), \ | |
| 1034 | } | |
| 1035 | ||
| 1036 | /* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ | |
| 1037 | #define QL_V3LONGBHS \ | |
| 1038 | { \ | |
| 1039 | QLF3(V_8H , V_8B , V_8B ), \ | |
| 1040 | QLF3(V_4S , V_4H , V_4H ), \ | |
| 1041 | QLF3(V_2D , V_2S , V_2S ), \ | |
| 1042 | } | |
| 1043 | ||
| 1044 | /* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ | |
| 1045 | #define QL_V3LONGBHS2 \ | |
| 1046 | { \ | |
| 1047 | QLF3(V_8H , V_16B , V_16B ), \ | |
| 1048 | QLF3(V_4S , V_8H , V_8H ), \ | |
| 1049 | QLF3(V_2D , V_4S , V_4S ), \ | |
| 1050 | } | |
| 1051 | ||
| 1052 | /* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */ | |
| 1053 | #define QL_V3WIDEBHS \ | |
| 1054 | { \ | |
| 1055 | QLF3(V_8H , V_8H , V_8B ), \ | |
| 1056 | QLF3(V_4S , V_4S , V_4H ), \ | |
| 1057 | QLF3(V_2D , V_2D , V_2S ), \ | |
| 1058 | } | |
| 1059 | ||
| 1060 | /* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */ | |
| 1061 | #define QL_V3WIDEBHS2 \ | |
| 1062 | { \ | |
| 1063 | QLF3(V_8H , V_8H , V_16B ), \ | |
| 1064 | QLF3(V_4S , V_4S , V_8H ), \ | |
| 1065 | QLF3(V_2D , V_2D , V_4S ), \ | |
| 1066 | } | |
| 1067 | ||
| 1068 | /* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */ | |
| 1069 | #define QL_V3NARRBHS \ | |
| 1070 | { \ | |
| 1071 | QLF3(V_8B , V_8H , V_8H ), \ | |
| 1072 | QLF3(V_4H , V_4S , V_4S ), \ | |
| 1073 | QLF3(V_2S , V_2D , V_2D ), \ | |
| 1074 | } | |
| 1075 | ||
| 1076 | /* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */ | |
| 1077 | #define QL_V3NARRBHS2 \ | |
| 1078 | { \ | |
| 1079 | QLF3(V_16B , V_8H , V_8H ), \ | |
| 1080 | QLF3(V_8H , V_4S , V_4S ), \ | |
| 1081 | QLF3(V_4S , V_2D , V_2D ), \ | |
| 1082 | } | |
| 1083 | ||
| 1084 | /* e.g. PMULL. */ | |
| 1085 | #define QL_V3LONGB \ | |
| 1086 | { \ | |
| 1087 | QLF3(V_8H , V_8B , V_8B ), \ | |
| 1088 | } | |
| 1089 | ||
| 1090 | /* e.g. PMULL crypto. */ | |
| 1091 | #define QL_V3LONGD \ | |
| 1092 | { \ | |
| 1093 | QLF3(V_1Q , V_1D , V_1D ), \ | |
| 1094 | } | |
| 1095 | ||
| 1096 | /* e.g. PMULL2. */ | |
| 1097 | #define QL_V3LONGB2 \ | |
| 1098 | { \ | |
| 1099 | QLF3(V_8H , V_16B, V_16B), \ | |
| 1100 | } | |
| 1101 | ||
| 1102 | /* e.g. PMULL2 crypto. */ | |
| 1103 | #define QL_V3LONGD2 \ | |
| 1104 | { \ | |
| 1105 | QLF3(V_1Q , V_2D , V_2D ), \ | |
| 1106 | } | |
| 1107 | ||
| 1108 | /* e.g. SHA1C. */ | |
| 1109 | #define QL_SHAUPT \ | |
| 1110 | { \ | |
| 1111 | QLF3(S_Q, S_S, V_4S), \ | |
| 1112 | } | |
| 1113 | ||
| 1114 | /* e.g. SHA256H2. */ | |
| 1115 | #define QL_SHA256UPT \ | |
| 1116 | { \ | |
| 1117 | QLF3(S_Q, S_Q, V_4S), \ | |
| 1118 | } | |
| 1119 | ||
| 1120 | /* e.g. LDXRB <Wt>, [<Xn|SP>{,#0}]. */ | |
| 1121 | #define QL_W1_LDST_EXC \ | |
| 1122 | { \ | |
| 1123 | QLF2(W, NIL), \ | |
| 1124 | } | |
| 1125 | ||
| 1126 | /* e.g. LDXR <Xt>, [<Xn|SP>{,#0}]. */ | |
| 1127 | #define QL_R1NIL \ | |
| 1128 | { \ | |
| 1129 | QLF2(W, NIL), \ | |
| 1130 | QLF2(X, NIL), \ | |
| 1131 | } | |
| 1132 | ||
| 1133 | /* e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */ | |
| 1134 | #define QL_W2_LDST_EXC \ | |
| 1135 | { \ | |
| 1136 | QLF3(W, W, NIL), \ | |
| 1137 | } | |
| 1138 | ||
| 1139 | /* e.g. STXR <Ws>, <Xt>, [<Xn|SP>{,#0}]. */ | |
| 1140 | #define QL_R2_LDST_EXC \ | |
| 1141 | { \ | |
| 1142 | QLF3(W, W, NIL), \ | |
| 1143 | QLF3(W, X, NIL), \ | |
| 1144 | } | |
| 1145 | ||
| 3f06e550 SN |
1146 | /* e.g. LDRAA <Xt>, [<Xn|SP>{,#imm}]. */ |
| 1147 | #define QL_X1NIL \ | |
| 1148 | { \ | |
| 1149 | QLF2(X, NIL), \ | |
| 1150 | } | |
| 1151 | ||
| a06ea964 NC |
1152 | /* e.g. LDXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */ |
| 1153 | #define QL_R2NIL \ | |
| 1154 | { \ | |
| 1155 | QLF3(W, W, NIL), \ | |
| 1156 | QLF3(X, X, NIL), \ | |
| 1157 | } | |
| 1158 | ||
| ee804238 JW |
1159 | /* e.g. CASP <Xt1>, <Xt1+1>, <Xt2>, <Xt2+1>, [<Xn|SP>{,#0}]. */ |
| 1160 | #define QL_R4NIL \ | |
| 1161 | { \ | |
| 1162 | QLF5(W, W, W, W, NIL), \ | |
| 1163 | QLF5(X, X, X, X, NIL), \ | |
| 1164 | } | |
| 1165 | ||
| a06ea964 NC |
1166 | /* e.g. STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */ |
| 1167 | #define QL_R3_LDST_EXC \ | |
| 1168 | { \ | |
| 1169 | QLF4(W, W, W, NIL), \ | |
| 1170 | QLF4(W, X, X, NIL), \ | |
| 1171 | } | |
| 1172 | ||
| 1173 | /* e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1174 | #define QL_LDST_FP \ | |
| 1175 | { \ | |
| 1176 | QLF2(S_B, S_B), \ | |
| 1177 | QLF2(S_H, S_H), \ | |
| 1178 | QLF2(S_S, S_S), \ | |
| 1179 | QLF2(S_D, S_D), \ | |
| 1180 | QLF2(S_Q, S_Q), \ | |
| 1181 | } | |
| 1182 | ||
| 1183 | /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1184 | #define QL_LDST_R \ | |
| 1185 | { \ | |
| 1186 | QLF2(W, S_S), \ | |
| 1187 | QLF2(X, S_D), \ | |
| 1188 | } | |
| 1189 | ||
| 1190 | /* e.g. STRB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1191 | #define QL_LDST_W8 \ | |
| 1192 | { \ | |
| 1193 | QLF2(W, S_B), \ | |
| 1194 | } | |
| 1195 | ||
| 1196 | /* e.g. LDRSB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1197 | #define QL_LDST_R8 \ | |
| 1198 | { \ | |
| 1199 | QLF2(W, S_B), \ | |
| 1200 | QLF2(X, S_B), \ | |
| 1201 | } | |
| 1202 | ||
| 1203 | /* e.g. STRH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1204 | #define QL_LDST_W16 \ | |
| 1205 | { \ | |
| 1206 | QLF2(W, S_H), \ | |
| 1207 | } | |
| 1208 | ||
| 1209 | /* e.g. LDRSW <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1210 | #define QL_LDST_X32 \ | |
| 1211 | { \ | |
| 1212 | QLF2(X, S_S), \ | |
| 1213 | } | |
| 1214 | ||
| 1215 | /* e.g. LDRSH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1216 | #define QL_LDST_R16 \ | |
| 1217 | { \ | |
| 1218 | QLF2(W, S_H), \ | |
| 1219 | QLF2(X, S_H), \ | |
| 1220 | } | |
| 1221 | ||
| 1222 | /* e.g. PRFM <prfop>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
| 1223 | #define QL_LDST_PRFM \ | |
| 1224 | { \ | |
| 1225 | QLF2(NIL, S_D), \ | |
| 1226 | } | |
| 1227 | ||
| e6025b54 SD |
1228 | /* e.g. LDG <Xt>, [<Xn|SP>{, #<simm>}]. */ |
| 1229 | #define QL_LDG \ | |
| 1230 | { \ | |
| 1231 | QLF2(X, imm_tag), \ | |
| 1232 | } | |
| 1233 | ||
| a06ea964 NC |
1234 | /* e.g. LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]. */ |
| 1235 | #define QL_LDST_PAIR_X32 \ | |
| 1236 | { \ | |
| 1237 | QLF3(X, X, S_S), \ | |
| 1238 | } | |
| 1239 | ||
| fb3265b3 SD |
1240 | /* e.g. STGP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]. */ |
| 1241 | #define QL_STGP \ | |
| 1242 | { \ | |
| 1243 | QLF3(X, X, imm_tag), \ | |
| 1244 | } | |
| 1245 | ||
| a06ea964 NC |
1246 | /* e.g. STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!. */ |
| 1247 | #define QL_LDST_PAIR_R \ | |
| 1248 | { \ | |
| 1249 | QLF3(W, W, S_S), \ | |
| 1250 | QLF3(X, X, S_D), \ | |
| 1251 | } | |
| 1252 | ||
| 1253 | /* e.g. STNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */ | |
| 1254 | #define QL_LDST_PAIR_FP \ | |
| 1255 | { \ | |
| 1256 | QLF3(S_S, S_S, S_S), \ | |
| 1257 | QLF3(S_D, S_D, S_D), \ | |
| 1258 | QLF3(S_Q, S_Q, S_Q), \ | |
| 1259 | } | |
| 1260 | ||
| 1261 | /* e.g. LD3 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */ | |
| 1262 | #define QL_SIMD_LDST \ | |
| 1263 | { \ | |
| 1264 | QLF2(V_8B, NIL), \ | |
| 1265 | QLF2(V_16B, NIL), \ | |
| 1266 | QLF2(V_4H, NIL), \ | |
| 1267 | QLF2(V_8H, NIL), \ | |
| 1268 | QLF2(V_2S, NIL), \ | |
| 1269 | QLF2(V_4S, NIL), \ | |
| 1270 | QLF2(V_2D, NIL), \ | |
| 1271 | } | |
| 1272 | ||
| 1273 | /* e.g. LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */ | |
| 1274 | #define QL_SIMD_LDST_ANY \ | |
| 1275 | { \ | |
| 1276 | QLF2(V_8B, NIL), \ | |
| 1277 | QLF2(V_16B, NIL), \ | |
| 1278 | QLF2(V_4H, NIL), \ | |
| 1279 | QLF2(V_8H, NIL), \ | |
| 1280 | QLF2(V_2S, NIL), \ | |
| 1281 | QLF2(V_4S, NIL), \ | |
| 1282 | QLF2(V_1D, NIL), \ | |
| 1283 | QLF2(V_2D, NIL), \ | |
| 1284 | } | |
| 1285 | ||
| 1286 | /* e.g. LD4 {<Vt>.<T>, <Vt2a>.<T>, <Vt3a>.<T>, <Vt4a>.<T>}[<index>], [<Xn|SP>]. */ | |
| 1287 | #define QL_SIMD_LDSTONE \ | |
| 1288 | { \ | |
| 1289 | QLF2(S_B, NIL), \ | |
| 1290 | QLF2(S_H, NIL), \ | |
| 1291 | QLF2(S_S, NIL), \ | |
| 1292 | QLF2(S_D, NIL), \ | |
| 1293 | } | |
| 1294 | ||
| 1295 | /* e.g. ADDV <V><d>, <Vn>.<T>. */ | |
| 1296 | #define QL_XLANES \ | |
| 1297 | { \ | |
| 1298 | QLF2(S_B, V_8B), \ | |
| 1299 | QLF2(S_B, V_16B), \ | |
| 1300 | QLF2(S_H, V_4H), \ | |
| 1301 | QLF2(S_H, V_8H), \ | |
| 1302 | QLF2(S_S, V_4S), \ | |
| 1303 | } | |
| 1304 | ||
| 1305 | /* e.g. FMINV <V><d>, <Vn>.<T>. */ | |
| 1306 | #define QL_XLANES_FP \ | |
| 1307 | { \ | |
| 1308 | QLF2(S_S, V_4S), \ | |
| 1309 | } | |
| 1310 | ||
| bb515fea MW |
1311 | /* e.g. FMINV <V><d>, <Vn>.<T>. */ |
| 1312 | #define QL_XLANES_FP_H \ | |
| 1313 | { \ | |
| 1314 | QLF2 (S_H, V_4H), \ | |
| 1315 | QLF2 (S_H, V_8H), \ | |
| 1316 | } | |
| 1317 | ||
| a06ea964 NC |
1318 | /* e.g. SADDLV <V><d>, <Vn>.<T>. */ |
| 1319 | #define QL_XLANES_L \ | |
| 1320 | { \ | |
| 1321 | QLF2(S_H, V_8B), \ | |
| 1322 | QLF2(S_H, V_16B), \ | |
| 1323 | QLF2(S_S, V_4H), \ | |
| 1324 | QLF2(S_S, V_8H), \ | |
| 1325 | QLF2(S_D, V_4S), \ | |
| 1326 | } | |
| 1327 | ||
| 1328 | /* e.g. MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]. */ | |
| 1329 | #define QL_ELEMENT \ | |
| 1330 | { \ | |
| 1331 | QLF3(V_4H, V_4H, S_H), \ | |
| 1332 | QLF3(V_8H, V_8H, S_H), \ | |
| 1333 | QLF3(V_2S, V_2S, S_S), \ | |
| 1334 | QLF3(V_4S, V_4S, S_S), \ | |
| 1335 | } | |
| 1336 | ||
| 1337 | /* e.g. SMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */ | |
| 1338 | #define QL_ELEMENT_L \ | |
| 1339 | { \ | |
| 1340 | QLF3(V_4S, V_4H, S_H), \ | |
| 1341 | QLF3(V_2D, V_2S, S_S), \ | |
| 1342 | } | |
| 1343 | ||
| 1344 | /* e.g. SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */ | |
| 1345 | #define QL_ELEMENT_L2 \ | |
| 1346 | { \ | |
| 1347 | QLF3(V_4S, V_8H, S_H), \ | |
| 1348 | QLF3(V_2D, V_4S, S_S), \ | |
| 1349 | } | |
| 1350 | ||
| 1351 | /* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */ | |
| 1352 | #define QL_ELEMENT_FP \ | |
| 1353 | { \ | |
| 1354 | QLF3(V_2S, V_2S, S_S), \ | |
| 1355 | QLF3(V_4S, V_4S, S_S), \ | |
| 1356 | QLF3(V_2D, V_2D, S_D), \ | |
| 1357 | } | |
| 1358 | ||
| 42f23f62 MW |
1359 | /* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */ |
| 1360 | #define QL_ELEMENT_FP_H \ | |
| 1361 | { \ | |
| 1362 | QLF3 (V_4H, V_4H, S_H), \ | |
| 1363 | QLF3 (V_8H, V_8H, S_H), \ | |
| 1364 | } | |
| 1365 | ||
| c2c4ff8d SN |
1366 | /* e.g. FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>], #<rotate>. */ |
| 1367 | #define QL_ELEMENT_ROT \ | |
| 1368 | { \ | |
| 1369 | QLF4 (V_4H, V_4H, S_H, NIL), \ | |
| 1370 | QLF4 (V_8H, V_8H, S_H, NIL), \ | |
| 1371 | QLF4 (V_4S, V_4S, S_S, NIL), \ | |
| 1372 | } | |
| 1373 | ||
| a06ea964 NC |
1374 | /* e.g. MOVI <Vd>.4S, #<imm8> {, LSL #<amount>}. */ |
| 1375 | #define QL_SIMD_IMM_S0W \ | |
| 1376 | { \ | |
| 1377 | QLF2(V_2S, LSL), \ | |
| 1378 | QLF2(V_4S, LSL), \ | |
| 1379 | } | |
| 1380 | ||
| 1381 | /* e.g. MOVI <Vd>.4S, #<imm8>, MSL #<amount>. */ | |
| 1382 | #define QL_SIMD_IMM_S1W \ | |
| 1383 | { \ | |
| 1384 | QLF2(V_2S, MSL), \ | |
| 1385 | QLF2(V_4S, MSL), \ | |
| 1386 | } | |
| 1387 | ||
| 1388 | /* e.g. MOVI <Vd>.4H, #<imm8> {, LSL #<amount>}. */ | |
| 1389 | #define QL_SIMD_IMM_S0H \ | |
| 1390 | { \ | |
| 1391 | QLF2(V_4H, LSL), \ | |
| 1392 | QLF2(V_8H, LSL), \ | |
| 1393 | } | |
| 1394 | ||
| 1395 | /* e.g. FMOV <Vd>.<T>, #<imm>. */ | |
| 1396 | #define QL_SIMD_IMM_S \ | |
| 1397 | { \ | |
| 1398 | QLF2(V_2S, NIL), \ | |
| 1399 | QLF2(V_4S, NIL), \ | |
| 1400 | } | |
| 1401 | ||
| f5555712 | 1402 | /* e.g. MOVI <Vd>.8B, #<imm8> {, LSL #<amount>}. */ |
| a06ea964 NC |
1403 | #define QL_SIMD_IMM_B \ |
| 1404 | { \ | |
| f5555712 YZ |
1405 | QLF2(V_8B, LSL), \ |
| 1406 | QLF2(V_16B, LSL), \ | |
| a06ea964 NC |
1407 | } |
| 1408 | /* e.g. MOVI <Dd>, #<imm>. */ | |
| 1409 | #define QL_SIMD_IMM_D \ | |
| 1410 | { \ | |
| 1411 | QLF2(S_D, NIL), \ | |
| 1412 | } | |
| 1413 | ||
| 4b5fc357 MW |
1414 | /* e.g. FMOV <Vd>.<T>, #<imm>. */ |
| 1415 | #define QL_SIMD_IMM_H \ | |
| 1416 | { \ | |
| 1417 | QLF2 (V_4H, NIL), \ | |
| 1418 | QLF2 (V_8H, NIL), \ | |
| 1419 | } | |
| 1420 | ||
| a06ea964 NC |
1421 | /* e.g. MOVI <Vd>.2D, #<imm>. */ |
| 1422 | #define QL_SIMD_IMM_V2D \ | |
| 1423 | { \ | |
| 1424 | QLF2(V_2D, NIL), \ | |
| 1425 | } | |
| c0890d26 RS |
1426 | |
| 1427 | /* The naming convention for SVE macros is: | |
| 1428 | ||
| 1429 | OP_SVE_<operands>[_<sizes>]* | |
| 1430 | ||
| 1431 | <operands> contains one character per operand, using the following scheme: | |
| 1432 | ||
| 1433 | - U: the operand is unqualified (NIL). | |
| 1434 | ||
| 1435 | - [BHSD]: the operand has a S_[BHSD] qualifier and the choice of | |
| 1436 | qualifier is the same for all variants. This is used for both | |
| 1437 | .[BHSD] suffixes on an SVE predicate or vector register and | |
| 1438 | scalar FPRs of the form [BHSD]<number>. | |
| 1439 | ||
| 1440 | - [WX]: the operand has a [WX] qualifier and the choice of qualifier | |
| 1441 | is the same for all variants. | |
| 1442 | ||
| 1443 | - [ZM]: the operand has a /[ZM] suffix and the choice of suffix | |
| 1444 | is the same for all variants. | |
| 1445 | ||
| 1446 | - V: the operand has a S_[BHSD] qualifier and the choice of qualifier | |
| 1447 | is not the same for all variants. | |
| 1448 | ||
| 1449 | - R: the operand has a [WX] qualifier and the choice of qualifier is | |
| 1450 | not the same for all variants. | |
| 1451 | ||
| 1452 | - P: the operand has a /[ZM] suffix and the choice of suffix is not | |
| 1453 | the same for all variants. | |
| 1454 | ||
| 1455 | The _<sizes>, if present, give the subset of [BHSD] that are accepted | |
| 1456 | by the V entries in <operands>. */ | |
| 1457 | #define OP_SVE_B \ | |
| 1458 | { \ | |
| 1459 | QLF1(S_B), \ | |
| 1460 | } | |
| 1461 | #define OP_SVE_BB \ | |
| 1462 | { \ | |
| 1463 | QLF2(S_B,S_B), \ | |
| 1464 | } | |
| 1465 | #define OP_SVE_BBBU \ | |
| 1466 | { \ | |
| 1467 | QLF4(S_B,S_B,S_B,NIL), \ | |
| 1468 | } | |
| 1469 | #define OP_SVE_BMB \ | |
| 1470 | { \ | |
| 1471 | QLF3(S_B,P_M,S_B), \ | |
| 1472 | } | |
| 1473 | #define OP_SVE_BPB \ | |
| 1474 | { \ | |
| 1475 | QLF3(S_B,P_Z,S_B), \ | |
| 1476 | QLF3(S_B,P_M,S_B), \ | |
| 1477 | } | |
| 1478 | #define OP_SVE_BUB \ | |
| 1479 | { \ | |
| 1480 | QLF3(S_B,NIL,S_B), \ | |
| 1481 | } | |
| 1482 | #define OP_SVE_BUBB \ | |
| 1483 | { \ | |
| 1484 | QLF4(S_B,NIL,S_B,S_B), \ | |
| 1485 | } | |
| 1486 | #define OP_SVE_BUU \ | |
| 1487 | { \ | |
| 1488 | QLF3(S_B,NIL,NIL), \ | |
| 1489 | } | |
| 1490 | #define OP_SVE_BZ \ | |
| 1491 | { \ | |
| 1492 | QLF2(S_B,P_Z), \ | |
| 1493 | } | |
| 1494 | #define OP_SVE_BZB \ | |
| 1495 | { \ | |
| 1496 | QLF3(S_B,P_Z,S_B), \ | |
| 1497 | } | |
| 1498 | #define OP_SVE_BZBB \ | |
| 1499 | { \ | |
| 1500 | QLF4(S_B,P_Z,S_B,S_B), \ | |
| 1501 | } | |
| 1502 | #define OP_SVE_BZU \ | |
| 1503 | { \ | |
| 1504 | QLF3(S_B,P_Z,NIL), \ | |
| 1505 | } | |
| 1506 | #define OP_SVE_DD \ | |
| 1507 | { \ | |
| 1508 | QLF2(S_D,S_D), \ | |
| 1509 | } | |
| 1510 | #define OP_SVE_DDD \ | |
| 1511 | { \ | |
| 1512 | QLF3(S_D,S_D,S_D), \ | |
| 1513 | } | |
| 1514 | #define OP_SVE_DMD \ | |
| 1515 | { \ | |
| 1516 | QLF3(S_D,P_M,S_D), \ | |
| 1517 | } | |
| 1518 | #define OP_SVE_DMH \ | |
| 1519 | { \ | |
| 1520 | QLF3(S_D,P_M,S_H), \ | |
| 1521 | } | |
| 1522 | #define OP_SVE_DMS \ | |
| 1523 | { \ | |
| 1524 | QLF3(S_D,P_M,S_S), \ | |
| 1525 | } | |
| 1526 | #define OP_SVE_DU \ | |
| 1527 | { \ | |
| 1528 | QLF2(S_D,NIL), \ | |
| 1529 | } | |
| 1530 | #define OP_SVE_DUD \ | |
| 1531 | { \ | |
| 1532 | QLF3(S_D,NIL,S_D), \ | |
| 1533 | } | |
| 1534 | #define OP_SVE_DUU \ | |
| 1535 | { \ | |
| 1536 | QLF3(S_D,NIL,NIL), \ | |
| 1537 | } | |
| 1538 | #define OP_SVE_DUV_BHS \ | |
| 1539 | { \ | |
| 1540 | QLF3(S_D,NIL,S_B), \ | |
| 1541 | QLF3(S_D,NIL,S_H), \ | |
| 1542 | QLF3(S_D,NIL,S_S), \ | |
| 1543 | } | |
| 1544 | #define OP_SVE_DUV_BHSD \ | |
| 1545 | { \ | |
| 1546 | QLF3(S_D,NIL,S_B), \ | |
| 1547 | QLF3(S_D,NIL,S_H), \ | |
| 1548 | QLF3(S_D,NIL,S_S), \ | |
| 1549 | QLF3(S_D,NIL,S_D), \ | |
| 1550 | } | |
| 1551 | #define OP_SVE_DZD \ | |
| 1552 | { \ | |
| 1553 | QLF3(S_D,P_Z,S_D), \ | |
| 1554 | } | |
| 1555 | #define OP_SVE_DZU \ | |
| 1556 | { \ | |
| 1557 | QLF3(S_D,P_Z,NIL), \ | |
| 1558 | } | |
| 1559 | #define OP_SVE_HB \ | |
| 1560 | { \ | |
| 1561 | QLF2(S_H,S_B), \ | |
| 1562 | } | |
| 582e12bf RS |
1563 | #define OP_SVE_HMH \ |
| 1564 | { \ | |
| 1565 | QLF3(S_H,P_M,S_H), \ | |
| 1566 | } | |
| c0890d26 RS |
1567 | #define OP_SVE_HMD \ |
| 1568 | { \ | |
| 1569 | QLF3(S_H,P_M,S_D), \ | |
| 1570 | } | |
| 1571 | #define OP_SVE_HMS \ | |
| 1572 | { \ | |
| 1573 | QLF3(S_H,P_M,S_S), \ | |
| 1574 | } | |
| 1575 | #define OP_SVE_HU \ | |
| 1576 | { \ | |
| 1577 | QLF2(S_H,NIL), \ | |
| 1578 | } | |
| 1579 | #define OP_SVE_HUU \ | |
| 1580 | { \ | |
| 1581 | QLF3(S_H,NIL,NIL), \ | |
| 1582 | } | |
| 1583 | #define OP_SVE_HZU \ | |
| 1584 | { \ | |
| 1585 | QLF3(S_H,P_Z,NIL), \ | |
| 1586 | } | |
| 1587 | #define OP_SVE_RR \ | |
| 1588 | { \ | |
| 1589 | QLF2(W,W), \ | |
| 1590 | QLF2(X,X), \ | |
| 1591 | } | |
| 1592 | #define OP_SVE_RURV_BHSD \ | |
| 1593 | { \ | |
| 1594 | QLF4(W,NIL,W,S_B), \ | |
| 1595 | QLF4(W,NIL,W,S_H), \ | |
| 1596 | QLF4(W,NIL,W,S_S), \ | |
| 1597 | QLF4(X,NIL,X,S_D), \ | |
| 1598 | } | |
| 1599 | #define OP_SVE_RUV_BHSD \ | |
| 1600 | { \ | |
| 1601 | QLF3(W,NIL,S_B), \ | |
| 1602 | QLF3(W,NIL,S_H), \ | |
| 1603 | QLF3(W,NIL,S_S), \ | |
| 1604 | QLF3(X,NIL,S_D), \ | |
| 1605 | } | |
| 1606 | #define OP_SVE_SMD \ | |
| 1607 | { \ | |
| 1608 | QLF3(S_S,P_M,S_D), \ | |
| 1609 | } | |
| 1610 | #define OP_SVE_SMH \ | |
| 1611 | { \ | |
| 1612 | QLF3(S_S,P_M,S_H), \ | |
| 1613 | } | |
| 1614 | #define OP_SVE_SMS \ | |
| 1615 | { \ | |
| 1616 | QLF3(S_S,P_M,S_S), \ | |
| 1617 | } | |
| 1618 | #define OP_SVE_SU \ | |
| 1619 | { \ | |
| 1620 | QLF2(S_S,NIL), \ | |
| 1621 | } | |
| 1622 | #define OP_SVE_SUS \ | |
| 1623 | { \ | |
| 1624 | QLF3(S_S,NIL,S_S), \ | |
| 1625 | } | |
| 1626 | #define OP_SVE_SUU \ | |
| 1627 | { \ | |
| 1628 | QLF3(S_S,NIL,NIL), \ | |
| 1629 | } | |
| 1630 | #define OP_SVE_SZS \ | |
| 1631 | { \ | |
| 1632 | QLF3(S_S,P_Z,S_S), \ | |
| 1633 | } | |
| 1634 | #define OP_SVE_SZU \ | |
| 1635 | { \ | |
| 1636 | QLF3(S_S,P_Z,NIL), \ | |
| 1637 | } | |
| 1638 | #define OP_SVE_UB \ | |
| 1639 | { \ | |
| 1640 | QLF2(NIL,S_B), \ | |
| 1641 | } | |
| 1642 | #define OP_SVE_UUD \ | |
| 1643 | { \ | |
| 1644 | QLF3(NIL,NIL,S_D), \ | |
| 1645 | } | |
| 1646 | #define OP_SVE_UUS \ | |
| 1647 | { \ | |
| 1648 | QLF3(NIL,NIL,S_S), \ | |
| 1649 | } | |
| 1650 | #define OP_SVE_VMR_BHSD \ | |
| 1651 | { \ | |
| 1652 | QLF3(S_B,P_M,W), \ | |
| 1653 | QLF3(S_H,P_M,W), \ | |
| 1654 | QLF3(S_S,P_M,W), \ | |
| 1655 | QLF3(S_D,P_M,X), \ | |
| 1656 | } | |
| 582e12bf | 1657 | #define OP_SVE_VMU_HSD \ |
| c0890d26 | 1658 | { \ |
| 582e12bf | 1659 | QLF3(S_H,P_M,NIL), \ |
| c0890d26 RS |
1660 | QLF3(S_S,P_M,NIL), \ |
| 1661 | QLF3(S_D,P_M,NIL), \ | |
| 1662 | } | |
| 1663 | #define OP_SVE_VMVD_BHS \ | |
| 1664 | { \ | |
| 1665 | QLF4(S_B,P_M,S_B,S_D), \ | |
| 1666 | QLF4(S_H,P_M,S_H,S_D), \ | |
| 1667 | QLF4(S_S,P_M,S_S,S_D), \ | |
| 1668 | } | |
| 1669 | #define OP_SVE_VMVU_BHSD \ | |
| 1670 | { \ | |
| 1671 | QLF4(S_B,P_M,S_B,NIL), \ | |
| 1672 | QLF4(S_H,P_M,S_H,NIL), \ | |
| 1673 | QLF4(S_S,P_M,S_S,NIL), \ | |
| 1674 | QLF4(S_D,P_M,S_D,NIL), \ | |
| 1675 | } | |
| 582e12bf | 1676 | #define OP_SVE_VMVU_HSD \ |
| c0890d26 | 1677 | { \ |
| 582e12bf | 1678 | QLF4(S_H,P_M,S_H,NIL), \ |
| c0890d26 RS |
1679 | QLF4(S_S,P_M,S_S,NIL), \ |
| 1680 | QLF4(S_D,P_M,S_D,NIL), \ | |
| 1681 | } | |
| 1682 | #define OP_SVE_VMVV_BHSD \ | |
| 1683 | { \ | |
| 1684 | QLF4(S_B,P_M,S_B,S_B), \ | |
| 1685 | QLF4(S_H,P_M,S_H,S_H), \ | |
| 1686 | QLF4(S_S,P_M,S_S,S_S), \ | |
| 1687 | QLF4(S_D,P_M,S_D,S_D), \ | |
| 1688 | } | |
| 582e12bf RS |
1689 | #define OP_SVE_VMVV_HSD \ |
| 1690 | { \ | |
| 1691 | QLF4(S_H,P_M,S_H,S_H), \ | |
| 1692 | QLF4(S_S,P_M,S_S,S_S), \ | |
| 1693 | QLF4(S_D,P_M,S_D,S_D), \ | |
| 1694 | } | |
| c0890d26 RS |
1695 | #define OP_SVE_VMVV_SD \ |
| 1696 | { \ | |
| 1697 | QLF4(S_S,P_M,S_S,S_S), \ | |
| 1698 | QLF4(S_D,P_M,S_D,S_D), \ | |
| 1699 | } | |
| 582e12bf RS |
1700 | #define OP_SVE_VMVVU_HSD \ |
| 1701 | { \ | |
| 1702 | QLF5(S_H,P_M,S_H,S_H,NIL), \ | |
| 1703 | QLF5(S_S,P_M,S_S,S_S,NIL), \ | |
| 1704 | QLF5(S_D,P_M,S_D,S_D,NIL), \ | |
| 1705 | } | |
| c0890d26 RS |
1706 | #define OP_SVE_VMV_BHSD \ |
| 1707 | { \ | |
| 1708 | QLF3(S_B,P_M,S_B), \ | |
| 1709 | QLF3(S_H,P_M,S_H), \ | |
| 1710 | QLF3(S_S,P_M,S_S), \ | |
| 1711 | QLF3(S_D,P_M,S_D), \ | |
| 1712 | } | |
| 1713 | #define OP_SVE_VMV_HSD \ | |
| 1714 | { \ | |
| 1715 | QLF3(S_H,P_M,S_H), \ | |
| 1716 | QLF3(S_S,P_M,S_S), \ | |
| 1717 | QLF3(S_D,P_M,S_D), \ | |
| 1718 | } | |
| 1719 | #define OP_SVE_VMV_SD \ | |
| 1720 | { \ | |
| 1721 | QLF3(S_S,P_M,S_S), \ | |
| 1722 | QLF3(S_D,P_M,S_D), \ | |
| 1723 | } | |
| 582e12bf | 1724 | #define OP_SVE_VM_HSD \ |
| c0890d26 | 1725 | { \ |
| 582e12bf | 1726 | QLF2(S_H,P_M), \ |
| c0890d26 RS |
1727 | QLF2(S_S,P_M), \ |
| 1728 | QLF2(S_D,P_M), \ | |
| 1729 | } | |
| 1730 | #define OP_SVE_VPU_BHSD \ | |
| 1731 | { \ | |
| 1732 | QLF3(S_B,P_Z,NIL), \ | |
| 1733 | QLF3(S_B,P_M,NIL), \ | |
| 1734 | QLF3(S_H,P_Z,NIL), \ | |
| 1735 | QLF3(S_H,P_M,NIL), \ | |
| 1736 | QLF3(S_S,P_Z,NIL), \ | |
| 1737 | QLF3(S_S,P_M,NIL), \ | |
| 1738 | QLF3(S_D,P_Z,NIL), \ | |
| 1739 | QLF3(S_D,P_M,NIL), \ | |
| 1740 | } | |
| 1741 | #define OP_SVE_VPV_BHSD \ | |
| 1742 | { \ | |
| 1743 | QLF3(S_B,P_Z,S_B), \ | |
| 1744 | QLF3(S_B,P_M,S_B), \ | |
| 1745 | QLF3(S_H,P_Z,S_H), \ | |
| 1746 | QLF3(S_H,P_M,S_H), \ | |
| 1747 | QLF3(S_S,P_Z,S_S), \ | |
| 1748 | QLF3(S_S,P_M,S_S), \ | |
| 1749 | QLF3(S_D,P_Z,S_D), \ | |
| 1750 | QLF3(S_D,P_M,S_D), \ | |
| 1751 | } | |
| 1752 | #define OP_SVE_VRR_BHSD \ | |
| 1753 | { \ | |
| 1754 | QLF3(S_B,W,W), \ | |
| 1755 | QLF3(S_H,W,W), \ | |
| 1756 | QLF3(S_S,W,W), \ | |
| 1757 | QLF3(S_D,X,X), \ | |
| 1758 | } | |
| 1759 | #define OP_SVE_VRU_BHSD \ | |
| 1760 | { \ | |
| 1761 | QLF3(S_B,W,NIL), \ | |
| 1762 | QLF3(S_H,W,NIL), \ | |
| 1763 | QLF3(S_S,W,NIL), \ | |
| 1764 | QLF3(S_D,X,NIL), \ | |
| 1765 | } | |
| 1766 | #define OP_SVE_VR_BHSD \ | |
| 1767 | { \ | |
| 1768 | QLF2(S_B,W), \ | |
| 1769 | QLF2(S_H,W), \ | |
| 1770 | QLF2(S_S,W), \ | |
| 1771 | QLF2(S_D,X), \ | |
| 1772 | } | |
| 1773 | #define OP_SVE_VUR_BHSD \ | |
| 1774 | { \ | |
| 1775 | QLF3(S_B,NIL,W), \ | |
| 1776 | QLF3(S_H,NIL,W), \ | |
| 1777 | QLF3(S_S,NIL,W), \ | |
| 1778 | QLF3(S_D,NIL,X), \ | |
| 1779 | } | |
| 1780 | #define OP_SVE_VUU_BHSD \ | |
| 1781 | { \ | |
| 1782 | QLF3(S_B,NIL,NIL), \ | |
| 1783 | QLF3(S_H,NIL,NIL), \ | |
| 1784 | QLF3(S_S,NIL,NIL), \ | |
| 1785 | QLF3(S_D,NIL,NIL), \ | |
| 1786 | } | |
| 1787 | #define OP_SVE_VUVV_BHSD \ | |
| 1788 | { \ | |
| 1789 | QLF4(S_B,NIL,S_B,S_B), \ | |
| 1790 | QLF4(S_H,NIL,S_H,S_H), \ | |
| 1791 | QLF4(S_S,NIL,S_S,S_S), \ | |
| 1792 | QLF4(S_D,NIL,S_D,S_D), \ | |
| 1793 | } | |
| 582e12bf | 1794 | #define OP_SVE_VUVV_HSD \ |
| c0890d26 | 1795 | { \ |
| 582e12bf | 1796 | QLF4(S_H,NIL,S_H,S_H), \ |
| c0890d26 RS |
1797 | QLF4(S_S,NIL,S_S,S_S), \ |
| 1798 | QLF4(S_D,NIL,S_D,S_D), \ | |
| 1799 | } | |
| 1800 | #define OP_SVE_VUV_BHSD \ | |
| 1801 | { \ | |
| 1802 | QLF3(S_B,NIL,S_B), \ | |
| 1803 | QLF3(S_H,NIL,S_H), \ | |
| 1804 | QLF3(S_S,NIL,S_S), \ | |
| 1805 | QLF3(S_D,NIL,S_D), \ | |
| 1806 | } | |
| 582e12bf RS |
1807 | #define OP_SVE_VUV_HSD \ |
| 1808 | { \ | |
| 1809 | QLF3(S_H,NIL,S_H), \ | |
| 1810 | QLF3(S_S,NIL,S_S), \ | |
| 1811 | QLF3(S_D,NIL,S_D), \ | |
| 1812 | } | |
| c0890d26 RS |
1813 | #define OP_SVE_VUV_SD \ |
| 1814 | { \ | |
| 1815 | QLF3(S_S,NIL,S_S), \ | |
| 1816 | QLF3(S_D,NIL,S_D), \ | |
| 1817 | } | |
| 1818 | #define OP_SVE_VU_BHSD \ | |
| 1819 | { \ | |
| 1820 | QLF2(S_B,NIL), \ | |
| 1821 | QLF2(S_H,NIL), \ | |
| 1822 | QLF2(S_S,NIL), \ | |
| 1823 | QLF2(S_D,NIL), \ | |
| 1824 | } | |
| 1825 | #define OP_SVE_VU_HSD \ | |
| 1826 | { \ | |
| 1827 | QLF2(S_H,NIL), \ | |
| 1828 | QLF2(S_S,NIL), \ | |
| 1829 | QLF2(S_D,NIL), \ | |
| 1830 | } | |
| 582e12bf | 1831 | #define OP_SVE_VU_HSD \ |
| c0890d26 | 1832 | { \ |
| 582e12bf | 1833 | QLF2(S_H,NIL), \ |
| c0890d26 RS |
1834 | QLF2(S_S,NIL), \ |
| 1835 | QLF2(S_D,NIL), \ | |
| 1836 | } | |
| 1837 | #define OP_SVE_VVD_BHS \ | |
| 1838 | { \ | |
| 1839 | QLF3(S_B,S_B,S_D), \ | |
| 1840 | QLF3(S_H,S_H,S_D), \ | |
| 1841 | QLF3(S_S,S_S,S_D), \ | |
| 1842 | } | |
| 1843 | #define OP_SVE_VVU_BHSD \ | |
| 1844 | { \ | |
| 1845 | QLF3(S_B,S_B,NIL), \ | |
| 1846 | QLF3(S_H,S_H,NIL), \ | |
| 1847 | QLF3(S_S,S_S,NIL), \ | |
| 1848 | QLF3(S_D,S_D,NIL), \ | |
| 1849 | } | |
| 582e12bf RS |
1850 | #define OP_SVE_VVVU_H \ |
| 1851 | { \ | |
| 1852 | QLF4(S_H,S_H,S_H,NIL), \ | |
| 1853 | } | |
| 1854 | #define OP_SVE_VVVU_S \ | |
| c0890d26 RS |
1855 | { \ |
| 1856 | QLF4(S_S,S_S,S_S,NIL), \ | |
| 582e12bf RS |
1857 | } |
| 1858 | #define OP_SVE_VVVU_HSD \ | |
| 1859 | { \ | |
| 1860 | QLF4(S_H,S_H,S_H,NIL), \ | |
| 1861 | QLF4(S_S,S_S,S_S,NIL), \ | |
| c0890d26 RS |
1862 | QLF4(S_D,S_D,S_D,NIL), \ |
| 1863 | } | |
| 1864 | #define OP_SVE_VVV_BHSD \ | |
| 1865 | { \ | |
| 1866 | QLF3(S_B,S_B,S_B), \ | |
| 1867 | QLF3(S_H,S_H,S_H), \ | |
| 1868 | QLF3(S_S,S_S,S_S), \ | |
| 1869 | QLF3(S_D,S_D,S_D), \ | |
| 1870 | } | |
| 582e12bf RS |
1871 | #define OP_SVE_VVV_D \ |
| 1872 | { \ | |
| 1873 | QLF3(S_D,S_D,S_D), \ | |
| 1874 | } | |
| 1875 | #define OP_SVE_VVV_D_H \ | |
| 1876 | { \ | |
| 1877 | QLF3(S_D,S_H,S_H), \ | |
| 1878 | } | |
| 1879 | #define OP_SVE_VVV_H \ | |
| c0890d26 | 1880 | { \ |
| 582e12bf RS |
1881 | QLF3(S_H,S_H,S_H), \ |
| 1882 | } | |
| 1883 | #define OP_SVE_VVV_HSD \ | |
| 1884 | { \ | |
| 1885 | QLF3(S_H,S_H,S_H), \ | |
| c0890d26 RS |
1886 | QLF3(S_S,S_S,S_S), \ |
| 1887 | QLF3(S_D,S_D,S_D), \ | |
| 1888 | } | |
| 582e12bf RS |
1889 | #define OP_SVE_VVV_S \ |
| 1890 | { \ | |
| 1891 | QLF3(S_S,S_S,S_S), \ | |
| 1892 | } | |
| 1893 | #define OP_SVE_VVV_S_B \ | |
| 1894 | { \ | |
| 1895 | QLF3(S_S,S_B,S_B), \ | |
| 1896 | } | |
| 1897 | #define OP_SVE_VVV_SD_BH \ | |
| 1898 | { \ | |
| 1899 | QLF3(S_S,S_B,S_B), \ | |
| 1900 | QLF3(S_D,S_H,S_H), \ | |
| 1901 | } | |
| c0890d26 RS |
1902 | #define OP_SVE_VV_BHSD \ |
| 1903 | { \ | |
| 1904 | QLF2(S_B,S_B), \ | |
| 1905 | QLF2(S_H,S_H), \ | |
| 1906 | QLF2(S_S,S_S), \ | |
| 1907 | QLF2(S_D,S_D), \ | |
| 1908 | } | |
| 582e12bf RS |
1909 | #define OP_SVE_VV_BHSDQ \ |
| 1910 | { \ | |
| 1911 | QLF2(S_B,S_B), \ | |
| 1912 | QLF2(S_H,S_H), \ | |
| 1913 | QLF2(S_S,S_S), \ | |
| 1914 | QLF2(S_D,S_D), \ | |
| 1915 | QLF2(S_Q,S_Q), \ | |
| 1916 | } | |
| 1917 | #define OP_SVE_VV_HSD \ | |
| 1918 | { \ | |
| 1919 | QLF2(S_H,S_H), \ | |
| 1920 | QLF2(S_S,S_S), \ | |
| 1921 | QLF2(S_D,S_D), \ | |
| 1922 | } | |
| c0890d26 RS |
1923 | #define OP_SVE_VV_HSD_BHS \ |
| 1924 | { \ | |
| 1925 | QLF2(S_H,S_B), \ | |
| 1926 | QLF2(S_S,S_H), \ | |
| 1927 | QLF2(S_D,S_S), \ | |
| 1928 | } | |
| 1929 | #define OP_SVE_VV_SD \ | |
| 1930 | { \ | |
| 1931 | QLF2(S_S,S_S), \ | |
| 1932 | QLF2(S_D,S_D), \ | |
| 1933 | } | |
| 1934 | #define OP_SVE_VWW_BHSD \ | |
| 1935 | { \ | |
| 1936 | QLF3(S_B,W,W), \ | |
| 1937 | QLF3(S_H,W,W), \ | |
| 1938 | QLF3(S_S,W,W), \ | |
| 1939 | QLF3(S_D,W,W), \ | |
| 1940 | } | |
| 1941 | #define OP_SVE_VXX_BHSD \ | |
| 1942 | { \ | |
| 1943 | QLF3(S_B,X,X), \ | |
| 1944 | QLF3(S_H,X,X), \ | |
| 1945 | QLF3(S_S,X,X), \ | |
| 1946 | QLF3(S_D,X,X), \ | |
| 1947 | } | |
| 1948 | #define OP_SVE_VZVD_BHS \ | |
| 1949 | { \ | |
| 1950 | QLF4(S_B,P_Z,S_B,S_D), \ | |
| 1951 | QLF4(S_H,P_Z,S_H,S_D), \ | |
| 1952 | QLF4(S_S,P_Z,S_S,S_D), \ | |
| 1953 | } | |
| 1954 | #define OP_SVE_VZVU_BHSD \ | |
| 1955 | { \ | |
| 1956 | QLF4(S_B,P_Z,S_B,NIL), \ | |
| 1957 | QLF4(S_H,P_Z,S_H,NIL), \ | |
| 1958 | QLF4(S_S,P_Z,S_S,NIL), \ | |
| 1959 | QLF4(S_D,P_Z,S_D,NIL), \ | |
| 1960 | } | |
| 1961 | #define OP_SVE_VZVV_BHSD \ | |
| 1962 | { \ | |
| 1963 | QLF4(S_B,P_Z,S_B,S_B), \ | |
| 1964 | QLF4(S_H,P_Z,S_H,S_H), \ | |
| 1965 | QLF4(S_S,P_Z,S_S,S_S), \ | |
| 1966 | QLF4(S_D,P_Z,S_D,S_D), \ | |
| 1967 | } | |
| 582e12bf | 1968 | #define OP_SVE_VZVV_HSD \ |
| c0890d26 | 1969 | { \ |
| 582e12bf | 1970 | QLF4(S_H,P_Z,S_H,S_H), \ |
| c0890d26 RS |
1971 | QLF4(S_S,P_Z,S_S,S_S), \ |
| 1972 | QLF4(S_D,P_Z,S_D,S_D), \ | |
| 1973 | } | |
| 582e12bf | 1974 | #define OP_SVE_VZV_HSD \ |
| c0890d26 | 1975 | { \ |
| 582e12bf | 1976 | QLF3(S_H,P_Z,S_H), \ |
| c0890d26 RS |
1977 | QLF3(S_S,P_Z,S_S), \ |
| 1978 | QLF3(S_D,P_Z,S_D), \ | |
| 1979 | } | |
| 582e12bf | 1980 | #define OP_SVE_V_HSD \ |
| c0890d26 | 1981 | { \ |
| 582e12bf | 1982 | QLF1(S_H), \ |
| c0890d26 RS |
1983 | QLF1(S_S), \ |
| 1984 | QLF1(S_D), \ | |
| 1985 | } | |
| 1986 | #define OP_SVE_WU \ | |
| 1987 | { \ | |
| 1988 | QLF2(W,NIL), \ | |
| 1989 | } | |
| 1990 | #define OP_SVE_WV_BHSD \ | |
| 1991 | { \ | |
| 1992 | QLF2(W,S_B), \ | |
| 1993 | QLF2(W,S_H), \ | |
| 1994 | QLF2(W,S_S), \ | |
| 1995 | QLF2(W,S_D), \ | |
| 1996 | } | |
| 1997 | #define OP_SVE_XU \ | |
| 1998 | { \ | |
| 1999 | QLF2(X,NIL), \ | |
| 2000 | } | |
| 2001 | #define OP_SVE_XUV_BHSD \ | |
| 2002 | { \ | |
| 2003 | QLF3(X,NIL,S_B), \ | |
| 2004 | QLF3(X,NIL,S_H), \ | |
| 2005 | QLF3(X,NIL,S_S), \ | |
| 2006 | QLF3(X,NIL,S_D), \ | |
| 2007 | } | |
| 2008 | #define OP_SVE_XVW_BHSD \ | |
| 2009 | { \ | |
| 2010 | QLF3(X,S_B,W), \ | |
| 2011 | QLF3(X,S_H,W), \ | |
| 2012 | QLF3(X,S_S,W), \ | |
| 2013 | QLF3(X,S_D,W), \ | |
| 2014 | } | |
| 2015 | #define OP_SVE_XV_BHSD \ | |
| 2016 | { \ | |
| 2017 | QLF2(X,S_B), \ | |
| 2018 | QLF2(X,S_H), \ | |
| 2019 | QLF2(X,S_S), \ | |
| 2020 | QLF2(X,S_D), \ | |
| 2021 | } | |
| 2022 | #define OP_SVE_XWU \ | |
| 2023 | { \ | |
| 2024 | QLF3(X,W,NIL), \ | |
| 2025 | } | |
| 2026 | #define OP_SVE_XXU \ | |
| 2027 | { \ | |
| 2028 | QLF3(X,X,NIL), \ | |
| 2029 | } | |
| 65a55fbb TC |
2030 | /* e.g. UDOT <Vd>.2S, <Vn>.8B, <Vm>.8B. */ |
| 2031 | #define QL_V3DOT \ | |
| 2032 | { \ | |
| 2033 | QLF3(V_2S, V_8B, V_8B), \ | |
| 2034 | QLF3(V_4S, V_16B, V_16B),\ | |
| 2035 | } | |
| 2036 | ||
| 2037 | /* e.g. UDOT <Vd>.2S, <Vn>.8B, <Vm>.4B[<index>]. */ | |
| 2038 | #define QL_V2DOT \ | |
| 2039 | { \ | |
| 00c2093f TC |
2040 | QLF3(V_2S, V_8B, S_4B),\ |
| 2041 | QLF3(V_4S, V_16B, S_4B),\ | |
| 65a55fbb | 2042 | } |
| 1a7ed57c TC |
2043 | |
| 2044 | /* e.g. SHA512H <Qd>, <Qn>, <Vm>.2D\f. */ | |
| 2045 | #define QL_SHA512UPT \ | |
| 2046 | { \ | |
| 2047 | QLF3(S_Q, S_Q, V_2D), \ | |
| 2048 | } | |
| 2049 | ||
| 2050 | /* e.g. SHA512SU0 <Vd.2D>, <Vn>.2D\f. */ | |
| 2051 | #define QL_V2SAME2D \ | |
| 2052 | { \ | |
| 2053 | QLF2(V_2D, V_2D), \ | |
| 2054 | } | |
| 2055 | ||
| 2056 | /* e.g. SHA512SU1 <Vd>.2D, <Vn>.2D, <Vm>.2D>. */ | |
| 2057 | #define QL_V3SAME2D \ | |
| 2058 | { \ | |
| 2059 | QLF3(V_2D, V_2D, V_2D), \ | |
| 2060 | } | |
| 2061 | ||
| 2062 | /* e.g. EOR3 <Vd>.16B, <Vn>.16B, <Vm>.16B, <Va>.16B. */ | |
| 2063 | #define QL_V4SAME16B \ | |
| 2064 | { \ | |
| 2065 | QLF4(V_16B, V_16B, V_16B, V_16B), \ | |
| 2066 | } | |
| 2067 | ||
| 2068 | /* e.g. SM3SS1 <Vd>.4S, <Vn>.4S, <Vm>.4S, <Va>.4S. */ | |
| 2069 | #define QL_V4SAME4S \ | |
| 2070 | { \ | |
| 2071 | QLF4(V_4S, V_4S, V_4S, V_4S), \ | |
| 2072 | } | |
| 2073 | ||
| 2074 | /* e.g. XAR <Vd>.2D, <Vn>.2D, <Vm>.2D, #<imm6>. */ | |
| 2075 | #define QL_XAR \ | |
| 2076 | { \ | |
| 2077 | QLF4(V_2D, V_2D, V_2D, imm_0_63), \ | |
| 2078 | } | |
| 2079 | ||
| 2080 | /* e.g. SM3TT1A <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>]. */ | |
| 2081 | #define QL_SM3TT \ | |
| 2082 | { \ | |
| 2083 | QLF3(V_4S, V_4S, S_S),\ | |
| 2084 | } | |
| 2085 | ||
| 2086 | /* e.g. FMLAL <Vd>.2S, <Vn>.2H, <Vm>.2H. */ | |
| 2087 | #define QL_V3FML2S \ | |
| 2088 | { \ | |
| 2089 | QLF3(V_2S, V_2H, V_2H),\ | |
| 2090 | } | |
| 2091 | ||
| 2092 | /* e.g. FMLAL <Vd>.4S, <Vn>.4H, <Vm>.4H. */ | |
| 2093 | #define QL_V3FML4S \ | |
| 2094 | { \ | |
| 2095 | QLF3(V_4S, V_4H, V_4H),\ | |
| 2096 | } | |
| 2097 | ||
| 2098 | /* e.g. FMLAL <Vd>.2S, <Vn>.2H, <Vm>.H[<index>]. */ | |
| 2099 | #define QL_V2FML2S \ | |
| 2100 | { \ | |
| 2101 | QLF3(V_2S, V_2H, S_H),\ | |
| 2102 | } | |
| 2103 | ||
| 2104 | /* e.g. FMLAL <Vd>.4S, <Vn>.4H, <Vm>.H[<index>]. */ | |
| 2105 | #define QL_V2FML4S \ | |
| 2106 | { \ | |
| 2107 | QLF3(V_4S, V_4H, S_H),\ | |
| 2108 | } | |
| 2109 | ||
| 2110 | /* e.g. RMIF <Xn>, #<shift>, #<mask>. */ | |
| 2111 | #define QL_RMIF \ | |
| 2112 | { \ | |
| 2113 | QLF3(X, imm_0_63, imm_0_15),\ | |
| 2114 | } | |
| 2115 | ||
| 2116 | /* e.g. SETF8 <Wn>. */ | |
| 2117 | #define QL_SETF \ | |
| 2118 | { \ | |
| 2119 | QLF1(W), \ | |
| 2120 | } | |
| 2121 | ||
| 2122 | /* e.g. STLURB <Wt>, [<Xn|SP>{,#<simm>}]. */ | |
| 2123 | #define QL_STLW \ | |
| 2124 | { \ | |
| 2125 | QLF2(W, NIL), \ | |
| 2126 | } | |
| 2127 | ||
| 2128 | /* e.g. STLURB <Xt>, [<Xn|SP>{,#<simm>}]. */ | |
| 2129 | #define QL_STLX \ | |
| 2130 | { \ | |
| 2131 | QLF2(X, NIL), \ | |
| 2132 | } | |
| a06ea964 NC |
2133 | \f |
| 2134 | /* Opcode table. */ | |
| 2135 | ||
| 2136 | static const aarch64_feature_set aarch64_feature_v8 = | |
| 2137 | AARCH64_FEATURE (AARCH64_FEATURE_V8, 0); | |
| 2138 | static const aarch64_feature_set aarch64_feature_fp = | |
| 2139 | AARCH64_FEATURE (AARCH64_FEATURE_FP, 0); | |
| 2140 | static const aarch64_feature_set aarch64_feature_simd = | |
| 2141 | AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0); | |
| 2142 | static const aarch64_feature_set aarch64_feature_crypto = | |
| c0e7cef7 | 2143 | AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO | AARCH64_FEATURE_AES |
| fadfa6b0 | 2144 | | AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0); |
| e60bb1dd YZ |
2145 | static const aarch64_feature_set aarch64_feature_crc = |
| 2146 | AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0); | |
| ee804238 JW |
2147 | static const aarch64_feature_set aarch64_feature_lse = |
| 2148 | AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0); | |
| 290806fd MW |
2149 | static const aarch64_feature_set aarch64_feature_lor = |
| 2150 | AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0); | |
| 9e1f0fa7 MW |
2151 | static const aarch64_feature_set aarch64_feature_rdma = |
| 2152 | AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0); | |
| c8a6db6f MW |
2153 | static const aarch64_feature_set aarch64_feature_ras = |
| 2154 | AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0); | |
| d685192a MW |
2155 | static const aarch64_feature_set aarch64_feature_v8_2 = |
| 2156 | AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0); | |
| 3bd894a7 MW |
2157 | static const aarch64_feature_set aarch64_feature_fp_f16 = |
| 2158 | AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0); | |
| 40d16a76 MW |
2159 | static const aarch64_feature_set aarch64_feature_simd_f16 = |
| 2160 | AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_SIMD, 0); | |
| 1e6f4800 MW |
2161 | static const aarch64_feature_set aarch64_feature_stat_profile = |
| 2162 | AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0); | |
| c0890d26 RS |
2163 | static const aarch64_feature_set aarch64_feature_sve = |
| 2164 | AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0); | |
| 8787d804 SN |
2165 | static const aarch64_feature_set aarch64_feature_v8_3 = |
| 2166 | AARCH64_FEATURE (AARCH64_FEATURE_V8_3, 0); | |
| ccfc90a3 SN |
2167 | static const aarch64_feature_set aarch64_feature_fp_v8_3 = |
| 2168 | AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_FP, 0); | |
| f482d304 RS |
2169 | static const aarch64_feature_set aarch64_feature_compnum = |
| 2170 | AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0); | |
| d74d4880 SN |
2171 | static const aarch64_feature_set aarch64_feature_rcpc = |
| 2172 | AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0); | |
| 65a55fbb TC |
2173 | static const aarch64_feature_set aarch64_feature_dotprod = |
| 2174 | AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_DOTPROD, 0); | |
| c0e7cef7 NC |
2175 | static const aarch64_feature_set aarch64_feature_sha2 = |
| 2176 | AARCH64_FEATURE (AARCH64_FEATURE_V8 | AARCH64_FEATURE_SHA2, 0); | |
| 2177 | static const aarch64_feature_set aarch64_feature_aes = | |
| 2178 | AARCH64_FEATURE (AARCH64_FEATURE_V8 | AARCH64_FEATURE_AES, 0); | |
| b6b9ca0c TC |
2179 | static const aarch64_feature_set aarch64_feature_v8_4 = |
| 2180 | AARCH64_FEATURE (AARCH64_FEATURE_V8_4, 0); | |
| 2181 | static const aarch64_feature_set aarch64_feature_crypto_v8_2 = | |
| fadfa6b0 TC |
2182 | AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_CRYPTO |
| 2183 | | AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0); | |
| b6b9ca0c | 2184 | static const aarch64_feature_set aarch64_feature_sm4 = |
| fadfa6b0 TC |
2185 | AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_SM4 |
| 2186 | | AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0); | |
| b6b9ca0c TC |
2187 | static const aarch64_feature_set aarch64_feature_sha3 = |
| 2188 | AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_SHA2 | |
| fadfa6b0 | 2189 | | AARCH64_FEATURE_SHA3 | AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0); |
| b6b9ca0c | 2190 | static const aarch64_feature_set aarch64_feature_fp_16_v8_2 = |
| d0f7791c TC |
2191 | AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_F16_FML |
| 2192 | | AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0); | |
| 70d56181 SD |
2193 | static const aarch64_feature_set aarch64_feature_v8_5 = |
| 2194 | AARCH64_FEATURE (AARCH64_FEATURE_V8_5, 0); | |
| 13c60ad7 SD |
2195 | static const aarch64_feature_set aarch64_feature_flagmanip = |
| 2196 | AARCH64_FEATURE (AARCH64_FEATURE_FLAGMANIP, 0); | |
| 2197 | static const aarch64_feature_set aarch64_feature_frintts = | |
| 2198 | AARCH64_FEATURE (AARCH64_FEATURE_FRINTTS, 0); | |
| 68dfbb92 SD |
2199 | static const aarch64_feature_set aarch64_feature_sb = |
| 2200 | AARCH64_FEATURE (AARCH64_FEATURE_SB, 0); | |
| 2ac435d4 SD |
2201 | static const aarch64_feature_set aarch64_feature_predres = |
| 2202 | AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0); | |
| ff605452 SD |
2203 | static const aarch64_feature_set aarch64_feature_bti = |
| 2204 | AARCH64_FEATURE (AARCH64_FEATURE_BTI, 0); | |
| 73b605ec SD |
2205 | static const aarch64_feature_set aarch64_feature_memtag = |
| 2206 | AARCH64_FEATURE (AARCH64_FEATURE_V8_5 | AARCH64_FEATURE_MEMTAG, 0); | |
| b83b4b13 SD |
2207 | static const aarch64_feature_set aarch64_feature_tme = |
| 2208 | AARCH64_FEATURE (AARCH64_FEATURE_TME, 0); | |
| 7ce2460a MM |
2209 | static const aarch64_feature_set aarch64_feature_sve2 = |
| 2210 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0); | |
| 2211 | static const aarch64_feature_set aarch64_feature_sve2aes = | |
| 2212 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_AES, 0); | |
| 2213 | static const aarch64_feature_set aarch64_feature_sve2sha3 = | |
| 2214 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_SHA3, 0); | |
| 2215 | static const aarch64_feature_set aarch64_feature_sve2sm4 = | |
| 2216 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_SM4, 0); | |
| 2217 | static const aarch64_feature_set aarch64_feature_sve2bitperm = | |
| 2218 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_BITPERM, 0); | |
| 70d56181 | 2219 | |
| a06ea964 | 2220 | |
| 4bd13cde NC |
2221 | #define CORE &aarch64_feature_v8 |
| 2222 | #define FP &aarch64_feature_fp | |
| 2223 | #define SIMD &aarch64_feature_simd | |
| 2224 | #define CRYPTO &aarch64_feature_crypto | |
| 2225 | #define CRC &aarch64_feature_crc | |
| 2226 | #define LSE &aarch64_feature_lse | |
| 2227 | #define LOR &aarch64_feature_lor | |
| 2228 | #define RDMA &aarch64_feature_rdma | |
| 2229 | #define FP_F16 &aarch64_feature_fp_f16 | |
| 40d16a76 | 2230 | #define SIMD_F16 &aarch64_feature_simd_f16 |
| 4bd13cde | 2231 | #define RAS &aarch64_feature_ras |
| 1e6f4800 | 2232 | #define STAT_PROFILE &aarch64_feature_stat_profile |
| 4bd13cde | 2233 | #define ARMV8_2 &aarch64_feature_v8_2 |
| c0890d26 | 2234 | #define SVE &aarch64_feature_sve |
| 8787d804 | 2235 | #define ARMV8_3 &aarch64_feature_v8_3 |
| ccfc90a3 | 2236 | #define FP_V8_3 &aarch64_feature_fp_v8_3 |
| f482d304 | 2237 | #define COMPNUM &aarch64_feature_compnum |
| d74d4880 | 2238 | #define RCPC &aarch64_feature_rcpc |
| c0e7cef7 NC |
2239 | #define SHA2 &aarch64_feature_sha2 |
| 2240 | #define AES &aarch64_feature_aes | |
| b6b9ca0c TC |
2241 | #define ARMV8_4 &aarch64_feature_v8_4 |
| 2242 | #define SHA3 &aarch64_feature_sha3 | |
| 2243 | #define SM4 &aarch64_feature_sm4 | |
| 2244 | #define CRYPTO_V8_2 &aarch64_feature_crypto_v8_2 | |
| 2245 | #define FP_F16_V8_2 &aarch64_feature_fp_16_v8_2 | |
| 65a55fbb | 2246 | #define DOTPROD &aarch64_feature_dotprod |
| 70d56181 | 2247 | #define ARMV8_5 &aarch64_feature_v8_5 |
| 13c60ad7 SD |
2248 | #define FLAGMANIP &aarch64_feature_flagmanip |
| 2249 | #define FRINTTS &aarch64_feature_frintts | |
| 68dfbb92 | 2250 | #define SB &aarch64_feature_sb |
| 2ac435d4 | 2251 | #define PREDRES &aarch64_feature_predres |
| ff605452 | 2252 | #define BTI &aarch64_feature_bti |
| 73b605ec | 2253 | #define MEMTAG &aarch64_feature_memtag |
| b83b4b13 | 2254 | #define TME &aarch64_feature_tme |
| 7ce2460a MM |
2255 | #define SVE2 &aarch64_feature_sve2 |
| 2256 | #define SVE2_AES &aarch64_feature_sve2aes | |
| 2257 | #define SVE2_SHA3 &aarch64_feature_sve2sha3 | |
| 2258 | #define SVE2_SM4 &aarch64_feature_sve2sm4 | |
| 2259 | #define SVE2_BITPERM &aarch64_feature_sve2bitperm | |
| 4bd13cde | 2260 | |
| 9d30b0bd | 2261 | #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
| eae424ae | 2262 | { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 9d30b0bd | 2263 | #define __FP_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
| eae424ae | 2264 | { NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 9d30b0bd | 2265 | #define SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
| eae424ae | 2266 | { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 6456d318 TC |
2267 | #define _SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,VERIFIER) \ |
| 2268 | { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, VERIFIER } | |
| 4bd13cde | 2269 | #define CRYP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2270 | { NAME, OPCODE, MASK, CLASS, 0, CRYPTO, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 4bd13cde | 2271 | #define _CRC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2272 | { NAME, OPCODE, MASK, CLASS, 0, CRC, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 4bd13cde | 2273 | #define _LSE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2274 | { NAME, OPCODE, MASK, CLASS, 0, LSE, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 4bd13cde | 2275 | #define _LOR_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2276 | { NAME, OPCODE, MASK, CLASS, 0, LOR, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 4bd13cde | 2277 | #define RDMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2278 | { NAME, OPCODE, MASK, CLASS, 0, RDMA, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 4bd13cde | 2279 | #define FF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2280 | { NAME, OPCODE, MASK, CLASS, 0, FP_F16, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 4bd13cde | 2281 | #define SF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2282 | { NAME, OPCODE, MASK, CLASS, 0, SIMD_F16, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 344bde0a | 2283 | #define V8_2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
| eae424ae | 2284 | { NAME, OPCODE, MASK, CLASS, OP, ARMV8_2, OPS, QUALS, FLAGS, 0, 0, NULL } |
| c0890d26 RS |
2285 | #define _SVE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ |
| 2286 | { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \ | |
| eae424ae TC |
2287 | FLAGS | F_STRICT, 0, TIED, NULL } |
| 2288 | #define _SVE_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ | |
| 2289 | { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \ | |
| 2290 | FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } | |
| 8787d804 | 2291 | #define V8_3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2292 | { NAME, OPCODE, MASK, CLASS, 0, ARMV8_3, OPS, QUALS, FLAGS, 0, 0, NULL } |
| f482d304 | 2293 | #define CNUM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
| eae424ae | 2294 | { NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS, 0, 0, NULL } |
| d74d4880 | 2295 | #define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2296 | { NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, 0, NULL } |
| c0e7cef7 | 2297 | #define SHA2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2298 | { NAME, OPCODE, MASK, CLASS, 0, SHA2, OPS, QUALS, FLAGS, 0, 0, NULL } |
| c0e7cef7 | 2299 | #define AES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2300 | { NAME, OPCODE, MASK, CLASS, 0, AES, OPS, QUALS, FLAGS, 0, 0, NULL } |
| b6b9ca0c | 2301 | #define V8_4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2302 | { NAME, OPCODE, MASK, CLASS, 0, ARMV8_4, OPS, QUALS, FLAGS, 0, 0, NULL } |
| b6b9ca0c TC |
2303 | #define CRYPTO_V8_2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| 2304 | { NAME, OPCODE, MASK, CLASS, 0, CRYPTO_V8_2, OPS, QUALS, FLAGS, 0, NULL } | |
| 2305 | #define SHA3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ | |
| eae424ae | 2306 | { NAME, OPCODE, MASK, CLASS, 0, SHA3, OPS, QUALS, FLAGS, 0, 0, NULL } |
| b6b9ca0c | 2307 | #define SM4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2308 | { NAME, OPCODE, MASK, CLASS, 0, SM4, OPS, QUALS, FLAGS, 0, 0, NULL } |
| b6b9ca0c | 2309 | #define FP16_V8_2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2310 | { NAME, OPCODE, MASK, CLASS, 0, FP_F16_V8_2, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 65a55fbb | 2311 | #define DOT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| eae424ae | 2312 | { NAME, OPCODE, MASK, CLASS, 0, DOTPROD, OPS, QUALS, FLAGS, 0, 0, NULL } |
| 70d56181 SD |
2313 | #define V8_5_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| 2314 | { NAME, OPCODE, MASK, CLASS, 0, ARMV8_5, OPS, QUALS, FLAGS, 0, 0, NULL } | |
| 13c60ad7 SD |
2315 | #define FLAGMANIP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| 2316 | { NAME, OPCODE, MASK, CLASS, 0, FLAGMANIP, OPS, QUALS, FLAGS, 0, 0, NULL } | |
| 2317 | #define FRINTTS_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ | |
| 2318 | { NAME, OPCODE, MASK, CLASS, 0, FRINTTS, OPS, QUALS, FLAGS, 0, 0, NULL } | |
| 68dfbb92 SD |
2319 | #define SB_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| 2320 | { NAME, OPCODE, MASK, CLASS, 0, SB, OPS, QUALS, FLAGS, 0, 0, NULL } | |
| 2ac435d4 SD |
2321 | #define PREDRES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| 2322 | { NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL } | |
| ff605452 SD |
2323 | #define BTI_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| 2324 | { NAME, OPCODE, MASK, CLASS, 0, BTI, OPS, QUALS, FLAGS, 0, 0, NULL } | |
| 73b605ec SD |
2325 | #define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| 2326 | { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS, 0, 0, NULL } | |
| b83b4b13 SD |
2327 | #define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
| 2328 | { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS, 0, 0, NULL } | |
| 7ce2460a MM |
2329 | #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ |
| 2330 | { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \ | |
| 2331 | FLAGS | F_STRICT, 0, TIED, NULL } | |
| 2332 | #define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ | |
| 2333 | { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \ | |
| 2334 | FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } | |
| 2335 | #define SVE2AES_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ | |
| 2336 | { NAME, OPCODE, MASK, CLASS, OP, SVE2_AES, OPS, QUALS, \ | |
| 2337 | FLAGS | F_STRICT, 0, TIED, NULL } | |
| 2338 | #define SVE2SHA3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ | |
| 2339 | { NAME, OPCODE, MASK, CLASS, OP, SVE2_SHA3, OPS, QUALS, \ | |
| 2340 | FLAGS | F_STRICT, 0, TIED, NULL } | |
| 2341 | #define SVE2SM4_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ | |
| 2342 | { NAME, OPCODE, MASK, CLASS, OP, SVE2_SM4, OPS, QUALS, \ | |
| 2343 | FLAGS | F_STRICT, 0, TIED, NULL } | |
| 2344 | #define SVE2SM4_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ | |
| 2345 | { NAME, OPCODE, MASK, CLASS, OP, SVE2_SM4, OPS, QUALS, \ | |
| 2346 | FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } | |
| 2347 | #define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ | |
| 2348 | { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \ | |
| 2349 | FLAGS | F_STRICT, 0, TIED, NULL } | |
| a06ea964 NC |
2350 | |
| 2351 | struct aarch64_opcode aarch64_opcode_table[] = | |
| 2352 | { | |
| 2353 | /* Add/subtract (with carry). */ | |
| 9d30b0bd RS |
2354 | CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), |
| 2355 | CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), | |
| 2356 | CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
| 2357 | CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), | |
| 2358 | CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
| 2359 | CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), | |
| a06ea964 | 2360 | /* Add/subtract (extended register). */ |
| 9d30b0bd RS |
2361 | CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF), |
| 2362 | CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF), | |
| 2363 | CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), | |
| 2364 | CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF), | |
| 2365 | CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF), | |
| 2366 | CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), | |
| a06ea964 | 2367 | /* Add/subtract (immediate). */ |
| 5ce912d8 | 2368 | CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), |
| 9d30b0bd RS |
2369 | CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF), |
| 2370 | CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), | |
| 2371 | CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), | |
| 2372 | CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF), | |
| 2373 | CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), | |
| 2374 | CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), | |
| 193614f2 SD |
2375 | MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0), |
| 2376 | MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0), | |
| a06ea964 | 2377 | /* Add/subtract (shifted register). */ |
| 9d30b0bd RS |
2378 | CORE_INSN ("add", 0x0b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), |
| 2379 | CORE_INSN ("adds", 0x2b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
| 2380 | CORE_INSN ("cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), | |
| 2381 | CORE_INSN ("sub", 0x4b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
| 2382 | CORE_INSN ("neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), | |
| 2383 | CORE_INSN ("subs", 0x6b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
| 514cd3a0 | 2384 | CORE_INSN ("cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF | F_P1), |
| 9d30b0bd | 2385 | CORE_INSN ("negs", 0x6b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), |
| a06ea964 | 2386 | /* AdvSIMD across lanes. */ |
| 9d30b0bd RS |
2387 | SIMD_INSN ("saddlv", 0x0e303800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ), |
| 2388 | SIMD_INSN ("smaxv", 0x0e30a800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), | |
| 2389 | SIMD_INSN ("sminv", 0x0e31a800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), | |
| 2390 | SIMD_INSN ("addv", 0x0e31b800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), | |
| 2391 | SIMD_INSN ("uaddlv", 0x2e303800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ), | |
| 2392 | SIMD_INSN ("umaxv", 0x2e30a800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), | |
| 2393 | SIMD_INSN ("uminv", 0x2e31a800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), | |
| 2394 | SIMD_INSN ("fmaxnmv",0x2e30c800, 0xbfbffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), | |
| 4bd13cde | 2395 | SF16_INSN ("fmaxnmv",0x0e30c800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), |
| 9d30b0bd | 2396 | SIMD_INSN ("fmaxv", 0x2e30f800, 0xbfbffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), |
| 4bd13cde | 2397 | SF16_INSN ("fmaxv", 0x0e30f800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), |
| 9d30b0bd | 2398 | SIMD_INSN ("fminnmv",0x2eb0c800, 0xbfbffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), |
| 4bd13cde | 2399 | SF16_INSN ("fminnmv",0x0eb0c800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), |
| 9d30b0bd | 2400 | SIMD_INSN ("fminv", 0x2eb0f800, 0xbfbffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), |
| 4bd13cde | 2401 | SF16_INSN ("fminv", 0x0eb0f800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), |
| a06ea964 | 2402 | /* AdvSIMD three different. */ |
| 9d30b0bd RS |
2403 | SIMD_INSN ("saddl", 0x0e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| 2404 | SIMD_INSN ("saddl2", 0x4e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2405 | SIMD_INSN ("saddw", 0x0e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), | |
| 2406 | SIMD_INSN ("saddw2", 0x4e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), | |
| 2407 | SIMD_INSN ("ssubl", 0x0e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2408 | SIMD_INSN ("ssubl2", 0x4e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2409 | SIMD_INSN ("ssubw", 0x0e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), | |
| 2410 | SIMD_INSN ("ssubw2", 0x4e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), | |
| 2411 | SIMD_INSN ("addhn", 0x0e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), | |
| 2412 | SIMD_INSN ("addhn2", 0x4e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), | |
| 2413 | SIMD_INSN ("sabal", 0x0e205000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2414 | SIMD_INSN ("sabal2", 0x4e205000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2415 | SIMD_INSN ("subhn", 0x0e206000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), | |
| 2416 | SIMD_INSN ("subhn2", 0x4e206000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), | |
| 2417 | SIMD_INSN ("sabdl", 0x0e207000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2418 | SIMD_INSN ("sabdl2", 0x4e207000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2419 | SIMD_INSN ("smlal", 0x0e208000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2420 | SIMD_INSN ("smlal2", 0x4e208000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2421 | SIMD_INSN ("sqdmlal", 0x0e209000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ), | |
| 2422 | SIMD_INSN ("sqdmlal2",0x4e209000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ), | |
| 2423 | SIMD_INSN ("smlsl", 0x0e20a000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2424 | SIMD_INSN ("smlsl2", 0x4e20a000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2425 | SIMD_INSN ("sqdmlsl", 0x0e20b000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ), | |
| 2426 | SIMD_INSN ("sqdmlsl2",0x4e20b000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ), | |
| 2427 | SIMD_INSN ("smull", 0x0e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2428 | SIMD_INSN ("smull2", 0x4e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2429 | SIMD_INSN ("sqdmull", 0x0e20d000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ), | |
| 2430 | SIMD_INSN ("sqdmull2",0x4e20d000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ), | |
| 2431 | SIMD_INSN ("pmull", 0x0e20e000, 0xffe0fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGB, 0), | |
| c0e7cef7 | 2432 | AES_INSN ("pmull", 0x0ee0e000, 0xffe0fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGD, 0), |
| 9d30b0bd | 2433 | SIMD_INSN ("pmull2", 0x4e20e000, 0xffe0fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGB2, 0), |
| c0e7cef7 | 2434 | AES_INSN ("pmull2", 0x4ee0e000, 0xffe0fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGD2, 0), |
| 9d30b0bd RS |
2435 | SIMD_INSN ("uaddl", 0x2e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| 2436 | SIMD_INSN ("uaddl2", 0x6e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2437 | SIMD_INSN ("uaddw", 0x2e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), | |
| 2438 | SIMD_INSN ("uaddw2", 0x6e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), | |
| 2439 | SIMD_INSN ("usubl", 0x2e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2440 | SIMD_INSN ("usubl2", 0x6e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2441 | SIMD_INSN ("usubw", 0x2e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), | |
| 2442 | SIMD_INSN ("usubw2", 0x6e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), | |
| 2443 | SIMD_INSN ("raddhn", 0x2e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), | |
| 2444 | SIMD_INSN ("raddhn2", 0x6e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), | |
| 2445 | SIMD_INSN ("uabal", 0x2e205000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2446 | SIMD_INSN ("uabal2", 0x6e205000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2447 | SIMD_INSN ("rsubhn", 0x2e206000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), | |
| 2448 | SIMD_INSN ("rsubhn2", 0x6e206000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), | |
| 2449 | SIMD_INSN ("uabdl", 0x2e207000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2450 | SIMD_INSN ("uabdl2", 0x6e207000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2451 | SIMD_INSN ("umlal", 0x2e208000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2452 | SIMD_INSN ("umlal2", 0x6e208000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2453 | SIMD_INSN ("umlsl", 0x2e20a000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2454 | SIMD_INSN ("umlsl2", 0x6e20a000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| 2455 | SIMD_INSN ("umull", 0x2e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
| 2456 | SIMD_INSN ("umull2", 0x6e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
| a06ea964 | 2457 | /* AdvSIMD vector x indexed element. */ |
| 369c9167 TC |
2458 | SIMD_INSN ("smlal", 0x0f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), |
| 2459 | SIMD_INSN ("smlal2", 0x4f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 45a28947 TC |
2460 | SIMD_INSN ("sqdmlal", 0x0f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), |
| 2461 | SIMD_INSN ("sqdmlal2",0x4f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 2462 | SIMD_INSN ("smlsl", 0x0f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
| 2463 | SIMD_INSN ("smlsl2", 0x4f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 2464 | SIMD_INSN ("sqdmlsl", 0x0f007000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
| 2465 | SIMD_INSN ("sqdmlsl2",0x4f007000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 2466 | SIMD_INSN ("mul", 0x0f008000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
| 2467 | SIMD_INSN ("smull", 0x0f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
| 2468 | SIMD_INSN ("smull2", 0x4f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 2469 | SIMD_INSN ("sqdmull", 0x0f00b000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
| 2470 | SIMD_INSN ("sqdmull2",0x4f00b000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 2471 | SIMD_INSN ("sqdmulh", 0x0f00c000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
| 2472 | SIMD_INSN ("sqrdmulh",0x0f00d000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
| 6456d318 | 2473 | _SIMD_INSN ("fmla", 0x0f801000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ, VERIFIER (elem_sd)), |
| 369c9167 | 2474 | SF16_INSN ("fmla", 0x0f001000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), |
| 6456d318 | 2475 | _SIMD_INSN ("fmls", 0x0f805000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ, VERIFIER (elem_sd)), |
| 369c9167 | 2476 | SF16_INSN ("fmls", 0x0f005000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), |
| 6456d318 | 2477 | _SIMD_INSN ("fmul", 0x0f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ, VERIFIER (elem_sd)), |
| 369c9167 | 2478 | SF16_INSN ("fmul", 0x0f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), |
| 45a28947 TC |
2479 | SIMD_INSN ("mla", 0x2f000000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), |
| 2480 | SIMD_INSN ("umlal", 0x2f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
| 2481 | SIMD_INSN ("umlal2", 0x6f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 2482 | SIMD_INSN ("mls", 0x2f004000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
| 2483 | SIMD_INSN ("umlsl", 0x2f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
| 2484 | SIMD_INSN ("umlsl2", 0x6f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 2485 | SIMD_INSN ("umull", 0x2f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
| 2486 | SIMD_INSN ("umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
| 6456d318 | 2487 | _SIMD_INSN ("fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ, VERIFIER (elem_sd)), |
| 369c9167 TC |
2488 | SF16_INSN ("fmulx", 0x2f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), |
| 2489 | RDMA_INSN ("sqrdmlah",0x2f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
| 2490 | RDMA_INSN ("sqrdmlsh",0x2f00f000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
| f482d304 | 2491 | CNUM_INSN ("fcmla", 0x2f001000, 0xbf009400, asimdelem, OP_FCMLA_ELEM, OP4 (Vd, Vn, Em, IMM_ROT2), QL_ELEMENT_ROT, F_SIZEQ), |
| a06ea964 | 2492 | /* AdvSIMD EXT. */ |
| 9d30b0bd | 2493 | SIMD_INSN ("ext", 0x2e000000, 0xbfe08400, asimdext, 0, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ), |
| a06ea964 | 2494 | /* AdvSIMD modified immediate. */ |
| 9d30b0bd RS |
2495 | SIMD_INSN ("movi", 0x0f000400, 0xbff89c00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), |
| 2496 | SIMD_INSN ("orr", 0x0f001400, 0xbff89c00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), | |
| 2497 | SIMD_INSN ("movi", 0x0f008400, 0xbff8dc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), | |
| 2498 | SIMD_INSN ("orr", 0x0f009400, 0xbff8dc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), | |
| 2499 | SIMD_INSN ("movi", 0x0f00c400, 0xbff8ec00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ), | |
| 2500 | SIMD_INSN ("movi", 0x0f00e400, 0xbff8fc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_B, F_SIZEQ), | |
| 2501 | SIMD_INSN ("fmov", 0x0f00f400, 0xbff8fc00, asimdimm, 0, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_S, F_SIZEQ), | |
| 4bd13cde | 2502 | SF16_INSN ("fmov", 0x0f00fc00, 0xbff8fc00, asimdimm, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_H, F_SIZEQ), |
| 9d30b0bd RS |
2503 | SIMD_INSN ("mvni", 0x2f000400, 0xbff89c00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), |
| 2504 | SIMD_INSN ("bic", 0x2f001400, 0xbff89c00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), | |
| 2505 | SIMD_INSN ("mvni", 0x2f008400, 0xbff8dc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), | |
| 2506 | SIMD_INSN ("bic", 0x2f009400, 0xbff8dc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), | |
| 2507 | SIMD_INSN ("mvni", 0x2f00c400, 0xbff8ec00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ), | |
| 2508 | SIMD_INSN ("movi", 0x2f00e400, 0xfff8fc00, asimdimm, 0, OP2 (Sd, SIMD_IMM), QL_SIMD_IMM_D, F_SIZEQ), | |
| 2509 | SIMD_INSN ("movi", 0x6f00e400, 0xfff8fc00, asimdimm, 0, OP2 (Vd, SIMD_IMM), QL_SIMD_IMM_V2D, F_SIZEQ), | |
| 2510 | SIMD_INSN ("fmov", 0x6f00f400, 0xfff8fc00, asimdimm, 0, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_V2D, F_SIZEQ), | |
| a06ea964 | 2511 | /* AdvSIMD copy. */ |
| 9d30b0bd RS |
2512 | SIMD_INSN ("dup", 0x0e000400, 0xbfe0fc00, asimdins, 0, OP2 (Vd, En), QL_DUP_VX, F_T), |
| 2513 | SIMD_INSN ("dup", 0x0e000c00, 0xbfe0fc00, asimdins, 0, OP2 (Vd, Rn), QL_DUP_VR, F_T), | |
| 2514 | SIMD_INSN ("smov",0x0e002c00, 0xbfe0fc00, asimdins, 0, OP2 (Rd, En), QL_SMOV, F_GPRSIZE_IN_Q), | |
| 2515 | SIMD_INSN ("umov",0x0e003c00, 0xbfe0fc00, asimdins, 0, OP2 (Rd, En), QL_UMOV, F_HAS_ALIAS | F_GPRSIZE_IN_Q), | |
| 2516 | SIMD_INSN ("mov", 0x0e003c00, 0xbfe0fc00, asimdins, 0, OP2 (Rd, En), QL_MOV, F_ALIAS | F_GPRSIZE_IN_Q), | |
| 2517 | SIMD_INSN ("ins", 0x4e001c00, 0xffe0fc00, asimdins, 0, OP2 (Ed, Rn), QL_INS_XR, F_HAS_ALIAS), | |
| 2518 | SIMD_INSN ("mov", 0x4e001c00, 0xffe0fc00, asimdins, 0, OP2 (Ed, Rn), QL_INS_XR, F_ALIAS), | |
| 2519 | SIMD_INSN ("ins", 0x6e000400, 0xffe08400, asimdins, 0, OP2 (Ed, En), QL_S_2SAME, F_HAS_ALIAS), | |
| 2520 | SIMD_INSN ("mov", 0x6e000400, 0xffe08400, asimdins, 0, OP2 (Ed, En), QL_S_2SAME, F_ALIAS), | |
| a06ea964 | 2521 | /* AdvSIMD two-reg misc. */ |
| 13c60ad7 SD |
2522 | FRINTTS_INSN ("frint32z", 0x0e21e800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 2523 | FRINTTS_INSN ("frint32x", 0x2e21e800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
| 2524 | FRINTTS_INSN ("frint64z", 0x0e21f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
| 2525 | FRINTTS_INSN ("frint64x", 0x2e21f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
| 9d30b0bd RS |
2526 | SIMD_INSN ("rev64", 0x0e200800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ), |
| 2527 | SIMD_INSN ("rev16", 0x0e201800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ), | |
| 2528 | SIMD_INSN ("saddlp",0x0e202800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), | |
| 2529 | SIMD_INSN ("suqadd",0x0e203800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
| 2530 | SIMD_INSN ("cls", 0x0e204800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ), | |
| 2531 | SIMD_INSN ("cnt", 0x0e205800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ), | |
| 2532 | SIMD_INSN ("sadalp",0x0e206800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), | |
| 2533 | SIMD_INSN ("sqabs", 0x0e207800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
| 2534 | SIMD_INSN ("cmgt", 0x0e208800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), | |
| 2535 | SIMD_INSN ("cmeq", 0x0e209800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), | |
| 2536 | SIMD_INSN ("cmlt", 0x0e20a800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), | |
| 2537 | SIMD_INSN ("abs", 0x0e20b800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
| 2538 | SIMD_INSN ("xtn", 0x0e212800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), | |
| 2539 | SIMD_INSN ("xtn2", 0x4e212800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), | |
| 2540 | SIMD_INSN ("sqxtn", 0xe214800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), | |
| 2541 | SIMD_INSN ("sqxtn2",0x4e214800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), | |
| 5ce912d8 RS |
2542 | SIMD_INSN ("fcvtn", 0x0e216800, 0xffbffc00, asimdmisc, OP_FCVTN, OP2 (Vd, Vn), QL_V2NARRHS, F_MISC), |
| 2543 | SIMD_INSN ("fcvtn2", 0x4e216800, 0xffbffc00, asimdmisc, OP_FCVTN2, OP2 (Vd, Vn), QL_V2NARRHS2, F_MISC), | |
| 2544 | SIMD_INSN ("fcvtl", 0x0e217800, 0xffbffc00, asimdmisc, OP_FCVTL, OP2 (Vd, Vn), QL_V2LONGHS, F_MISC), | |
| 2545 | SIMD_INSN ("fcvtl2", 0x4e217800, 0xffbffc00, asimdmisc, OP_FCVTL2, OP2 (Vd, Vn), QL_V2LONGHS2, F_MISC), | |
| 9d30b0bd | 2546 | SIMD_INSN ("frintn", 0x0e218800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2547 | SF16_INSN ("frintn", 0x0e798800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2548 | SIMD_INSN ("frintm", 0x0e219800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2549 | SF16_INSN ("frintm", 0x0e799800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2550 | SIMD_INSN ("fcvtns", 0x0e21a800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2551 | SF16_INSN ("fcvtns", 0x0e79a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2552 | SIMD_INSN ("fcvtms", 0x0e21b800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2553 | SF16_INSN ("fcvtms", 0x0e79b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2554 | SIMD_INSN ("fcvtas", 0x0e21c800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2555 | SF16_INSN ("fcvtas", 0x0e79c800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2556 | SIMD_INSN ("scvtf", 0x0e21d800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2557 | SF16_INSN ("scvtf", 0x0e79d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2558 | SIMD_INSN ("fcmgt", 0x0ea0c800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2559 | SF16_INSN ("fcmgt", 0x0ef8c800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2560 | SIMD_INSN ("fcmeq", 0x0ea0d800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2561 | SF16_INSN ("fcmeq", 0x0ef8d800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2562 | SIMD_INSN ("fcmlt", 0x0ea0e800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2563 | SF16_INSN ("fcmlt", 0x0ef8e800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2564 | SIMD_INSN ("fabs", 0x0ea0f800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2565 | SF16_INSN ("fabs", 0x0ef8f800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2566 | SIMD_INSN ("frintp", 0x0ea18800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2567 | SF16_INSN ("frintp", 0x0ef98800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2568 | SIMD_INSN ("frintz", 0x0ea19800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2569 | SF16_INSN ("frintz", 0x0ef99800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2570 | SIMD_INSN ("fcvtps", 0x0ea1a800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2571 | SF16_INSN ("fcvtps", 0x0ef9a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2572 | SIMD_INSN ("fcvtzs", 0x0ea1b800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2573 | SF16_INSN ("fcvtzs", 0x0ef9b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd RS |
2574 | SIMD_INSN ("urecpe", 0x0ea1c800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ), |
| 2575 | SIMD_INSN ("frecpe", 0x0ea1d800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
| 4bd13cde | 2576 | SF16_INSN ("frecpe", 0x0ef9d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd RS |
2577 | SIMD_INSN ("rev32", 0x2e200800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEBH, F_SIZEQ), |
| 2578 | SIMD_INSN ("uaddlp", 0x2e202800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), | |
| 2579 | SIMD_INSN ("usqadd", 0x2e203800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
| 2580 | SIMD_INSN ("clz", 0x2e204800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ), | |
| 2581 | SIMD_INSN ("uadalp", 0x2e206800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), | |
| 2582 | SIMD_INSN ("sqneg", 0x2e207800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
| 2583 | SIMD_INSN ("cmge", 0x2e208800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), | |
| 2584 | SIMD_INSN ("cmle", 0x2e209800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), | |
| 2585 | SIMD_INSN ("neg", 0x2e20b800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
| 2586 | SIMD_INSN ("sqxtun", 0x2e212800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), | |
| 2587 | SIMD_INSN ("sqxtun2",0x6e212800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), | |
| 2588 | SIMD_INSN ("shll", 0x2e213800, 0xff3ffc00, asimdmisc, 0, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS, F_SIZEQ), | |
| 2589 | SIMD_INSN ("shll2", 0x6e213800, 0xff3ffc00, asimdmisc, 0, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS2, F_SIZEQ), | |
| 2590 | SIMD_INSN ("uqxtn", 0x2e214800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), | |
| 2591 | SIMD_INSN ("uqxtn2", 0x6e214800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), | |
| 2592 | SIMD_INSN ("fcvtxn", 0x2e616800, 0xfffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRS, 0), | |
| 2593 | SIMD_INSN ("fcvtxn2",0x6e616800, 0xfffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRS2, 0), | |
| 2594 | SIMD_INSN ("frinta", 0x2e218800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
| 4bd13cde | 2595 | SF16_INSN ("frinta", 0x2e798800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2596 | SIMD_INSN ("frintx", 0x2e219800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2597 | SF16_INSN ("frintx", 0x2e799800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2598 | SIMD_INSN ("fcvtnu", 0x2e21a800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2599 | SF16_INSN ("fcvtnu", 0x2e79a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2600 | SIMD_INSN ("fcvtmu", 0x2e21b800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2601 | SF16_INSN ("fcvtmu", 0x2e79b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2602 | SIMD_INSN ("fcvtau", 0x2e21c800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2603 | SF16_INSN ("fcvtau", 0x2e79c800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2604 | SIMD_INSN ("ucvtf", 0x2e21d800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2605 | SF16_INSN ("ucvtf", 0x2e79d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd RS |
2606 | SIMD_INSN ("not", 0x2e205800, 0xbffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_HAS_ALIAS), |
| 2607 | SIMD_INSN ("mvn", 0x2e205800, 0xbffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_ALIAS), | |
| 2608 | SIMD_INSN ("rbit", 0x2e605800, 0xbffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ), | |
| 2609 | SIMD_INSN ("fcmge", 0x2ea0c800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), | |
| 4bd13cde | 2610 | SF16_INSN ("fcmge", 0x2ef8c800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2611 | SIMD_INSN ("fcmle", 0x2ea0d800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2612 | SF16_INSN ("fcmle", 0x2ef8d800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2613 | SIMD_INSN ("fneg", 0x2ea0f800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2614 | SF16_INSN ("fneg", 0x2ef8f800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2615 | SIMD_INSN ("frinti", 0x2ea19800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2616 | SF16_INSN ("frinti", 0x2ef99800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2617 | SIMD_INSN ("fcvtpu", 0x2ea1a800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2618 | SF16_INSN ("fcvtpu", 0x2ef9a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2619 | SIMD_INSN ("fcvtzu", 0x2ea1b800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2620 | SF16_INSN ("fcvtzu", 0x2ef9b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd RS |
2621 | SIMD_INSN ("ursqrte",0x2ea1c800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ), |
| 2622 | SIMD_INSN ("frsqrte",0x2ea1d800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
| 4bd13cde | 2623 | SF16_INSN ("frsqrte",0x2ef9d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| 9d30b0bd | 2624 | SIMD_INSN ("fsqrt", 0x2ea1f800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| 4bd13cde | 2625 | SF16_INSN ("fsqrt", 0x2ef9f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| a06ea964 | 2626 | /* AdvSIMD ZIP/UZP/TRN. */ |
| 9d30b0bd RS |
2627 | SIMD_INSN ("uzp1", 0xe001800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| 2628 | SIMD_INSN ("trn1", 0xe002800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2629 | SIMD_INSN ("zip1", 0xe003800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2630 | SIMD_INSN ("uzp2", 0xe005800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2631 | SIMD_INSN ("trn2", 0xe006800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2632 | SIMD_INSN ("zip2", 0xe007800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| a06ea964 | 2633 | /* AdvSIMD three same. */ |
| 9d30b0bd RS |
2634 | SIMD_INSN ("shadd", 0xe200400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| 2635 | SIMD_INSN ("sqadd", 0xe200c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2636 | SIMD_INSN ("srhadd", 0xe201400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2637 | SIMD_INSN ("shsub", 0xe202400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2638 | SIMD_INSN ("sqsub", 0xe202c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2639 | SIMD_INSN ("cmgt", 0xe203400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2640 | SIMD_INSN ("cmge", 0xe203c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2641 | SIMD_INSN ("sshl", 0xe204400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2642 | SIMD_INSN ("sqshl", 0xe204c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2643 | SIMD_INSN ("srshl", 0xe205400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2644 | SIMD_INSN ("sqrshl", 0xe205c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2645 | SIMD_INSN ("smax", 0xe206400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2646 | SIMD_INSN ("smin", 0xe206c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2647 | SIMD_INSN ("sabd", 0xe207400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2648 | SIMD_INSN ("saba", 0xe207c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2649 | SIMD_INSN ("add", 0xe208400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2650 | SIMD_INSN ("cmtst", 0xe208c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2651 | SIMD_INSN ("mla", 0xe209400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2652 | SIMD_INSN ("mul", 0xe209c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2653 | SIMD_INSN ("smaxp", 0xe20a400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2654 | SIMD_INSN ("sminp", 0xe20ac00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2655 | SIMD_INSN ("sqdmulh", 0xe20b400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), | |
| 2656 | SIMD_INSN ("addp", 0xe20bc00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2657 | SIMD_INSN ("fmaxnm", 0xe20c400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), | |
| 4bd13cde | 2658 | SF16_INSN ("fmaxnm", 0xe400400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2659 | SIMD_INSN ("fmla", 0xe20cc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2660 | SF16_INSN ("fmla", 0xe400c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2661 | SIMD_INSN ("fadd", 0xe20d400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2662 | SF16_INSN ("fadd", 0xe401400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2663 | SIMD_INSN ("fmulx", 0xe20dc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2664 | SF16_INSN ("fmulx", 0xe401c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2665 | SIMD_INSN ("fcmeq", 0xe20e400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2666 | SF16_INSN ("fcmeq", 0xe402400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2667 | SIMD_INSN ("fmax", 0xe20f400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2668 | SF16_INSN ("fmax", 0xe403400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2669 | SIMD_INSN ("frecps", 0xe20fc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2670 | SF16_INSN ("frecps", 0xe403c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd RS |
2671 | SIMD_INSN ("and", 0xe201c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
| 2672 | SIMD_INSN ("bic", 0xe601c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), | |
| 2673 | SIMD_INSN ("fminnm", 0xea0c400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), | |
| 4bd13cde | 2674 | SF16_INSN ("fminnm", 0xec00400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2675 | SIMD_INSN ("fmls", 0xea0cc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2676 | SF16_INSN ("fmls", 0xec00c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2677 | SIMD_INSN ("fsub", 0xea0d400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2678 | SF16_INSN ("fsub", 0xec01400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2679 | SIMD_INSN ("fmin", 0xea0f400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2680 | SF16_INSN ("fmin", 0xec03400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2681 | SIMD_INSN ("frsqrts", 0xea0fc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2682 | SF16_INSN ("frsqrts", 0xec03c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2683 | SIMD_INSN ("orr", 0xea01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_HAS_ALIAS | F_SIZEQ), |
| 5ce912d8 | 2684 | SIMD_INSN ("mov", 0xea01c00, 0xbfe0fc00, asimdsame, OP_MOV_V, OP2 (Vd, Vn), QL_V2SAMEB, F_ALIAS | F_CONV), |
| 9d30b0bd RS |
2685 | SIMD_INSN ("orn", 0xee01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
| 2686 | SIMD_INSN ("uhadd", 0x2e200400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2687 | SIMD_INSN ("uqadd", 0x2e200c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2688 | SIMD_INSN ("urhadd", 0x2e201400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2689 | SIMD_INSN ("uhsub", 0x2e202400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2690 | SIMD_INSN ("uqsub", 0x2e202c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2691 | SIMD_INSN ("cmhi", 0x2e203400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2692 | SIMD_INSN ("cmhs", 0x2e203c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2693 | SIMD_INSN ("ushl", 0x2e204400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2694 | SIMD_INSN ("uqshl", 0x2e204c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2695 | SIMD_INSN ("urshl", 0x2e205400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2696 | SIMD_INSN ("uqrshl", 0x2e205c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2697 | SIMD_INSN ("umax", 0x2e206400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2698 | SIMD_INSN ("umin", 0x2e206c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2699 | SIMD_INSN ("uabd", 0x2e207400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2700 | SIMD_INSN ("uaba", 0x2e207c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2701 | SIMD_INSN ("sub", 0x2e208400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2702 | SIMD_INSN ("cmeq", 0x2e208c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
| 2703 | SIMD_INSN ("mls", 0x2e209400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2704 | SIMD_INSN ("pmul", 0x2e209c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), | |
| 2705 | SIMD_INSN ("umaxp", 0x2e20a400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2706 | SIMD_INSN ("uminp", 0x2e20ac00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
| 2707 | SIMD_INSN ("sqrdmulh", 0x2e20b400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), | |
| 2708 | SIMD_INSN ("fmaxnmp", 0x2e20c400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), | |
| 4bd13cde | 2709 | SF16_INSN ("fmaxnmp", 0x2e400400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2710 | SIMD_INSN ("faddp", 0x2e20d400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2711 | SF16_INSN ("faddp", 0x2e401400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2712 | SIMD_INSN ("fmul", 0x2e20dc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2713 | SF16_INSN ("fmul", 0x2e401c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2714 | SIMD_INSN ("fcmge", 0x2e20e400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2715 | SF16_INSN ("fcmge", 0x2e402400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2716 | SIMD_INSN ("facge", 0x2e20ec00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2717 | SF16_INSN ("facge", 0x2e402c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2718 | SIMD_INSN ("fmaxp", 0x2e20f400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2719 | SF16_INSN ("fmaxp", 0x2e403400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2720 | SIMD_INSN ("fdiv", 0x2e20fc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2721 | SF16_INSN ("fdiv", 0x2e403c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd RS |
2722 | SIMD_INSN ("eor", 0x2e201c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
| 2723 | SIMD_INSN ("bsl", 0x2e601c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), | |
| 2724 | SIMD_INSN ("fminnmp", 0x2ea0c400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), | |
| 4bd13cde | 2725 | SF16_INSN ("fminnmp", 0x2ec00400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2726 | SIMD_INSN ("fabd", 0x2ea0d400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2727 | SF16_INSN ("fabd", 0x2ec01400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2728 | SIMD_INSN ("fcmgt", 0x2ea0e400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2729 | SF16_INSN ("fcmgt", 0x2ec02400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2730 | SIMD_INSN ("facgt", 0x2ea0ec00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2731 | SF16_INSN ("facgt", 0x2ec02c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd | 2732 | SIMD_INSN ("fminp", 0x2ea0f400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| 4bd13cde | 2733 | SF16_INSN ("fminp", 0x2ec03400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| 9d30b0bd RS |
2734 | SIMD_INSN ("bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
| 2735 | SIMD_INSN ("bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), | |
| 9e1f0fa7 | 2736 | /* AdvSIMD three same extension. */ |
| 10bba94b TC |
2737 | RDMA_INSN ("sqrdmlah",0x2e008400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), |
| 2738 | RDMA_INSN ("sqrdmlsh",0x2e008c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), | |
| f482d304 RS |
2739 | CNUM_INSN ("fcmla", 0x2e00c400, 0xbf20e400, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT1), QL_V3SAMEHSD_ROT, F_SIZEQ), |
| 2740 | CNUM_INSN ("fcadd", 0x2e00e400, 0xbf20ec00, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT3), QL_V3SAMEHSD_ROT, F_SIZEQ), | |
| a06ea964 | 2741 | /* AdvSIMD shift by immediate. */ |
| 9d30b0bd RS |
2742 | SIMD_INSN ("sshr", 0xf000400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), |
| 2743 | SIMD_INSN ("ssra", 0xf001400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
| 2744 | SIMD_INSN ("srshr", 0xf002400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
| 2745 | SIMD_INSN ("srsra", 0xf003400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
| 2746 | SIMD_INSN ("shl", 0xf005400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), | |
| 2747 | SIMD_INSN ("sqshl", 0xf007400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), | |
| 2748 | SIMD_INSN ("shrn", 0xf008400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
| 2749 | SIMD_INSN ("shrn2", 0x4f008400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
| 2750 | SIMD_INSN ("rshrn", 0xf008c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
| 2751 | SIMD_INSN ("rshrn2", 0x4f008c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
| 2752 | SIMD_INSN ("sqshrn", 0xf009400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
| 2753 | SIMD_INSN ("sqshrn2", 0x4f009400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
| 2754 | SIMD_INSN ("sqrshrn", 0xf009c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
| 2755 | SIMD_INSN ("sqrshrn2", 0x4f009c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
| 2756 | SIMD_INSN ("sshll", 0xf00a400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS), | |
| 5ce912d8 | 2757 | SIMD_INSN ("sxtl", 0xf00a400, 0xff87fc00, asimdshf, OP_SXTL, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV), |
| 9d30b0bd | 2758 | SIMD_INSN ("sshll2", 0x4f00a400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS), |
| 5ce912d8 | 2759 | SIMD_INSN ("sxtl2", 0x4f00a400, 0xff87fc00, asimdshf, OP_SXTL2, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV), |
| 9d30b0bd | 2760 | SIMD_INSN ("scvtf", 0xf00e400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), |
| 4bd13cde | 2761 | SF16_INSN ("scvtf", 0xf10e400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), |
| 9d30b0bd | 2762 | SIMD_INSN ("fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), |
| 4bd13cde | 2763 | SF16_INSN ("fcvtzs", 0xf10fc00, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), |
| 9d30b0bd RS |
2764 | SIMD_INSN ("ushr", 0x2f000400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), |
| 2765 | SIMD_INSN ("usra", 0x2f001400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
| 2766 | SIMD_INSN ("urshr", 0x2f002400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
| 2767 | SIMD_INSN ("ursra", 0x2f003400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
| 2768 | SIMD_INSN ("sri", 0x2f004400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
| 2769 | SIMD_INSN ("sli", 0x2f005400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), | |
| 2770 | SIMD_INSN ("sqshlu", 0x2f006400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), | |
| 2771 | SIMD_INSN ("uqshl", 0x2f007400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), | |
| 2772 | SIMD_INSN ("sqshrun", 0x2f008400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
| 2773 | SIMD_INSN ("sqshrun2", 0x6f008400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
| 2774 | SIMD_INSN ("sqrshrun", 0x2f008c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
| 2775 | SIMD_INSN ("sqrshrun2", 0x6f008c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
| 2776 | SIMD_INSN ("uqshrn", 0x2f009400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
| 2777 | SIMD_INSN ("uqshrn2", 0x6f009400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
| 2778 | SIMD_INSN ("uqrshrn", 0x2f009c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
| 2779 | SIMD_INSN ("uqrshrn2", 0x6f009c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
| 2780 | SIMD_INSN ("ushll", 0x2f00a400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS), | |
| 5ce912d8 | 2781 | SIMD_INSN ("uxtl", 0x2f00a400, 0xff87fc00, asimdshf, OP_UXTL, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV), |
| 9d30b0bd | 2782 | SIMD_INSN ("ushll2", 0x6f00a400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS), |
| 5ce912d8 | 2783 | SIMD_INSN ("uxtl2", 0x6f00a400, 0xff87fc00, asimdshf, OP_UXTL2, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV), |
| 9d30b0bd | 2784 | SIMD_INSN ("ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), |
| 4bd13cde | 2785 | SF16_INSN ("ucvtf", 0x2f10e400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), |
| 9d30b0bd | 2786 | SIMD_INSN ("fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), |
| 4bd13cde | 2787 | SF16_INSN ("fcvtzu", 0x2f10fc00, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), |
| a06ea964 | 2788 | /* AdvSIMD TBL/TBX. */ |
| 9d30b0bd RS |
2789 | SIMD_INSN ("tbl", 0xe000000, 0xbfe09c00, asimdtbl, 0, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ), |
| 2790 | SIMD_INSN ("tbx", 0xe001000, 0xbfe09c00, asimdtbl, 0, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ), | |
| a06ea964 | 2791 | /* AdvSIMD scalar three different. */ |
| 9d30b0bd RS |
2792 | SIMD_INSN ("sqdmlal", 0x5e209000, 0xff20fc00, asisddiff, 0, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE), |
| 2793 | SIMD_INSN ("sqdmlsl", 0x5e20b000, 0xff20fc00, asisddiff, 0, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE), | |
| 2794 | SIMD_INSN ("sqdmull", 0x5e20d000, 0xff20fc00, asisddiff, 0, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE), | |
| a06ea964 | 2795 | /* AdvSIMD scalar x indexed element. */ |
| 45a28947 TC |
2796 | SIMD_INSN ("sqdmlal", 0x5f003000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISDL_HS, F_SSIZE), |
| 2797 | SIMD_INSN ("sqdmlsl", 0x5f007000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISDL_HS, F_SSIZE), | |
| 2798 | SIMD_INSN ("sqdmull", 0x5f00b000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISDL_HS, F_SSIZE), | |
| 2799 | SIMD_INSN ("sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE), | |
| 2800 | SIMD_INSN ("sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE), | |
| 6456d318 | 2801 | _SIMD_INSN ("fmla", 0x5f801000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE, VERIFIER (elem_sd)), |
| 369c9167 | 2802 | SF16_INSN ("fmla", 0x5f001000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE), |
| 6456d318 | 2803 | _SIMD_INSN ("fmls", 0x5f805000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE, VERIFIER (elem_sd)), |
| 369c9167 | 2804 | SF16_INSN ("fmls", 0x5f005000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE), |
| 6456d318 | 2805 | _SIMD_INSN ("fmul", 0x5f809000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE, VERIFIER (elem_sd)), |
| 369c9167 | 2806 | SF16_INSN ("fmul", 0x5f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE), |
| 6456d318 | 2807 | _SIMD_INSN ("fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE, VERIFIER (elem_sd)), |
| 369c9167 TC |
2808 | SF16_INSN ("fmulx", 0x7f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE), |
| 2809 | RDMA_INSN ("sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE), | |
| 2810 | RDMA_INSN ("sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE), | |
| a06ea964 | 2811 | /* AdvSIMD load/store multiple structures. */ |
| 9d30b0bd RS |
2812 | SIMD_INSN ("st4", 0xc000000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)), |
| 2813 | SIMD_INSN ("st1", 0xc000000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), | |
| 2814 | SIMD_INSN ("st2", 0xc000000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)), | |
| 2815 | SIMD_INSN ("st3", 0xc000000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)), | |
| 2816 | SIMD_INSN ("ld4", 0xc400000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)), | |
| 2817 | SIMD_INSN ("ld1", 0xc400000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), | |
| 2818 | SIMD_INSN ("ld2", 0xc400000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)), | |
| 2819 | SIMD_INSN ("ld3", 0xc400000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)), | |
| a06ea964 | 2820 | /* AdvSIMD load/store multiple structures (post-indexed). */ |
| 9d30b0bd RS |
2821 | SIMD_INSN ("st4", 0xc800000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)), |
| 2822 | SIMD_INSN ("st1", 0xc800000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), | |
| 2823 | SIMD_INSN ("st2", 0xc800000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)), | |
| 2824 | SIMD_INSN ("st3", 0xc800000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)), | |
| 2825 | SIMD_INSN ("ld4", 0xcc00000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)), | |
| 2826 | SIMD_INSN ("ld1", 0xcc00000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), | |
| 2827 | SIMD_INSN ("ld2", 0xcc00000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)), | |
| 2828 | SIMD_INSN ("ld3", 0xcc00000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)), | |
| a06ea964 | 2829 | /* AdvSIMD load/store single structure. */ |
| 9d30b0bd RS |
2830 | SIMD_INSN ("st1", 0xd000000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)), |
| 2831 | SIMD_INSN ("st3", 0xd002000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)), | |
| 2832 | SIMD_INSN ("st2", 0xd200000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)), | |
| 2833 | SIMD_INSN ("st4", 0xd202000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)), | |
| 2834 | SIMD_INSN ("ld1", 0xd400000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)), | |
| 2835 | SIMD_INSN ("ld3", 0xd402000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)), | |
| 792f174f NC |
2836 | SIMD_INSN ("ld1r", 0xd40c000, 0xbffff000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), |
| 2837 | SIMD_INSN ("ld3r", 0xd40e000, 0xbffff000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)), | |
| 9d30b0bd RS |
2838 | SIMD_INSN ("ld2", 0xd600000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)), |
| 2839 | SIMD_INSN ("ld4", 0xd602000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)), | |
| 792f174f NC |
2840 | SIMD_INSN ("ld2r", 0xd60c000, 0xbffff000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)), |
| 2841 | SIMD_INSN ("ld4r", 0xd60e000, 0xbffff000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)), | |
| a06ea964 | 2842 | /* AdvSIMD load/store single structure (post-indexed). */ |
| 9d30b0bd RS |
2843 | SIMD_INSN ("st1", 0xd800000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)), |
| 2844 | SIMD_INSN ("st3", 0xd802000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)), | |
| 2845 | SIMD_INSN ("st2", 0xda00000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)), | |
| 2846 | SIMD_INSN ("st4", 0xda02000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)), | |
| 2847 | SIMD_INSN ("ld1", 0xdc00000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)), | |
| 2848 | SIMD_INSN ("ld3", 0xdc02000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)), | |
| 792f174f NC |
2849 | SIMD_INSN ("ld1r", 0xdc0c000, 0xbfe0f000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), |
| 2850 | SIMD_INSN ("ld3r", 0xdc0e000, 0xbfe0f000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)), | |
| 9d30b0bd RS |
2851 | SIMD_INSN ("ld2", 0xde00000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)), |
| 2852 | SIMD_INSN ("ld4", 0xde02000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)), | |
| 792f174f NC |
2853 | SIMD_INSN ("ld2r", 0xde0c000, 0xbfe0f000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)), |
| 2854 | SIMD_INSN ("ld4r", 0xde0e000, 0xbfe0f000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)), | |
| a06ea964 | 2855 | /* AdvSIMD scalar two-reg misc. */ |
| 9d30b0bd RS |
2856 | SIMD_INSN ("suqadd", 0x5e203800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE), |
| 2857 | SIMD_INSN ("sqabs", 0x5e207800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE), | |
| 2858 | SIMD_INSN ("cmgt", 0x5e208800, 0xff3ffc00, asisdmisc, 0, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), | |
| 2859 | SIMD_INSN ("cmeq", 0x5e209800, 0xff3ffc00, asisdmisc, 0, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), | |
| 2860 | SIMD_INSN ("cmlt", 0x5e20a800, 0xff3ffc00, asisdmisc, 0, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), | |
| 2861 | SIMD_INSN ("abs", 0x5e20b800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE), | |
| 2862 | SIMD_INSN ("sqxtn", 0x5e214800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE), | |
| 2863 | SIMD_INSN ("fcvtns", 0x5e21a800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), | |
| 4bd13cde | 2864 | SF16_INSN ("fcvtns", 0x5e79a800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2865 | SIMD_INSN ("fcvtms", 0x5e21b800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2866 | SF16_INSN ("fcvtms", 0x5e79b800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2867 | SIMD_INSN ("fcvtas", 0x5e21c800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2868 | SF16_INSN ("fcvtas", 0x5e79c800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2869 | SIMD_INSN ("scvtf", 0x5e21d800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2870 | SF16_INSN ("scvtf", 0x5e79d800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2871 | SIMD_INSN ("fcmgt", 0x5ea0c800, 0xffbffc00, asisdmisc, 0, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), |
| 4bd13cde | 2872 | SF16_INSN ("fcmgt", 0x5ef8c800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), |
| 9d30b0bd | 2873 | SIMD_INSN ("fcmeq", 0x5ea0d800, 0xffbffc00, asisdmisc, 0, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), |
| 4bd13cde | 2874 | SF16_INSN ("fcmeq", 0x5ef8d800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), |
| 9d30b0bd | 2875 | SIMD_INSN ("fcmlt", 0x5ea0e800, 0xffbffc00, asisdmisc, 0, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), |
| 4bd13cde | 2876 | SF16_INSN ("fcmlt", 0x5ef8e800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), |
| 9d30b0bd | 2877 | SIMD_INSN ("fcvtps", 0x5ea1a800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2878 | SF16_INSN ("fcvtps", 0x5ef9a800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2879 | SIMD_INSN ("fcvtzs", 0x5ea1b800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2880 | SF16_INSN ("fcvtzs", 0x5ef9b800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2881 | SIMD_INSN ("frecpe", 0x5ea1d800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2882 | SF16_INSN ("frecpe", 0x5ef9d800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2883 | SIMD_INSN ("frecpx", 0x5ea1f800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2884 | SF16_INSN ("frecpx", 0x5ef9f800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd RS |
2885 | SIMD_INSN ("usqadd", 0x7e203800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE), |
| 2886 | SIMD_INSN ("sqneg", 0x7e207800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE), | |
| 2887 | SIMD_INSN ("cmge", 0x7e208800, 0xff3ffc00, asisdmisc, 0, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), | |
| 2888 | SIMD_INSN ("cmle", 0x7e209800, 0xff3ffc00, asisdmisc, 0, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), | |
| 2889 | SIMD_INSN ("neg", 0x7e20b800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE), | |
| 2890 | SIMD_INSN ("sqxtun", 0x7e212800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE), | |
| 2891 | SIMD_INSN ("uqxtn", 0x7e214800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE), | |
| 5ce912d8 | 2892 | SIMD_INSN ("fcvtxn", 0x7e216800, 0xffbffc00, asisdmisc, OP_FCVTXN_S, OP2 (Sd, Sn), QL_SISD_NARROW_S, F_MISC), |
| 9d30b0bd | 2893 | SIMD_INSN ("fcvtnu", 0x7e21a800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2894 | SF16_INSN ("fcvtnu", 0x7e79a800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2895 | SIMD_INSN ("fcvtmu", 0x7e21b800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2896 | SF16_INSN ("fcvtmu", 0x7e79b800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2897 | SIMD_INSN ("fcvtau", 0x7e21c800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2898 | SF16_INSN ("fcvtau", 0x7e79c800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2899 | SIMD_INSN ("ucvtf", 0x7e21d800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2900 | SF16_INSN ("ucvtf", 0x7e79d800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2901 | SIMD_INSN ("fcmge", 0x7ea0c800, 0xffbffc00, asisdmisc, 0, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), |
| 4bd13cde | 2902 | SF16_INSN ("fcmge", 0x7ef8c800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), |
| 9d30b0bd | 2903 | SIMD_INSN ("fcmle", 0x7ea0d800, 0xffbffc00, asisdmisc, 0, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), |
| 4bd13cde | 2904 | SF16_INSN ("fcmle", 0x7ef8d800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), |
| 9d30b0bd | 2905 | SIMD_INSN ("fcvtpu", 0x7ea1a800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2906 | SF16_INSN ("fcvtpu", 0x7ef9a800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_SISD_FCMP_H_0, F_SSIZE), |
| 9d30b0bd | 2907 | SIMD_INSN ("fcvtzu", 0x7ea1b800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2908 | SF16_INSN ("fcvtzu", 0x7ef9b800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| 9d30b0bd | 2909 | SIMD_INSN ("frsqrte", 0x7ea1d800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
| 4bd13cde | 2910 | SF16_INSN ("frsqrte", 0x7ef9d800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
| a06ea964 | 2911 | /* AdvSIMD scalar copy. */ |
| 9d30b0bd RS |
2912 | SIMD_INSN ("dup", 0x5e000400, 0xffe0fc00, asisdone, 0, OP2 (Sd, En), QL_S_2SAME, F_HAS_ALIAS), |
| 2913 | SIMD_INSN ("mov", 0x5e000400, 0xffe0fc00, asisdone, 0, OP2 (Sd, En), QL_S_2SAME, F_ALIAS), | |
| a06ea964 | 2914 | /* AdvSIMD scalar pairwise. */ |
| 9d30b0bd RS |
2915 | SIMD_INSN ("addp", 0x5e31b800, 0xff3ffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR_D, F_SIZEQ), |
| 2916 | SIMD_INSN ("fmaxnmp", 0x7e30c800, 0xffbffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), | |
| 4bd13cde | 2917 | SF16_INSN ("fmaxnmp", 0x5e30c800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), |
| 9d30b0bd | 2918 | SIMD_INSN ("faddp", 0x7e30d800, 0xffbffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), |
| 4bd13cde | 2919 | SF16_INSN ("faddp", 0x5e30d800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), |
| 9d30b0bd | 2920 | SIMD_INSN ("fmaxp", 0x7e30f800, 0xffbffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), |
| 4bd13cde | 2921 | SF16_INSN ("fmaxp", 0x5e30f800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), |
| 9d30b0bd | 2922 | SIMD_INSN ("fminnmp", 0x7eb0c800, 0xffbffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), |
| 4bd13cde | 2923 | SF16_INSN ("fminnmp", 0x5eb0c800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), |
| 9d30b0bd | 2924 | SIMD_INSN ("fminp", 0x7eb0f800, 0xffbffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), |
| 4bd13cde | 2925 | SF16_INSN ("fminp", 0x5eb0f800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), |
| a06ea964 | 2926 | /* AdvSIMD scalar three same. */ |
| 9d30b0bd RS |
2927 | SIMD_INSN ("sqadd", 0x5e200c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), |
| 2928 | SIMD_INSN ("sqsub", 0x5e202c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
| 2929 | SIMD_INSN ("sqshl", 0x5e204c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
| 2930 | SIMD_INSN ("sqrshl", 0x5e205c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
| 2931 | SIMD_INSN ("sqdmulh", 0x5e20b400, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE), | |
| 2932 | SIMD_INSN ("fmulx", 0x5e20dc00, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), | |
| 4bd13cde | 2933 | SF16_INSN ("fmulx", 0x5e401c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd | 2934 | SIMD_INSN ("fcmeq", 0x5e20e400, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
| 4bd13cde | 2935 | SF16_INSN ("fcmeq", 0x5e402400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd | 2936 | SIMD_INSN ("frecps", 0x5e20fc00, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
| 4bd13cde | 2937 | SF16_INSN ("frecps", 0x5e403c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd | 2938 | SIMD_INSN ("frsqrts", 0x5ea0fc00, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
| 4bd13cde | 2939 | SF16_INSN ("frsqrts", 0x5ec03c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd RS |
2940 | SIMD_INSN ("cmgt", 0x5ee03400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), |
| 2941 | SIMD_INSN ("cmge", 0x5ee03c00, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2942 | SIMD_INSN ("sshl", 0x5ee04400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2943 | SIMD_INSN ("srshl", 0x5ee05400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2944 | SIMD_INSN ("add", 0x5ee08400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2945 | SIMD_INSN ("cmtst", 0x5ee08c00, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2946 | SIMD_INSN ("uqadd", 0x7e200c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
| 2947 | SIMD_INSN ("uqsub", 0x7e202c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
| 2948 | SIMD_INSN ("uqshl", 0x7e204c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
| 2949 | SIMD_INSN ("uqrshl", 0x7e205c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
| 2950 | SIMD_INSN ("sqrdmulh", 0x7e20b400, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE), | |
| 2951 | SIMD_INSN ("fcmge", 0x7e20e400, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), | |
| 4bd13cde | 2952 | SF16_INSN ("fcmge", 0x7e402400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd | 2953 | SIMD_INSN ("facge", 0x7e20ec00, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
| 4bd13cde | 2954 | SF16_INSN ("facge", 0x7e402c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd | 2955 | SIMD_INSN ("fabd", 0x7ea0d400, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
| 4bd13cde | 2956 | SF16_INSN ("fabd", 0x7ec01400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd | 2957 | SIMD_INSN ("fcmgt", 0x7ea0e400, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
| 4bd13cde | 2958 | SF16_INSN ("fcmgt", 0x7ec02400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd | 2959 | SIMD_INSN ("facgt", 0x7ea0ec00, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
| 4bd13cde | 2960 | SF16_INSN ("facgt", 0x7ec02c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
| 9d30b0bd RS |
2961 | SIMD_INSN ("cmhi", 0x7ee03400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), |
| 2962 | SIMD_INSN ("cmhs", 0x7ee03c00, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2963 | SIMD_INSN ("ushl", 0x7ee04400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2964 | SIMD_INSN ("urshl", 0x7ee05400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2965 | SIMD_INSN ("sub", 0x7ee08400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 2966 | SIMD_INSN ("cmeq", 0x7ee08c00, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
| 9e1f0fa7 | 2967 | /* AdvSIMDs scalar three same extension. */ |
| 4bd13cde NC |
2968 | RDMA_INSN ("sqrdmlah", 0x7e008400, 0xff20fc00, asimdsame, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE), |
| 2969 | RDMA_INSN ("sqrdmlsh", 0x7e008c00, 0xff20fc00, asimdsame, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE), | |
| a06ea964 | 2970 | /* AdvSIMD scalar shift by immediate. */ |
| 9d30b0bd RS |
2971 | SIMD_INSN ("sshr", 0x5f000400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), |
| 2972 | SIMD_INSN ("ssra", 0x5f001400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
| 2973 | SIMD_INSN ("srshr", 0x5f002400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
| 2974 | SIMD_INSN ("srsra", 0x5f003400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
| 2975 | SIMD_INSN ("shl", 0x5f005400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0), | |
| 2976 | SIMD_INSN ("sqshl", 0x5f007400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0), | |
| 2977 | SIMD_INSN ("sqshrn", 0x5f009400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
| 2978 | SIMD_INSN ("sqrshrn", 0x5f009c00, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
| 2979 | SIMD_INSN ("scvtf", 0x5f00e400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0), | |
| 4bd13cde | 2980 | SF16_INSN ("scvtf", 0x5f10e400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0), |
| 9d30b0bd | 2981 | SIMD_INSN ("fcvtzs", 0x5f00fc00, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0), |
| 4bd13cde | 2982 | SF16_INSN ("fcvtzs", 0x5f10fc00, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0), |
| 9d30b0bd RS |
2983 | SIMD_INSN ("ushr", 0x7f000400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), |
| 2984 | SIMD_INSN ("usra", 0x7f001400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
| 2985 | SIMD_INSN ("urshr", 0x7f002400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
| 2986 | SIMD_INSN ("ursra", 0x7f003400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
| 2987 | SIMD_INSN ("sri", 0x7f004400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
| 2988 | SIMD_INSN ("sli", 0x7f005400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0), | |
| 2989 | SIMD_INSN ("sqshlu", 0x7f006400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0), | |
| 2990 | SIMD_INSN ("uqshl", 0x7f007400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0), | |
| 2991 | SIMD_INSN ("sqshrun", 0x7f008400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
| 2992 | SIMD_INSN ("sqrshrun", 0x7f008c00, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
| 2993 | SIMD_INSN ("uqshrn", 0x7f009400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
| 2994 | SIMD_INSN ("uqrshrn", 0x7f009c00, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
| 2995 | SIMD_INSN ("ucvtf", 0x7f00e400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0), | |
| 4bd13cde | 2996 | SF16_INSN ("ucvtf", 0x7f10e400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0), |
| 9d30b0bd | 2997 | SIMD_INSN ("fcvtzu", 0x7f00fc00, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0), |
| 4bd13cde | 2998 | SF16_INSN ("fcvtzu", 0x7f10fc00, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0), |
| a06ea964 | 2999 | /* Bitfield. */ |
| 9d30b0bd | 3000 | CORE_INSN ("sbfm", 0x13000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N), |
| 5ce912d8 RS |
3001 | CORE_INSN ("sbfiz", 0x13000000, 0x7f800000, bitfield, OP_SBFIZ, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), |
| 3002 | CORE_INSN ("sbfx", 0x13000000, 0x7f800000, bitfield, OP_SBFX, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), | |
| 9d30b0bd RS |
3003 | CORE_INSN ("sxtb", 0x13001c00, 0x7fbffc00, bitfield, 0, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N), |
| 3004 | CORE_INSN ("sxth", 0x13003c00, 0x7fbffc00, bitfield, 0, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N), | |
| 3005 | CORE_INSN ("sxtw", 0x93407c00, 0xfffffc00, bitfield, 0, OP2 (Rd, Rn), QL_EXT_W, F_ALIAS | F_P3), | |
| 5ce912d8 | 3006 | CORE_INSN ("asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV), |
| 9d30b0bd | 3007 | CORE_INSN ("bfm", 0x33000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N), |
| 5ce912d8 | 3008 | CORE_INSN ("bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), |
| 344bde0a | 3009 | V8_2_INSN ("bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV), |
| 5ce912d8 | 3010 | CORE_INSN ("bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), |
| 9d30b0bd | 3011 | CORE_INSN ("ubfm", 0x53000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N), |
| 5ce912d8 RS |
3012 | CORE_INSN ("ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), |
| 3013 | CORE_INSN ("ubfx", 0x53000000, 0x7f800000, bitfield, OP_UBFX, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), | |
| 3014 | CORE_INSN ("uxtb", 0x53001c00, 0xfffffc00, bitfield, OP_UXTB, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3), | |
| 3015 | CORE_INSN ("uxth", 0x53003c00, 0xfffffc00, bitfield, OP_UXTH, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3), | |
| 3016 | CORE_INSN ("lsl", 0x53000000, 0x7f800000, bitfield, OP_LSL_IMM, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV), | |
| 3017 | CORE_INSN ("lsr", 0x53000000, 0x7f800000, bitfield, OP_LSR_IMM, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV), | |
| a06ea964 | 3018 | /* Unconditional branch (immediate). */ |
| 5ce912d8 RS |
3019 | CORE_INSN ("b", 0x14000000, 0xfc000000, branch_imm, OP_B, OP1 (ADDR_PCREL26), QL_PCREL_26, 0), |
| 3020 | CORE_INSN ("bl", 0x94000000, 0xfc000000, branch_imm, OP_BL, OP1 (ADDR_PCREL26), QL_PCREL_26, 0), | |
| a06ea964 | 3021 | /* Unconditional branch (register). */ |
| 9d30b0bd RS |
3022 | CORE_INSN ("br", 0xd61f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, 0), |
| 3023 | CORE_INSN ("blr", 0xd63f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, 0), | |
| 3024 | CORE_INSN ("ret", 0xd65f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, F_OPD0_OPT | F_DEFAULT (30)), | |
| 3025 | CORE_INSN ("eret", 0xd69f03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, 0), | |
| 3026 | CORE_INSN ("drps", 0xd6bf03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, 0), | |
| 74f5402d SN |
3027 | V8_3_INSN ("braa", 0xd71f0800, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0), |
| 3028 | V8_3_INSN ("brab", 0xd71f0c00, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0), | |
| 3029 | V8_3_INSN ("blraa", 0xd73f0800, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0), | |
| 3030 | V8_3_INSN ("blrab", 0xd73f0c00, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0), | |
| 3031 | V8_3_INSN ("braaz", 0xd61f081f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0), | |
| 3032 | V8_3_INSN ("brabz", 0xd61f0c1f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0), | |
| 3033 | V8_3_INSN ("blraaz", 0xd63f081f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0), | |
| 3034 | V8_3_INSN ("blrabz", 0xd63f0c1f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0), | |
| 3035 | V8_3_INSN ("retaa", 0xd65f0bff, 0xffffffff, branch_reg, OP0 (), {}, 0), | |
| 3036 | V8_3_INSN ("retab", 0xd65f0fff, 0xffffffff, branch_reg, OP0 (), {}, 0), | |
| 3037 | V8_3_INSN ("eretaa", 0xd69f0bff, 0xffffffff, branch_reg, OP0 (), {}, 0), | |
| 3038 | V8_3_INSN ("eretab", 0xd69f0fff, 0xffffffff, branch_reg, OP0 (), {}, 0), | |
| a06ea964 | 3039 | /* Compare & branch (immediate). */ |
| 9d30b0bd RS |
3040 | CORE_INSN ("cbz", 0x34000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF), |
| 3041 | CORE_INSN ("cbnz", 0x35000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF), | |
| a06ea964 | 3042 | /* Conditional branch (immediate). */ |
| 9d30b0bd | 3043 | CORE_INSN ("b.c", 0x54000000, 0xff000010, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_COND), |
| a06ea964 | 3044 | /* Conditional compare (immediate). */ |
| 9d30b0bd RS |
3045 | CORE_INSN ("ccmn", 0x3a400800, 0x7fe00c10, condcmp_imm, 0, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF), |
| 3046 | CORE_INSN ("ccmp", 0x7a400800, 0x7fe00c10, condcmp_imm, 0, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF), | |
| a06ea964 | 3047 | /* Conditional compare (register). */ |
| 9d30b0bd RS |
3048 | CORE_INSN ("ccmn", 0x3a400000, 0x7fe00c10, condcmp_reg, 0, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF), |
| 3049 | CORE_INSN ("ccmp", 0x7a400000, 0x7fe00c10, condcmp_reg, 0, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF), | |
| a06ea964 | 3050 | /* Conditional select. */ |
| 9d30b0bd RS |
3051 | CORE_INSN ("csel", 0x1a800000, 0x7fe00c00, condsel, 0, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_SF), |
| 3052 | CORE_INSN ("csinc", 0x1a800400, 0x7fe00c00, condsel, 0, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF), | |
| 5ce912d8 RS |
3053 | CORE_INSN ("cinc", 0x1a800400, 0x7fe00c00, condsel, OP_CINC, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV), |
| 3054 | CORE_INSN ("cset", 0x1a9f07e0, 0x7fff0fe0, condsel, OP_CSET, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV), | |
| 9d30b0bd | 3055 | CORE_INSN ("csinv", 0x5a800000, 0x7fe00c00, condsel, 0, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF), |
| 5ce912d8 RS |
3056 | CORE_INSN ("cinv", 0x5a800000, 0x7fe00c00, condsel, OP_CINV, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV), |
| 3057 | CORE_INSN ("csetm", 0x5a9f03e0, 0x7fff0fe0, condsel, OP_CSETM, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV), | |
| 9d30b0bd | 3058 | CORE_INSN ("csneg", 0x5a800400, 0x7fe00c00, condsel, 0, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF), |
| 5ce912d8 | 3059 | CORE_INSN ("cneg", 0x5a800400, 0x7fe00c00, condsel, OP_CNEG, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV), |
| a06ea964 | 3060 | /* Crypto AES. */ |
| c0e7cef7 NC |
3061 | AES_INSN ("aese", 0x4e284800, 0xfffffc00, cryptoaes, OP2 (Vd, Vn), QL_V2SAME16B, 0), |
| 3062 | AES_INSN ("aesd", 0x4e285800, 0xfffffc00, cryptoaes, OP2 (Vd, Vn), QL_V2SAME16B, 0), | |
| 3063 | AES_INSN ("aesmc", 0x4e286800, 0xfffffc00, cryptoaes, OP2 (Vd, Vn), QL_V2SAME16B, 0), | |
| 3064 | AES_INSN ("aesimc", 0x4e287800, 0xfffffc00, cryptoaes, OP2 (Vd, Vn), QL_V2SAME16B, 0), | |
| a06ea964 | 3065 | /* Crypto two-reg SHA. */ |
| c0e7cef7 NC |
3066 | SHA2_INSN ("sha1h", 0x5e280800, 0xfffffc00, cryptosha2, OP2 (Fd, Fn), QL_2SAMES, 0), |
| 3067 | SHA2_INSN ("sha1su1", 0x5e281800, 0xfffffc00, cryptosha2, OP2 (Vd, Vn), QL_V2SAME4S, 0), | |
| 3068 | SHA2_INSN ("sha256su0",0x5e282800, 0xfffffc00, cryptosha2, OP2 (Vd, Vn), QL_V2SAME4S, 0), | |
| a06ea964 | 3069 | /* Crypto three-reg SHA. */ |
| c0e7cef7 NC |
3070 | SHA2_INSN ("sha1c", 0x5e000000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0), |
| 3071 | SHA2_INSN ("sha1p", 0x5e001000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0), | |
| 3072 | SHA2_INSN ("sha1m", 0x5e002000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0), | |
| 3073 | SHA2_INSN ("sha1su0", 0x5e003000, 0xffe0fc00, cryptosha3, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0), | |
| 3074 | SHA2_INSN ("sha256h", 0x5e004000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0), | |
| 3075 | SHA2_INSN ("sha256h2", 0x5e005000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0), | |
| 3076 | SHA2_INSN ("sha256su1",0x5e006000, 0xffe0fc00, cryptosha3, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0), | |
| a06ea964 | 3077 | /* Data-processing (1 source). */ |
| 9d30b0bd RS |
3078 | CORE_INSN ("rbit", 0x5ac00000, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), |
| 3079 | CORE_INSN ("rev16", 0x5ac00400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), | |
| 3080 | CORE_INSN ("rev", 0x5ac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEW, 0), | |
| 3081 | CORE_INSN ("rev", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_HAS_ALIAS | F_P1), | |
| 344bde0a | 3082 | V8_2_INSN ("rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS), |
| 9d30b0bd RS |
3083 | CORE_INSN ("clz", 0x5ac01000, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), |
| 3084 | CORE_INSN ("cls", 0x5ac01400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), | |
| 3085 | CORE_INSN ("rev32", 0xdac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, 0), | |
| a2cfc830 SN |
3086 | V8_3_INSN ("pacia", 0xdac10000, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), |
| 3087 | V8_3_INSN ("pacib", 0xdac10400, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
| 3088 | V8_3_INSN ("pacda", 0xdac10800, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
| 3089 | V8_3_INSN ("pacdb", 0xdac10c00, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
| 3090 | V8_3_INSN ("autia", 0xdac11000, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
| 3091 | V8_3_INSN ("autib", 0xdac11400, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
| 3092 | V8_3_INSN ("autda", 0xdac11800, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
| 3093 | V8_3_INSN ("autdb", 0xdac11c00, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
| 3094 | V8_3_INSN ("paciza", 0xdac123e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3095 | V8_3_INSN ("pacizb", 0xdac127e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3096 | V8_3_INSN ("pacdza", 0xdac12be0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3097 | V8_3_INSN ("pacdzb", 0xdac12fe0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3098 | V8_3_INSN ("autiza", 0xdac133e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3099 | V8_3_INSN ("autizb", 0xdac137e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3100 | V8_3_INSN ("autdza", 0xdac13be0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3101 | V8_3_INSN ("autdzb", 0xdac13fe0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3102 | V8_3_INSN ("xpaci", 0xdac143e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| 3103 | V8_3_INSN ("xpacd", 0xdac147e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
| a06ea964 | 3104 | /* Data-processing (2 source). */ |
| 9d30b0bd RS |
3105 | CORE_INSN ("udiv", 0x1ac00800, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), |
| 3106 | CORE_INSN ("sdiv", 0x1ac00c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), | |
| 3107 | CORE_INSN ("lslv", 0x1ac02000, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS), | |
| 3108 | CORE_INSN ("lsl", 0x1ac02000, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), | |
| 3109 | CORE_INSN ("lsrv", 0x1ac02400, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS), | |
| 3110 | CORE_INSN ("lsr", 0x1ac02400, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), | |
| 3111 | CORE_INSN ("asrv", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS), | |
| 3112 | CORE_INSN ("asr", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), | |
| 3113 | CORE_INSN ("rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS), | |
| 3114 | CORE_INSN ("ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), | |
| b731bc3b SD |
3115 | MEMTAG_INSN ("subp", 0x9ac00000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn_SP, Rm_SP), QL_I3SAMEX, 0), |
| 3116 | MEMTAG_INSN ("subps", 0xbac00000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn_SP, Rm_SP), QL_I3SAMEX, F_HAS_ALIAS), | |
| 3117 | MEMTAG_INSN ("cmpp", 0xbac0001f, 0xffe0fc1f, dp_2src, OP2 (Rn_SP, Rm_SP), QL_I2SAMEX, F_ALIAS), | |
| 193614f2 SD |
3118 | MEMTAG_INSN ("irg", 0x9ac01000, 0xffe0fc00, dp_2src, OP3 (Rd_SP, Rn_SP, Rm), QL_I3SAMEX, F_OPD2_OPT | F_DEFAULT (0x1f)), |
| 3119 | MEMTAG_INSN ("gmi", 0x9ac01400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn_SP, Rm), QL_I3SAMEX, 0), | |
| c84364ec | 3120 | V8_3_INSN ("pacga", 0x9ac03000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm_SP), QL_I3SAMEX, 0), |
| e60bb1dd | 3121 | /* CRC instructions. */ |
| 4bd13cde NC |
3122 | _CRC_INSN ("crc32b", 0x1ac04000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), |
| 3123 | _CRC_INSN ("crc32h", 0x1ac04400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), | |
| 3124 | _CRC_INSN ("crc32w", 0x1ac04800, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), | |
| 3125 | _CRC_INSN ("crc32x", 0x9ac04c00, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3WWX, 0), | |
| 3126 | _CRC_INSN ("crc32cb",0x1ac05000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), | |
| 3127 | _CRC_INSN ("crc32ch",0x1ac05400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), | |
| 3128 | _CRC_INSN ("crc32cw",0x1ac05800, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), | |
| 3129 | _CRC_INSN ("crc32cx",0x9ac05c00, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3WWX, 0), | |
| a06ea964 | 3130 | /* Data-processing (3 source). */ |
| 9d30b0bd RS |
3131 | CORE_INSN ("madd", 0x1b000000, 0x7fe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF), |
| 3132 | CORE_INSN ("mul", 0x1b007c00, 0x7fe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF), | |
| 3133 | CORE_INSN ("msub", 0x1b008000, 0x7fe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF), | |
| 3134 | CORE_INSN ("mneg", 0x1b00fc00, 0x7fe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF), | |
| 3135 | CORE_INSN ("smaddl",0x9b200000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS), | |
| 3136 | CORE_INSN ("smull", 0x9b207c00, 0xffe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS), | |
| 3137 | CORE_INSN ("smsubl",0x9b208000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS), | |
| 3138 | CORE_INSN ("smnegl",0x9b20fc00, 0xffe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS), | |
| 3139 | CORE_INSN ("smulh", 0x9b407c00, 0xffe08000, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0), | |
| 3140 | CORE_INSN ("umaddl",0x9ba00000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS), | |
| 3141 | CORE_INSN ("umull", 0x9ba07c00, 0xffe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS), | |
| 3142 | CORE_INSN ("umsubl",0x9ba08000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS), | |
| 3143 | CORE_INSN ("umnegl",0x9ba0fc00, 0xffe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS), | |
| 3144 | CORE_INSN ("umulh", 0x9bc07c00, 0xffe08000, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0), | |
| a06ea964 | 3145 | /* Excep'n generation. */ |
| 9d30b0bd RS |
3146 | CORE_INSN ("svc", 0xd4000001, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), |
| 3147 | CORE_INSN ("hvc", 0xd4000002, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), | |
| 3148 | CORE_INSN ("smc", 0xd4000003, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), | |
| 3149 | CORE_INSN ("brk", 0xd4200000, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), | |
| 3150 | CORE_INSN ("hlt", 0xd4400000, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), | |
| 3151 | CORE_INSN ("dcps1", 0xd4a00001, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), | |
| 3152 | CORE_INSN ("dcps2", 0xd4a00002, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), | |
| 3153 | CORE_INSN ("dcps3", 0xd4a00003, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), | |
| a06ea964 | 3154 | /* Extract. */ |
| 9d30b0bd | 3155 | CORE_INSN ("extr", 0x13800000, 0x7fa00000, extract, 0, OP4 (Rd, Rn, Rm, IMMS), QL_EXTR, F_HAS_ALIAS | F_SF | F_N), |
| 5ce912d8 | 3156 | CORE_INSN ("ror", 0x13800000, 0x7fa00000, extract, OP_ROR_IMM, OP3 (Rd, Rm, IMMS), QL_SHIFT, F_ALIAS | F_CONV), |
| a06ea964 | 3157 | /* Floating-point<->fixed-point conversions. */ |
| 9d30b0bd | 3158 | __FP_INSN ("scvtf", 0x1e020000, 0x7f3f0000, float2fix, 0, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF), |
| 4bd13cde | 3159 | FF16_INSN ("scvtf", 0x1ec20000, 0x7f3f0000, float2fix, OP3 (Fd, Rn, FBITS), QL_FIX2FP_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3160 | __FP_INSN ("ucvtf", 0x1e030000, 0x7f3f0000, float2fix, 0, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF), |
| 4bd13cde | 3161 | FF16_INSN ("ucvtf", 0x1ec30000, 0x7f3f0000, float2fix, OP3 (Fd, Rn, FBITS), QL_FIX2FP_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3162 | __FP_INSN ("fcvtzs",0x1e180000, 0x7f3f0000, float2fix, 0, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF), |
| 4bd13cde | 3163 | FF16_INSN ("fcvtzs",0x1ed80000, 0x7f3f0000, float2fix, OP3 (Rd, Fn, FBITS), QL_FP2FIX_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3164 | __FP_INSN ("fcvtzu",0x1e190000, 0x7f3f0000, float2fix, 0, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF), |
| 4bd13cde | 3165 | FF16_INSN ("fcvtzu",0x1ed90000, 0x7f3f0000, float2fix, OP3 (Rd, Fn, FBITS), QL_FP2FIX_H, F_FPTYPE | F_SF), |
| a06ea964 | 3166 | /* Floating-point<->integer conversions. */ |
| 9d30b0bd | 3167 | __FP_INSN ("fcvtns",0x1e200000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3168 | FF16_INSN ("fcvtns",0x1ee00000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3169 | __FP_INSN ("fcvtnu",0x1e210000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3170 | FF16_INSN ("fcvtnu",0x1ee10000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3171 | __FP_INSN ("scvtf", 0x1e220000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF), |
| 4bd13cde | 3172 | FF16_INSN ("scvtf", 0x1ee20000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3173 | __FP_INSN ("ucvtf", 0x1e230000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF), |
| 4bd13cde | 3174 | FF16_INSN ("ucvtf", 0x1ee30000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3175 | __FP_INSN ("fcvtas",0x1e240000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3176 | FF16_INSN ("fcvtas",0x1ee40000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3177 | __FP_INSN ("fcvtau",0x1e250000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3178 | FF16_INSN ("fcvtau",0x1ee50000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| cb366992 | 3179 | __FP_INSN ("fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT_FMOV, F_FPTYPE | F_SF), |
| 4bd13cde | 3180 | FF16_INSN ("fmov", 0x1ee60000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| cb366992 | 3181 | __FP_INSN ("fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP_FMOV, F_FPTYPE | F_SF), |
| 4bd13cde | 3182 | FF16_INSN ("fmov", 0x1ee70000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3183 | __FP_INSN ("fcvtps",0x1e280000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3184 | FF16_INSN ("fcvtps",0x1ee80000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3185 | __FP_INSN ("fcvtpu",0x1e290000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3186 | FF16_INSN ("fcvtpu",0x1ee90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3187 | __FP_INSN ("fcvtms",0x1e300000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3188 | FF16_INSN ("fcvtms",0x1ef00000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3189 | __FP_INSN ("fcvtmu",0x1e310000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3190 | FF16_INSN ("fcvtmu",0x1ef10000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3191 | __FP_INSN ("fcvtzs",0x1e380000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3192 | FF16_INSN ("fcvtzs",0x1ef80000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd | 3193 | __FP_INSN ("fcvtzu",0x1e390000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
| 4bd13cde | 3194 | FF16_INSN ("fcvtzu",0x1ef90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
| 9d30b0bd RS |
3195 | __FP_INSN ("fmov", 0x9eae0000, 0xfffffc00, float2int, 0, OP2 (Rd, VnD1), QL_XVD1, 0), |
| 3196 | __FP_INSN ("fmov", 0x9eaf0000, 0xfffffc00, float2int, 0, OP2 (VdD1, Rn), QL_VD1X, 0), | |
| eae424ae | 3197 | {"fjcvtzs", 0x1e7e0000, 0xfffffc00, float2int, 0, FP_V8_3, OP2 (Rd, Fn), QL_FP2INT_W_D, 0, 0, 0, NULL }, |
| a06ea964 | 3198 | /* Floating-point conditional compare. */ |
| 9d30b0bd | 3199 | __FP_INSN ("fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE), |
| 4bd13cde | 3200 | FF16_INSN ("fccmp", 0x1ee00400, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE), |
| 9d30b0bd | 3201 | __FP_INSN ("fccmpe",0x1e200410, 0xff200c10, floatccmp, 0, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE), |
| 4bd13cde | 3202 | FF16_INSN ("fccmpe",0x1ee00410, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE), |
| a06ea964 | 3203 | /* Floating-point compare. */ |
| 9d30b0bd | 3204 | __FP_INSN ("fcmp", 0x1e202000, 0xff20fc1f, floatcmp, 0, OP2 (Fn, Fm), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3205 | FF16_INSN ("fcmp", 0x1ee02000, 0xff20fc1f, floatcmp, OP2 (Fn, Fm), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3206 | __FP_INSN ("fcmpe", 0x1e202010, 0xff20fc1f, floatcmp, 0, OP2 (Fn, Fm), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3207 | FF16_INSN ("fcmpe", 0x1ee02010, 0xff20fc1f, floatcmp, OP2 (Fn, Fm), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3208 | __FP_INSN ("fcmp", 0x1e202008, 0xff20fc1f, floatcmp, 0, OP2 (Fn, FPIMM0), QL_DST_SD,F_FPTYPE), |
| 4bd13cde | 3209 | FF16_INSN ("fcmp", 0x1ee02008, 0xff20fc1f, floatcmp, OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3210 | __FP_INSN ("fcmpe", 0x1e202018, 0xff20fc1f, floatcmp, 0, OP2 (Fn, FPIMM0), QL_DST_SD,F_FPTYPE), |
| 4bd13cde | 3211 | FF16_INSN ("fcmpe", 0x1ee02018, 0xff20fc1f, floatcmp, OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE), |
| 13c60ad7 SD |
3212 | /* Data processing instructions ARMv8.5-A. */ |
| 3213 | FLAGMANIP_INSN ("xaflag", 0xd500403f, 0xffffffff, 0, OP0 (), {}, 0), | |
| 3214 | FLAGMANIP_INSN ("axflag", 0xd500405f, 0xffffffff, 0, OP0 (), {}, 0), | |
| 3215 | FRINTTS_INSN ("frint32z", 0x1e284000, 0xffbffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), | |
| 3216 | FRINTTS_INSN ("frint32x", 0x1e28c000, 0xffbffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), | |
| 3217 | FRINTTS_INSN ("frint64z", 0x1e294000, 0xffbffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), | |
| 3218 | FRINTTS_INSN ("frint64x", 0x1e29c000, 0xffbffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), | |
| a06ea964 | 3219 | /* Floating-point data-processing (1 source). */ |
| 9d30b0bd | 3220 | __FP_INSN ("fmov", 0x1e204000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3221 | FF16_INSN ("fmov", 0x1ee04000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3222 | __FP_INSN ("fabs", 0x1e20c000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3223 | FF16_INSN ("fabs", 0x1ee0c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3224 | __FP_INSN ("fneg", 0x1e214000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3225 | FF16_INSN ("fneg", 0x1ee14000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3226 | __FP_INSN ("fsqrt", 0x1e21c000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3227 | FF16_INSN ("fsqrt", 0x1ee1c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 5ce912d8 | 3228 | __FP_INSN ("fcvt", 0x1e224000, 0xff3e7c00, floatdp1, OP_FCVT, OP2 (Fd, Fn), QL_FCVT, F_FPTYPE | F_MISC), |
| 9d30b0bd | 3229 | __FP_INSN ("frintn",0x1e244000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3230 | FF16_INSN ("frintn",0x1ee44000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3231 | __FP_INSN ("frintp",0x1e24c000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3232 | FF16_INSN ("frintp",0x1ee4c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3233 | __FP_INSN ("frintm",0x1e254000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3234 | FF16_INSN ("frintm",0x1ee54000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3235 | __FP_INSN ("frintz",0x1e25c000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3236 | FF16_INSN ("frintz",0x1ee5c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3237 | __FP_INSN ("frinta",0x1e264000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3238 | FF16_INSN ("frinta",0x1ee64000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3239 | __FP_INSN ("frintx",0x1e274000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3240 | FF16_INSN ("frintx",0x1ee74000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| 9d30b0bd | 3241 | __FP_INSN ("frinti",0x1e27c000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
| 4bd13cde | 3242 | FF16_INSN ("frinti",0x1ee7c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
| a06ea964 | 3243 | /* Floating-point data-processing (2 source). */ |
| 9d30b0bd | 3244 | __FP_INSN ("fmul", 0x1e200800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3245 | FF16_INSN ("fmul", 0x1ee00800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| 9d30b0bd | 3246 | __FP_INSN ("fdiv", 0x1e201800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3247 | FF16_INSN ("fdiv", 0x1ee01800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| 9d30b0bd | 3248 | __FP_INSN ("fadd", 0x1e202800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3249 | FF16_INSN ("fadd", 0x1ee02800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| 9d30b0bd | 3250 | __FP_INSN ("fsub", 0x1e203800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3251 | FF16_INSN ("fsub", 0x1ee03800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| 9d30b0bd | 3252 | __FP_INSN ("fmax", 0x1e204800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3253 | FF16_INSN ("fmax", 0x1ee04800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| 9d30b0bd | 3254 | __FP_INSN ("fmin", 0x1e205800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3255 | FF16_INSN ("fmin", 0x1ee05800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| 9d30b0bd | 3256 | __FP_INSN ("fmaxnm",0x1e206800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3257 | FF16_INSN ("fmaxnm",0x1ee06800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| 9d30b0bd | 3258 | __FP_INSN ("fminnm",0x1e207800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3259 | FF16_INSN ("fminnm",0x1ee07800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| 9d30b0bd | 3260 | __FP_INSN ("fnmul", 0x1e208800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
| 4bd13cde | 3261 | FF16_INSN ("fnmul", 0x1ee08800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
| a06ea964 | 3262 | /* Floating-point data-processing (3 source). */ |
| 9d30b0bd | 3263 | __FP_INSN ("fmadd", 0x1f000000, 0xff208000, floatdp3, 0, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE), |
| 4bd13cde | 3264 | FF16_INSN ("fmadd", 0x1fc00000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE), |
| 9d30b0bd | 3265 | __FP_INSN ("fmsub", 0x1f008000, 0xff208000, floatdp3, 0, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE), |
| 4bd13cde | 3266 | FF16_INSN ("fmsub", 0x1fc08000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE), |
| 9d30b0bd | 3267 | __FP_INSN ("fnmadd",0x1f200000, 0xff208000, floatdp3, 0, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE), |
| 4bd13cde | 3268 | FF16_INSN ("fnmadd",0x1fe00000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE), |
| 9d30b0bd | 3269 | __FP_INSN ("fnmsub",0x1f208000, 0xff208000, floatdp3, 0, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE), |
| 4bd13cde | 3270 | FF16_INSN ("fnmsub",0x1fe08000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE), |
| a06ea964 | 3271 | /* Floating-point immediate. */ |
| 9d30b0bd | 3272 | __FP_INSN ("fmov", 0x1e201000, 0xff201fe0, floatimm, 0, OP2 (Fd, FPIMM), QL_DST_SD, F_FPTYPE), |
| 4bd13cde | 3273 | FF16_INSN ("fmov", 0x1ee01000, 0xff201fe0, floatimm, OP2 (Fd, FPIMM), QL_DST_H, F_FPTYPE), |
| a06ea964 | 3274 | /* Floating-point conditional select. */ |
| 9d30b0bd | 3275 | __FP_INSN ("fcsel", 0x1e200c00, 0xff200c00, floatsel, 0, OP4 (Fd, Fn, Fm, COND), QL_FP_COND, F_FPTYPE), |
| 4bd13cde | 3276 | FF16_INSN ("fcsel", 0x1ee00c00, 0xff200c00, floatsel, OP4 (Fd, Fn, Fm, COND), QL_FP_COND_H, F_FPTYPE), |
| a06ea964 | 3277 | /* Load/store register (immediate indexed). */ |
| 9d30b0bd RS |
3278 | CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), |
| 3279 | CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), | |
| 3280 | CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE), | |
| 3281 | CORE_INSN ("str", 0x3c000400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0), | |
| 3282 | CORE_INSN ("ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0), | |
| 3283 | CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
| 3284 | CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
| 3285 | CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE), | |
| 3286 | CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3287 | CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3288 | CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0), | |
| fb3265b3 | 3289 | /* Load/store Allocation Tag instructions. */ |
| bd7ceb8d SD |
3290 | MEMTAG_INSN ("stg", 0xd9200800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0), |
| 3291 | MEMTAG_INSN ("stzg", 0xd9600800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0), | |
| 3292 | MEMTAG_INSN ("st2g", 0xd9a00800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0), | |
| 3293 | MEMTAG_INSN ("stz2g",0xd9e00800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0), | |
| 3294 | MEMTAG_INSN ("stg", 0xd9200400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0), | |
| 3295 | MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0), | |
| 3296 | MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0), | |
| 3297 | MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0), | |
| a06ea964 | 3298 | /* Load/store register (unsigned immediate). */ |
| 5ce912d8 RS |
3299 | CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0), |
| 3300 | CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0), | |
| 3301 | CORE_INSN ("ldrsb", 0x39800000, 0xff800000, ldst_pos, OP_LDRSB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R8, F_LDS_SIZE), | |
| 3302 | CORE_INSN ("str", 0x3d000000, 0x3f400000, ldst_pos, OP_STRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0), | |
| 3303 | CORE_INSN ("ldr", 0x3d400000, 0x3f400000, ldst_pos, OP_LDRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0), | |
| 3304 | CORE_INSN ("strh", 0x79000000, 0xffc00000, ldst_pos, OP_STRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0), | |
| 3305 | CORE_INSN ("ldrh", 0x79400000, 0xffc00000, ldst_pos, OP_LDRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0), | |
| 3306 | CORE_INSN ("ldrsh", 0x79800000, 0xff800000, ldst_pos, OP_LDRSH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R16, F_LDS_SIZE), | |
| 3307 | CORE_INSN ("str", 0xb9000000, 0xbfc00000, ldst_pos, OP_STR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3308 | CORE_INSN ("ldr", 0xb9400000, 0xbfc00000, ldst_pos, OP_LDR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3309 | CORE_INSN ("ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0), | |
| 3310 | CORE_INSN ("prfm", 0xf9800000, 0xffc00000, ldst_pos, OP_PRFM_POS, OP2 (PRFOP, ADDR_UIMM12), QL_LDST_PRFM, 0), | |
| a06ea964 | 3311 | /* Load/store register (register offset). */ |
| 9d30b0bd RS |
3312 | CORE_INSN ("strb", 0x38200800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0), |
| 3313 | CORE_INSN ("ldrb", 0x38600800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0), | |
| 3314 | CORE_INSN ("ldrsb", 0x38a00800, 0xffa00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_R8, F_LDS_SIZE), | |
| 3315 | CORE_INSN ("str", 0x3c200800, 0x3f600c00, ldst_regoff, 0, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0), | |
| 3316 | CORE_INSN ("ldr", 0x3c600800, 0x3f600c00, ldst_regoff, 0, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0), | |
| 3317 | CORE_INSN ("strh", 0x78200800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0), | |
| 3318 | CORE_INSN ("ldrh", 0x78600800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0), | |
| 3319 | CORE_INSN ("ldrsh", 0x78a00800, 0xffa00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_R16, F_LDS_SIZE), | |
| 3320 | CORE_INSN ("str", 0xb8200800, 0xbfe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3321 | CORE_INSN ("ldr", 0xb8600800, 0xbfe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3322 | CORE_INSN ("ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_X32, 0), | |
| 3323 | CORE_INSN ("prfm", 0xf8a00800, 0xffe00c00, ldst_regoff, 0, OP2 (PRFOP, ADDR_REGOFF), QL_LDST_PRFM, 0), | |
| a06ea964 | 3324 | /* Load/store register (unprivileged). */ |
| 9d30b0bd RS |
3325 | CORE_INSN ("sttrb", 0x38000800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), |
| 3326 | CORE_INSN ("ldtrb", 0x38400800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), | |
| 3327 | CORE_INSN ("ldtrsb", 0x38800800, 0xffa00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE), | |
| 3328 | CORE_INSN ("sttrh", 0x78000800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
| 3329 | CORE_INSN ("ldtrh", 0x78400800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
| 3330 | CORE_INSN ("ldtrsh", 0x78800800, 0xffa00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE), | |
| 3331 | CORE_INSN ("sttr", 0xb8000800, 0xbfe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3332 | CORE_INSN ("ldtr", 0xb8400800, 0xbfe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3333 | CORE_INSN ("ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0), | |
| a06ea964 | 3334 | /* Load/store register (unscaled immediate). */ |
| 5ce912d8 RS |
3335 | CORE_INSN ("sturb", 0x38000000, 0xffe00c00, ldst_unscaled, OP_STURB, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), |
| 3336 | CORE_INSN ("ldurb", 0x38400000, 0xffe00c00, ldst_unscaled, OP_LDURB, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), | |
| 3337 | CORE_INSN ("ldursb", 0x38800000, 0xffa00c00, ldst_unscaled, OP_LDURSB, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE), | |
| 3338 | CORE_INSN ("stur", 0x3c000000, 0x3f600c00, ldst_unscaled, OP_STURV, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0), | |
| 3339 | CORE_INSN ("ldur", 0x3c400000, 0x3f600c00, ldst_unscaled, OP_LDURV, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0), | |
| 3340 | CORE_INSN ("sturh", 0x78000000, 0xffe00c00, ldst_unscaled, OP_STURH, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
| 3341 | CORE_INSN ("ldurh", 0x78400000, 0xffe00c00, ldst_unscaled, OP_LDURH, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
| 3342 | CORE_INSN ("ldursh", 0x78800000, 0xffa00c00, ldst_unscaled, OP_LDURSH, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE), | |
| 3343 | CORE_INSN ("stur", 0xb8000000, 0xbfe00c00, ldst_unscaled, OP_STUR, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3344 | CORE_INSN ("ldur", 0xb8400000, 0xbfe00c00, ldst_unscaled, OP_LDUR, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
| 3345 | CORE_INSN ("ldursw", 0xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0), | |
| 3346 | CORE_INSN ("prfum", 0xf8800000, 0xffe00c00, ldst_unscaled, OP_PRFUM, OP2 (PRFOP, ADDR_SIMM9), QL_LDST_PRFM, 0), | |
| e6025b54 | 3347 | MEMTAG_INSN ("ldg", 0xd9600000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_SIMM13), QL_LDG, 0), |
| 3f06e550 SN |
3348 | /* Load/store register (scaled signed immediate). */ |
| 3349 | V8_3_INSN ("ldraa", 0xf8200400, 0xffa00400, ldst_imm10, OP2 (Rt, ADDR_SIMM10), QL_X1NIL, 0), | |
| 3350 | V8_3_INSN ("ldrab", 0xf8a00400, 0xffa00400, ldst_imm10, OP2 (Rt, ADDR_SIMM10), QL_X1NIL, 0), | |
| a06ea964 | 3351 | /* Load/store exclusive. */ |
| 9d30b0bd RS |
3352 | CORE_INSN ("stxrb", 0x8007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), |
| 3353 | CORE_INSN ("stlxrb", 0x800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3354 | CORE_INSN ("ldxrb", 0x85f7c00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3355 | CORE_INSN ("ldaxrb", 0x85ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3356 | CORE_INSN ("stlrb", 0x89ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3357 | CORE_INSN ("ldarb", 0x8dffc00, 0xffeffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3358 | CORE_INSN ("stxrh", 0x48007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3359 | CORE_INSN ("stlxrh", 0x4800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3360 | CORE_INSN ("ldxrh", 0x485f7c00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3361 | CORE_INSN ("ldaxrh", 0x485ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3362 | CORE_INSN ("stlrh", 0x489ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| f311ba7e | 3363 | CORE_INSN ("ldarh", 0x48dffc00, 0xfffffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), |
| 9d30b0bd RS |
3364 | CORE_INSN ("stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q), |
| 3365 | CORE_INSN ("stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q), | |
| 3366 | CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q), | |
| 3367 | CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q), | |
| 3368 | CORE_INSN ("ldxr", 0x885f7c00, 0xbfe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
| 3369 | CORE_INSN ("ldaxr", 0x885ffc00, 0xbfe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
| 3370 | CORE_INSN ("ldxp", 0x887f0000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q), | |
| 3371 | CORE_INSN ("ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q), | |
| 3372 | CORE_INSN ("stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
| 3373 | CORE_INSN ("ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
| d74d4880 SN |
3374 | RCPC_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), |
| 3375 | RCPC_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3376 | RCPC_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
| e54010f1 SD |
3377 | MEMTAG_INSN ("ldgm", 0xd9e00000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0), |
| 3378 | MEMTAG_INSN ("stgm", 0xd9a00000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0), | |
| 20a4ca55 | 3379 | MEMTAG_INSN ("stzgm", 0xd9200000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0), |
| 290806fd | 3380 | /* Limited Ordering Regions load/store instructions. */ |
| 4bd13cde NC |
3381 | _LOR_INSN ("ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), |
| 3382 | _LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3383 | _LOR_INSN ("ldlarh", 0x48df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3384 | _LOR_INSN ("stllr", 0x889f7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
| 3385 | _LOR_INSN ("stllrb", 0x089f7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| 3386 | _LOR_INSN ("stllrh", 0x489f7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
| a06ea964 | 3387 | /* Load/store no-allocate pair (offset). */ |
| 9d30b0bd RS |
3388 | CORE_INSN ("stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), |
| 3389 | CORE_INSN ("ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), | |
| 3390 | CORE_INSN ("stnp", 0x2c000000, 0x3fc00000, ldstnapair_offs, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
| 3391 | CORE_INSN ("ldnp", 0x2c400000, 0x3fc00000, ldstnapair_offs, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
| a06ea964 | 3392 | /* Load/store register pair (offset). */ |
| 9d30b0bd RS |
3393 | CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), |
| 3394 | CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), | |
| 3395 | CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
| 3396 | CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
| eae424ae | 3397 | {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)}, |
| fb3265b3 | 3398 | MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, 0), |
| a06ea964 | 3399 | /* Load/store register pair (indexed). */ |
| 9d30b0bd RS |
3400 | CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), |
| 3401 | CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), | |
| 3402 | CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
| 3403 | CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
| eae424ae | 3404 | {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)}, |
| fb3265b3 | 3405 | MEMTAG_INSN ("stgp", 0x68800000, 0xfec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, 0), |
| a06ea964 | 3406 | /* Load register (literal). */ |
| 5ce912d8 RS |
3407 | CORE_INSN ("ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q), |
| 3408 | CORE_INSN ("ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0), | |
| 3409 | CORE_INSN ("ldrsw", 0x98000000, 0xff000000, loadlit, OP_LDRSW_LIT, OP2 (Rt, ADDR_PCREL19), QL_X_PCREL, 0), | |
| 3410 | CORE_INSN ("prfm", 0xd8000000, 0xff000000, loadlit, OP_PRFM_LIT, OP2 (PRFOP, ADDR_PCREL19), QL_PRFM_PCREL, 0), | |
| a06ea964 | 3411 | /* Logical (immediate). */ |
| 9d30b0bd | 3412 | CORE_INSN ("and", 0x12000000, 0x7f800000, log_imm, 0, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), |
| 5ce912d8 | 3413 | CORE_INSN ("bic", 0x12000000, 0x7f800000, log_imm, OP_BIC, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_ALIAS | F_PSEUDO | F_SF), |
| 9d30b0bd | 3414 | CORE_INSN ("orr", 0x32000000, 0x7f800000, log_imm, 0, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), |
| 5ce912d8 | 3415 | CORE_INSN ("mov", 0x320003e0, 0x7f8003e0, log_imm, OP_MOV_IMM_LOG, OP2 (Rd_SP, IMM_MOV), QL_R1NIL, F_ALIAS | F_P1 | F_SF | F_CONV), |
| 9d30b0bd RS |
3416 | CORE_INSN ("eor", 0x52000000, 0x7f800000, log_imm, 0, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_SF), |
| 3417 | CORE_INSN ("ands", 0x72000000, 0x7f800000, log_imm, 0, OP3 (Rd, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), | |
| 3418 | CORE_INSN ("tst", 0x7200001f, 0x7f80001f, log_imm, 0, OP2 (Rn, LIMM), QL_R1NIL, F_ALIAS | F_SF), | |
| a06ea964 | 3419 | /* Logical (shifted register). */ |
| 9d30b0bd RS |
3420 | CORE_INSN ("and", 0xa000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), |
| 3421 | CORE_INSN ("bic", 0xa200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), | |
| 3422 | CORE_INSN ("orr", 0x2a000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
| 57b64c41 | 3423 | CORE_INSN ("mov", 0x2a0003e0, 0x7fe0ffe0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF), |
| 5ce912d8 | 3424 | CORE_INSN ("uxtw", 0x2a0003e0, 0x7f2003e0, log_shift, OP_UXTW, OP2 (Rd, Rm), QL_I2SAMEW, F_ALIAS | F_PSEUDO), |
| 9d30b0bd RS |
3425 | CORE_INSN ("orn", 0x2a200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), |
| 3426 | CORE_INSN ("mvn", 0x2a2003e0, 0x7f2003e0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF), | |
| 3427 | CORE_INSN ("eor", 0x4a000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), | |
| 3428 | CORE_INSN ("eon", 0x4a200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), | |
| 3429 | CORE_INSN ("ands", 0x6a000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
| 3430 | CORE_INSN ("tst", 0x6a00001f, 0x7f20001f, log_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF), | |
| 3431 | CORE_INSN ("bics", 0x6a200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), | |
| ee804238 | 3432 | /* LSE extension (atomic). */ |
| 4bd13cde NC |
3433 | _LSE_INSN ("casb", 0x8a07c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), |
| 3434 | _LSE_INSN ("cash", 0x48a07c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3435 | _LSE_INSN ("cas", 0x88a07c00, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3436 | _LSE_INSN ("casab", 0x8e07c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3437 | _LSE_INSN ("caslb", 0x8a0fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3438 | _LSE_INSN ("casalb", 0x8e0fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3439 | _LSE_INSN ("casah", 0x48e07c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3440 | _LSE_INSN ("caslh", 0x48a0fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3441 | _LSE_INSN ("casalh", 0x48e0fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3442 | _LSE_INSN ("casa", 0x88e07c00, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3443 | _LSE_INSN ("casl", 0x88a0fc00, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3444 | _LSE_INSN ("casal", 0x88e0fc00, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3445 | _LSE_INSN ("casp", 0x8207c00, 0xbfe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ), | |
| 3446 | _LSE_INSN ("caspa", 0x8607c00, 0xbfe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ), | |
| 3447 | _LSE_INSN ("caspl", 0x820fc00, 0xbfe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ), | |
| 3448 | _LSE_INSN ("caspal", 0x860fc00, 0xbfe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ), | |
| 3449 | _LSE_INSN ("swpb", 0x38208000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3450 | _LSE_INSN ("swph", 0x78208000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3451 | _LSE_INSN ("swp", 0xb8208000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3452 | _LSE_INSN ("swpab", 0x38a08000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3453 | _LSE_INSN ("swplb", 0x38608000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3454 | _LSE_INSN ("swpalb", 0x38e08000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3455 | _LSE_INSN ("swpah", 0x78a08000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3456 | _LSE_INSN ("swplh", 0x78608000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3457 | _LSE_INSN ("swpalh", 0x78e08000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3458 | _LSE_INSN ("swpa", 0xb8a08000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3459 | _LSE_INSN ("swpl", 0xb8608000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3460 | _LSE_INSN ("swpal", 0xb8e08000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3461 | _LSE_INSN ("ldaddb", 0x38200000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3462 | _LSE_INSN ("ldaddh", 0x78200000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3463 | _LSE_INSN ("ldadd", 0xb8200000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3464 | _LSE_INSN ("ldaddab", 0x38a00000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3465 | _LSE_INSN ("ldaddlb", 0x38600000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3466 | _LSE_INSN ("ldaddalb", 0x38e00000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3467 | _LSE_INSN ("ldaddah", 0x78a00000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3468 | _LSE_INSN ("ldaddlh", 0x78600000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3469 | _LSE_INSN ("ldaddalh", 0x78e00000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3470 | _LSE_INSN ("ldadda", 0xb8a00000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3471 | _LSE_INSN ("ldaddl", 0xb8600000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3472 | _LSE_INSN ("ldaddal", 0xb8e00000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3473 | _LSE_INSN ("ldclrb", 0x38201000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3474 | _LSE_INSN ("ldclrh", 0x78201000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3475 | _LSE_INSN ("ldclr", 0xb8201000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3476 | _LSE_INSN ("ldclrab", 0x38a01000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3477 | _LSE_INSN ("ldclrlb", 0x38601000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3478 | _LSE_INSN ("ldclralb", 0x38e01000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3479 | _LSE_INSN ("ldclrah", 0x78a01000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3480 | _LSE_INSN ("ldclrlh", 0x78601000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3481 | _LSE_INSN ("ldclralh", 0x78e01000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3482 | _LSE_INSN ("ldclra", 0xb8a01000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3483 | _LSE_INSN ("ldclrl", 0xb8601000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3484 | _LSE_INSN ("ldclral", 0xb8e01000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3485 | _LSE_INSN ("ldeorb", 0x38202000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3486 | _LSE_INSN ("ldeorh", 0x78202000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3487 | _LSE_INSN ("ldeor", 0xb8202000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3488 | _LSE_INSN ("ldeorab", 0x38a02000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3489 | _LSE_INSN ("ldeorlb", 0x38602000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3490 | _LSE_INSN ("ldeoralb", 0x38e02000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3491 | _LSE_INSN ("ldeorah", 0x78a02000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3492 | _LSE_INSN ("ldeorlh", 0x78602000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3493 | _LSE_INSN ("ldeoralh", 0x78e02000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3494 | _LSE_INSN ("ldeora", 0xb8a02000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3495 | _LSE_INSN ("ldeorl", 0xb8602000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3496 | _LSE_INSN ("ldeoral", 0xb8e02000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3497 | _LSE_INSN ("ldsetb", 0x38203000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3498 | _LSE_INSN ("ldseth", 0x78203000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3499 | _LSE_INSN ("ldset", 0xb8203000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3500 | _LSE_INSN ("ldsetab", 0x38a03000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3501 | _LSE_INSN ("ldsetlb", 0x38603000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3502 | _LSE_INSN ("ldsetalb", 0x38e03000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3503 | _LSE_INSN ("ldsetah", 0x78a03000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3504 | _LSE_INSN ("ldsetlh", 0x78603000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3505 | _LSE_INSN ("ldsetalh", 0x78e03000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3506 | _LSE_INSN ("ldseta", 0xb8a03000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3507 | _LSE_INSN ("ldsetl", 0xb8603000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3508 | _LSE_INSN ("ldsetal", 0xb8e03000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3509 | _LSE_INSN ("ldsmaxb", 0x38204000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3510 | _LSE_INSN ("ldsmaxh", 0x78204000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3511 | _LSE_INSN ("ldsmax", 0xb8204000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3512 | _LSE_INSN ("ldsmaxab", 0x38a04000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3513 | _LSE_INSN ("ldsmaxlb", 0x38604000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3514 | _LSE_INSN ("ldsmaxalb", 0x38e04000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3515 | _LSE_INSN ("ldsmaxah", 0x78a04000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3516 | _LSE_INSN ("ldsmaxlh", 0x78604000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3517 | _LSE_INSN ("ldsmaxalh", 0x78e04000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3518 | _LSE_INSN ("ldsmaxa", 0xb8a04000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3519 | _LSE_INSN ("ldsmaxl", 0xb8604000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3520 | _LSE_INSN ("ldsmaxal", 0xb8e04000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3521 | _LSE_INSN ("ldsminb", 0x38205000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3522 | _LSE_INSN ("ldsminh", 0x78205000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3523 | _LSE_INSN ("ldsmin", 0xb8205000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3524 | _LSE_INSN ("ldsminab", 0x38a05000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3525 | _LSE_INSN ("ldsminlb", 0x38605000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3526 | _LSE_INSN ("ldsminalb", 0x38e05000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3527 | _LSE_INSN ("ldsminah", 0x78a05000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3528 | _LSE_INSN ("ldsminlh", 0x78605000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3529 | _LSE_INSN ("ldsminalh", 0x78e05000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3530 | _LSE_INSN ("ldsmina", 0xb8a05000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3531 | _LSE_INSN ("ldsminl", 0xb8605000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3532 | _LSE_INSN ("ldsminal", 0xb8e05000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3533 | _LSE_INSN ("ldumaxb", 0x38206000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3534 | _LSE_INSN ("ldumaxh", 0x78206000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3535 | _LSE_INSN ("ldumax", 0xb8206000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3536 | _LSE_INSN ("ldumaxab", 0x38a06000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3537 | _LSE_INSN ("ldumaxlb", 0x38606000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3538 | _LSE_INSN ("ldumaxalb", 0x38e06000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3539 | _LSE_INSN ("ldumaxah", 0x78a06000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3540 | _LSE_INSN ("ldumaxlh", 0x78606000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3541 | _LSE_INSN ("ldumaxalh", 0x78e06000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3542 | _LSE_INSN ("ldumaxa", 0xb8a06000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3543 | _LSE_INSN ("ldumaxl", 0xb8606000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3544 | _LSE_INSN ("ldumaxal", 0xb8e06000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3545 | _LSE_INSN ("lduminb", 0x38207000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3546 | _LSE_INSN ("lduminh", 0x78207000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3547 | _LSE_INSN ("ldumin", 0xb8207000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3548 | _LSE_INSN ("lduminab", 0x38a07000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3549 | _LSE_INSN ("lduminlb", 0x38607000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3550 | _LSE_INSN ("lduminalb", 0x38e07000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3551 | _LSE_INSN ("lduminah", 0x78a07000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3552 | _LSE_INSN ("lduminlh", 0x78607000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
| 3553 | _LSE_INSN ("lduminalh", 0x78e07000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
| 3554 | _LSE_INSN ("ldumina", 0xb8a07000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3555 | _LSE_INSN ("lduminl", 0xb8607000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
| 3556 | _LSE_INSN ("lduminal", 0xb8e07000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
| 3557 | _LSE_INSN ("staddb", 0x3820001f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3558 | _LSE_INSN ("staddh", 0x7820001f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3559 | _LSE_INSN ("stadd", 0xb820001f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3560 | _LSE_INSN ("staddlb", 0x3860001f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3561 | _LSE_INSN ("staddlh", 0x7860001f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3562 | _LSE_INSN ("staddl", 0xb860001f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3563 | _LSE_INSN ("stclrb", 0x3820101f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3564 | _LSE_INSN ("stclrh", 0x7820101f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3565 | _LSE_INSN ("stclr", 0xb820101f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3566 | _LSE_INSN ("stclrlb", 0x3860101f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3567 | _LSE_INSN ("stclrlh", 0x7860101f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3568 | _LSE_INSN ("stclrl", 0xb860101f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3569 | _LSE_INSN ("steorb", 0x3820201f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3570 | _LSE_INSN ("steorh", 0x7820201f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3571 | _LSE_INSN ("steor", 0xb820201f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3572 | _LSE_INSN ("steorlb", 0x3860201f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3573 | _LSE_INSN ("steorlh", 0x7860201f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3574 | _LSE_INSN ("steorl", 0xb860201f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3575 | _LSE_INSN ("stsetb", 0x3820301f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3576 | _LSE_INSN ("stseth", 0x7820301f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3577 | _LSE_INSN ("stset", 0xb820301f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3578 | _LSE_INSN ("stsetlb", 0x3860301f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3579 | _LSE_INSN ("stsetlh", 0x7860301f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3580 | _LSE_INSN ("stsetl", 0xb860301f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3581 | _LSE_INSN ("stsmaxb", 0x3820401f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3582 | _LSE_INSN ("stsmaxh", 0x7820401f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3583 | _LSE_INSN ("stsmax", 0xb820401f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3584 | _LSE_INSN ("stsmaxlb", 0x3860401f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3585 | _LSE_INSN ("stsmaxlh", 0x7860401f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3586 | _LSE_INSN ("stsmaxl", 0xb860401f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3587 | _LSE_INSN ("stsminb", 0x3820501f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3588 | _LSE_INSN ("stsminh", 0x7820501f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3589 | _LSE_INSN ("stsmin", 0xb820501f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3590 | _LSE_INSN ("stsminlb", 0x3860501f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3591 | _LSE_INSN ("stsminlh", 0x7860501f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3592 | _LSE_INSN ("stsminl", 0xb860501f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3593 | _LSE_INSN ("stumaxb", 0x3820601f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3594 | _LSE_INSN ("stumaxh", 0x7820601f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3595 | _LSE_INSN ("stumax", 0xb820601f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3596 | _LSE_INSN ("stumaxlb", 0x3860601f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3597 | _LSE_INSN ("stumaxlh", 0x7860601f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3598 | _LSE_INSN ("stumaxl", 0xb860601f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3599 | _LSE_INSN ("stuminb", 0x3820701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3600 | _LSE_INSN ("stuminh", 0x7820701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3601 | _LSE_INSN ("stumin", 0xb820701f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| 3602 | _LSE_INSN ("stuminlb", 0x3860701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3603 | _LSE_INSN ("stuminlh", 0x7860701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
| 3604 | _LSE_INSN ("stuminl", 0xb860701f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
| a06ea964 | 3605 | /* Move wide (immediate). */ |
| 5ce912d8 RS |
3606 | CORE_INSN ("movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS), |
| 3607 | CORE_INSN ("mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV), | |
| 3608 | CORE_INSN ("movz", 0x52800000, 0x7f800000, movewide, OP_MOVZ, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS), | |
| 3609 | CORE_INSN ("mov", 0x52800000, 0x7f800000, movewide, OP_MOV_IMM_WIDE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV), | |
| 3610 | CORE_INSN ("movk", 0x72800000, 0x7f800000, movewide, OP_MOVK, OP2 (Rd, HALF), QL_DST_R, F_SF), | |
| a06ea964 | 3611 | /* PC-rel. addressing. */ |
| 9d30b0bd RS |
3612 | CORE_INSN ("adr", 0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0), |
| 3613 | CORE_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0), | |
| b83b4b13 SD |
3614 | /* TME Instructions. */ |
| 3615 | _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0), | |
| 3616 | _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), {}, 0), | |
| 3617 | _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0), | |
| 3618 | _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0), | |
| a06ea964 | 3619 | /* System. */ |
| f9830ec1 | 3620 | CORE_INSN ("msr", 0xd500401f, 0xfff8f01f, ic_system, 0, OP2 (PSTATEFIELD, UIMM4), {}, F_SYS_WRITE), |
| 9d30b0bd RS |
3621 | CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS), |
| 3622 | CORE_INSN ("nop", 0xd503201f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
| be2e7d95 | 3623 | CORE_INSN ("csdb",0xd503229f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), |
| ff605452 | 3624 | BTI_INSN ("bti",0xd503241f, 0xffffff3f, ic_system, OP1 (BTI_TARGET), {}, F_ALIAS | F_OPD0_OPT | F_DEFAULT (0x0)), |
| 9d30b0bd RS |
3625 | CORE_INSN ("yield", 0xd503203f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), |
| 3626 | CORE_INSN ("wfe", 0xd503205f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
| 3627 | CORE_INSN ("wfi", 0xd503207f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
| 3628 | CORE_INSN ("sev", 0xd503209f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
| 3629 | CORE_INSN ("sevl",0xd50320bf, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
| 8787d804 SN |
3630 | V8_3_INSN ("xpaclri", 0xd50320ff, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), |
| 3631 | V8_3_INSN ("pacia1716", 0xd503211f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3632 | V8_3_INSN ("pacib1716", 0xd503215f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3633 | V8_3_INSN ("autia1716", 0xd503219f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3634 | V8_3_INSN ("autib1716", 0xd50321df, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| eae424ae TC |
3635 | {"esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {}, F_ALIAS, 0, 0, NULL}, |
| 3636 | {"psb", 0xd503223f, 0xffffffff, ic_system, 0, STAT_PROFILE, OP1 (BARRIER_PSB), {}, F_ALIAS, 0, 0, NULL}, | |
| 9d30b0bd | 3637 | CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)), |
| cde3679e NC |
3638 | CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, F_HAS_ALIAS), |
| 3639 | CORE_INSN ("ssbb", 0xd503309f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
| 3640 | CORE_INSN ("pssbb", 0xd503349f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
| 9d30b0bd RS |
3641 | CORE_INSN ("dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, 0), |
| 3642 | CORE_INSN ("isb", 0xd50330df, 0xfffff0ff, ic_system, 0, OP1 (BARRIER_ISB), {}, F_OPD0_OPT | F_DEFAULT (0xF)), | |
| 68dfbb92 | 3643 | SB_INSN ("sb", 0xd50330ff, 0xffffffff, ic_system, OP0 (), {}, 0), |
| a6a51754 | 3644 | CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)), |
| 9d30b0bd RS |
3645 | CORE_INSN ("at", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS), |
| 3646 | CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS), | |
| 3647 | CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), | |
| 3648 | CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), | |
| 2ac435d4 SD |
3649 | PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), |
| 3650 | PREDRES_INSN ("dvp", 0xd50b73a0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), | |
| 3651 | PREDRES_INSN ("cpp", 0xd50b73e0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), | |
| f9830ec1 | 3652 | CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, F_SYS_WRITE), |
| a6a51754 | 3653 | CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, CRn, CRm, UIMM3_OP2), QL_SYSL, 0), |
| f9830ec1 | 3654 | CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, F_SYS_READ), |
| 8787d804 SN |
3655 | V8_3_INSN ("paciaz", 0xd503231f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), |
| 3656 | V8_3_INSN ("paciasp", 0xd503233f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3657 | V8_3_INSN ("pacibz", 0xd503235f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3658 | V8_3_INSN ("pacibsp", 0xd503237f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3659 | V8_3_INSN ("autiaz", 0xd503239f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3660 | V8_3_INSN ("autiasp", 0xd50323bf, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3661 | V8_3_INSN ("autibz", 0xd50323df, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| 3662 | V8_3_INSN ("autibsp", 0xd50323ff, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
| a06ea964 | 3663 | /* Test & branch (immediate). */ |
| 9d30b0bd RS |
3664 | CORE_INSN ("tbz", 0x36000000, 0x7f000000, testbranch, 0, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0), |
| 3665 | CORE_INSN ("tbnz",0x37000000, 0x7f000000, testbranch, 0, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0), | |
| a06ea964 | 3666 | /* The old UAL conditional branch mnemonics (to aid portability). */ |
| 9d30b0bd RS |
3667 | CORE_INSN ("beq", 0x54000000, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), |
| 3668 | CORE_INSN ("bne", 0x54000001, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3669 | CORE_INSN ("bcs", 0x54000002, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3670 | CORE_INSN ("bhs", 0x54000002, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3671 | CORE_INSN ("bcc", 0x54000003, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3672 | CORE_INSN ("blo", 0x54000003, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3673 | CORE_INSN ("bmi", 0x54000004, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3674 | CORE_INSN ("bpl", 0x54000005, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3675 | CORE_INSN ("bvs", 0x54000006, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3676 | CORE_INSN ("bvc", 0x54000007, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3677 | CORE_INSN ("bhi", 0x54000008, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3678 | CORE_INSN ("bls", 0x54000009, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3679 | CORE_INSN ("bge", 0x5400000a, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3680 | CORE_INSN ("blt", 0x5400000b, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3681 | CORE_INSN ("bgt", 0x5400000c, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| 3682 | CORE_INSN ("ble", 0x5400000d, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
| c0890d26 | 3683 | /* SVE instructions. */ |
| 582e12bf RS |
3684 | _SVE_INSN ("fmov", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_ALIAS, 0), |
| 3685 | _SVE_INSN ("fmov", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_ALIAS, 0), | |
| c0890d26 | 3686 | _SVE_INSN ("mov", 0x04603000, 0xffe0fc00, sve_misc, OP_MOV_Z_Z, OP2 (SVE_Zd, SVE_Zn), OP_SVE_DD, F_ALIAS | F_MISC, 0), |
| 582e12bf | 3687 | _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0), |
| c0890d26 RS |
3688 | _SVE_INSN ("mov", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_ALIAS, 0), |
| 3689 | _SVE_INSN ("mov", 0x25804000, 0xfff0c210, sve_misc, OP_MOV_P_P, OP2 (SVE_Pd, SVE_Pn), OP_SVE_BB, F_ALIAS | F_MISC, 0), | |
| 582e12bf | 3690 | _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_Zi, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0), |
| c0890d26 RS |
3691 | _SVE_INSN ("mov", 0x05c00000, 0xfffc0000, sve_limm, 0, OP2 (SVE_Zd, SVE_LIMM_MOV), OP_SVE_VU_BHSD, F_ALIAS, 0), |
| 3692 | _SVE_INSN ("mov", 0x2538c000, 0xff3fc000, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_ASIMM), OP_SVE_VU_BHSD, F_ALIAS, 0), | |
| eae424ae | 3693 | _SVE_INSNC ("mov", 0x05208000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Vn), OP_SVE_VMV_BHSD, F_ALIAS, C_SCAN_MOVPRFX, 0), |
| c0890d26 | 3694 | _SVE_INSN ("mov", 0x0520c000, 0xff20c000, sve_size_bhsd, OP_MOV_Z_P_Z, OP3 (SVE_Zd, SVE_Pg4_10, SVE_Zn), OP_SVE_VMV_BHSD, F_ALIAS | F_MISC, 0), |
| eae424ae | 3695 | _SVE_INSNC ("mov", 0x0528a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, Rn_SP), OP_SVE_VMR_BHSD, F_ALIAS, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
3696 | _SVE_INSN ("mov", 0x25004000, 0xfff0c210, sve_misc, OP_MOVZ_P_P_P, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, F_ALIAS | F_MISC, 0), |
| 3697 | _SVE_INSN ("mov", 0x25004210, 0xfff0c210, sve_misc, OP_MOVM_P_P_P, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BMB, F_ALIAS | F_MISC, 0), | |
| eae424ae | 3698 | _SVE_INSNC ("mov", 0x05100000, 0xff308000, sve_cpy, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_ASIMM), OP_SVE_VPU_BHSD, F_ALIAS, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
3699 | _SVE_INSN ("movs", 0x25c04000, 0xfff0c210, sve_misc, OP_MOVS_P_P, OP2 (SVE_Pd, SVE_Pn), OP_SVE_BB, F_ALIAS | F_MISC, 0), |
| 3700 | _SVE_INSN ("movs", 0x25404000, 0xfff0c210, sve_misc, OP_MOVZS_P_P_P, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, F_ALIAS | F_MISC, 0), | |
| 3701 | _SVE_INSN ("not", 0x25004200, 0xfff0c210, sve_misc, OP_NOT_P_P_P_Z, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, F_ALIAS | F_MISC, 0), | |
| 3702 | _SVE_INSN ("nots", 0x25404200, 0xfff0c210, sve_misc, OP_NOTS_P_P_P_Z, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, F_ALIAS | F_MISC, 0), | |
| eae424ae | 3703 | _SVE_INSNC ("abs", 0x0416a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 | 3704 | _SVE_INSN ("add", 0x04200000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), |
| eae424ae TC |
3705 | _SVE_INSNC ("add", 0x2520c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| 3706 | _SVE_INSNC ("add", 0x04000000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 RS |
3707 | _SVE_INSN ("addpl", 0x04605000, 0xffe0f800, sve_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0), |
| 3708 | _SVE_INSN ("addvl", 0x04205000, 0xffe0f800, sve_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0), | |
| 3709 | _SVE_INSN ("adr", 0x0420a000, 0xffe0f000, sve_misc, 0, OP2 (SVE_Zd, SVE_ADDR_ZZ_SXTW), OP_SVE_DD, 0, 0), | |
| 3710 | _SVE_INSN ("adr", 0x0460a000, 0xffe0f000, sve_misc, 0, OP2 (SVE_Zd, SVE_ADDR_ZZ_UXTW), OP_SVE_DD, 0, 0), | |
| 3711 | _SVE_INSN ("adr", 0x04a0a000, 0xffa0f000, sve_size_sd, 0, OP2 (SVE_Zd, SVE_ADDR_ZZ_LSL), OP_SVE_VV_SD, 0, 0), | |
| 3712 | _SVE_INSN ("and", 0x04203000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, 0, 0), | |
| eae424ae TC |
3713 | _SVE_INSNC ("and", 0x05800000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_LIMM), OP_SVE_VVU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 1), |
| 3714 | _SVE_INSNC ("and", 0x041a0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 RS |
3715 | _SVE_INSN ("and", 0x25004000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), |
| 3716 | _SVE_INSN ("ands", 0x25404000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), | |
| 3717 | _SVE_INSN ("andv", 0x041a2000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), | |
| 3718 | _SVE_INSN ("asr", 0x04208000, 0xff20fc00, sve_size_bhs, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVD_BHS, 0, 0), | |
| 3719 | _SVE_INSN ("asr", 0x04209000, 0xff20fc00, sve_shift_unpred, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0), | |
| eae424ae TC |
3720 | _SVE_INSNC ("asr", 0x04108000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| 3721 | _SVE_INSNC ("asr", 0x04188000, 0xff3fe000, sve_size_bhs, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVD_BHS, 0, C_SCAN_MOVPRFX, 2), | |
| 3722 | _SVE_INSNC ("asr", 0x04008000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3723 | _SVE_INSNC ("asrd", 0x04048000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3724 | _SVE_INSNC ("asrr", 0x04148000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 | 3725 | _SVE_INSN ("bic", 0x04e03000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, 0, 0), |
| eae424ae | 3726 | _SVE_INSNC ("bic", 0x041b0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| c0890d26 RS |
3727 | _SVE_INSN ("bic", 0x25004010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), |
| 3728 | _SVE_INSN ("bics", 0x25404010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
| 3729 | _SVE_INSN ("brka", 0x25104000, 0xffffc200, sve_pred_zm, 0, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BPB, 0, 0), | |
| 3730 | _SVE_INSN ("brkas", 0x25504000, 0xffffc210, sve_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, 0, 0), | |
| 3731 | _SVE_INSN ("brkb", 0x25904000, 0xffffc200, sve_pred_zm, 0, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BPB, 0, 0), | |
| 3732 | _SVE_INSN ("brkbs", 0x25d04000, 0xffffc210, sve_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, 0, 0), | |
| 3733 | _SVE_INSN ("brkn", 0x25184000, 0xffffc210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pd), OP_SVE_BZBB, 0, 3), | |
| 3734 | _SVE_INSN ("brkns", 0x25584000, 0xffffc210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pd), OP_SVE_BZBB, 0, 3), | |
| 3735 | _SVE_INSN ("brkpa", 0x2500c000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
| 3736 | _SVE_INSN ("brkpas", 0x2540c000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
| 3737 | _SVE_INSN ("brkpb", 0x2500c010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
| 3738 | _SVE_INSN ("brkpbs", 0x2540c010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
| eae424ae | 3739 | _SVE_INSNC ("clasta", 0x05288000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| c0890d26 RS |
3740 | _SVE_INSN ("clasta", 0x052a8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Vd, SVE_Pg3, SVE_Vd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, 2), |
| 3741 | _SVE_INSN ("clasta", 0x0530a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (Rd, SVE_Pg3, Rd, SVE_Zm_5), OP_SVE_RURV_BHSD, 0, 2), | |
| eae424ae | 3742 | _SVE_INSNC ("clastb", 0x05298000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| c0890d26 RS |
3743 | _SVE_INSN ("clastb", 0x052b8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Vd, SVE_Pg3, SVE_Vd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, 2), |
| 3744 | _SVE_INSN ("clastb", 0x0531a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (Rd, SVE_Pg3, Rd, SVE_Zm_5), OP_SVE_RURV_BHSD, 0, 2), | |
| eae424ae TC |
3745 | _SVE_INSNC ("cls", 0x0418a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
| 3746 | _SVE_INSNC ("clz", 0x0419a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
| c0890d26 RS |
3747 | _SVE_INSN ("cmpeq", 0x24002000, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), |
| 3748 | _SVE_INSN ("cmpeq", 0x2400a000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, 0, 0), | |
| 3749 | _SVE_INSN ("cmpeq", 0x25008000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3750 | _SVE_INSN ("cmpge", 0x24004000, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3751 | _SVE_INSN ("cmpge", 0x24008000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, F_HAS_ALIAS, 0), | |
| 3752 | _SVE_INSN ("cmpge", 0x25000000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3753 | _SVE_INSN ("cmpgt", 0x24004010, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3754 | _SVE_INSN ("cmpgt", 0x24008010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, F_HAS_ALIAS, 0), | |
| 3755 | _SVE_INSN ("cmpgt", 0x25000010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3756 | _SVE_INSN ("cmphi", 0x24000010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, F_HAS_ALIAS, 0), | |
| 3757 | _SVE_INSN ("cmphi", 0x2400c010, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3758 | _SVE_INSN ("cmphi", 0x24200010, 0xff202010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_UIMM7), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3759 | _SVE_INSN ("cmphs", 0x24000000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, F_HAS_ALIAS, 0), | |
| 3760 | _SVE_INSN ("cmphs", 0x2400c000, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3761 | _SVE_INSN ("cmphs", 0x24200000, 0xff202010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_UIMM7), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3762 | _SVE_INSN ("cmple", 0x24006010, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3763 | _SVE_INSN ("cmple", 0x25002010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3764 | _SVE_INSN ("cmplo", 0x2400e000, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3765 | _SVE_INSN ("cmplo", 0x24202000, 0xff202010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_UIMM7), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3766 | _SVE_INSN ("cmpls", 0x2400e010, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3767 | _SVE_INSN ("cmpls", 0x24202010, 0xff202010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_UIMM7), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3768 | _SVE_INSN ("cmplt", 0x24006000, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3769 | _SVE_INSN ("cmplt", 0x25002000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
| 3770 | _SVE_INSN ("cmpne", 0x24002010, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
| 3771 | _SVE_INSN ("cmpne", 0x2400a010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, 0, 0), | |
| 3772 | _SVE_INSN ("cmpne", 0x25008010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
| eae424ae TC |
3773 | _SVE_INSNC ("cnot", 0x041ba000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
| 3774 | _SVE_INSNC ("cnt", 0x041aa000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
| c0890d26 RS |
3775 | _SVE_INSN ("cntb", 0x0420e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 3776 | _SVE_INSN ("cntd", 0x04e0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 3777 | _SVE_INSN ("cnth", 0x0460e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 3778 | _SVE_INSN ("cntp", 0x25208000, 0xff3fc200, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_10, SVE_Pn), OP_SVE_XUV_BHSD, 0, 0), | |
| 3779 | _SVE_INSN ("cntw", 0x04a0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 3780 | _SVE_INSN ("compact", 0x05a18000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0), | |
| eae424ae TC |
3781 | _SVE_INSNC ("cpy", 0x05208000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Vn), OP_SVE_VMV_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0), |
| 3782 | _SVE_INSNC ("cpy", 0x0528a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, Rn_SP), OP_SVE_VMR_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0), | |
| 3783 | _SVE_INSNC ("cpy", 0x05100000, 0xff308000, sve_cpy, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_ASIMM), OP_SVE_VPU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0), | |
| c0890d26 RS |
3784 | _SVE_INSN ("ctermeq", 0x25a02000, 0xffa0fc1f, sve_size_sd, 0, OP2 (Rn, Rm), OP_SVE_RR, 0, 0), |
| 3785 | _SVE_INSN ("ctermne", 0x25a02010, 0xffa0fc1f, sve_size_sd, 0, OP2 (Rn, Rm), OP_SVE_RR, 0, 0), | |
| 3786 | _SVE_INSN ("decb", 0x0430e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| eae424ae | 3787 | _SVE_INSNC ("decd", 0x04f0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 | 3788 | _SVE_INSN ("decd", 0x04f0e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| eae424ae | 3789 | _SVE_INSNC ("dech", 0x0470c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 | 3790 | _SVE_INSN ("dech", 0x0470e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| eae424ae | 3791 | _SVE_INSNC ("decp", 0x252d8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 | 3792 | _SVE_INSN ("decp", 0x252d8800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), |
| eae424ae | 3793 | _SVE_INSNC ("decw", 0x04b0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
3794 | _SVE_INSN ("decw", 0x04b0e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 3795 | _SVE_INSN ("dup", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_HAS_ALIAS, 0), | |
| 582e12bf | 3796 | _SVE_INSN ("dup", 0x05202000, 0xff20fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_HAS_ALIAS, 0), |
| c0890d26 RS |
3797 | _SVE_INSN ("dup", 0x2538c000, 0xff3fc000, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_ASIMM), OP_SVE_VU_BHSD, F_HAS_ALIAS, 0), |
| 3798 | _SVE_INSN ("dupm", 0x05c00000, 0xfffc0000, sve_limm, 0, OP2 (SVE_Zd, SVE_LIMM), OP_SVE_VU_BHSD, F_HAS_ALIAS, 0), | |
| 3799 | _SVE_INSN ("eor", 0x04a03000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, 0, 0), | |
| eae424ae TC |
3800 | _SVE_INSNC ("eor", 0x05400000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_LIMM), OP_SVE_VVU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 1), |
| 3801 | _SVE_INSNC ("eor", 0x04190000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 RS |
3802 | _SVE_INSN ("eor", 0x25004200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), |
| 3803 | _SVE_INSN ("eors", 0x25404200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), | |
| 3804 | _SVE_INSN ("eorv", 0x04192000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), | |
| eae424ae TC |
3805 | _SVE_INSNC ("ext", 0x05200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM8_53), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1), |
| 3806 | _SVE_INSNC ("fabd", 0x65088000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3807 | _SVE_INSNC ("fabs", 0x041ca000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 582e12bf RS |
3808 | _SVE_INSN ("facge", 0x6500c010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0), |
| 3809 | _SVE_INSN ("facgt", 0x6500e010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0), | |
| 3810 | _SVE_INSN ("fadd", 0x65000000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), | |
| eae424ae TC |
3811 | _SVE_INSNC ("fadd", 0x65008000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
| 3812 | _SVE_INSNC ("fadd", 0x65188000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 582e12bf RS |
3813 | _SVE_INSN ("fadda", 0x65182000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Vd, SVE_Pg3, SVE_Vd, SVE_Zm_5), OP_SVE_VUVV_HSD, 0, 2), |
| 3814 | _SVE_INSN ("faddv", 0x65002000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0), | |
| eae424ae TC |
3815 | _SVE_INSNC ("fcadd", 0x64008000, 0xff3ee000, sve_size_hsd, 0, OP5 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5, SVE_IMM_ROT1), OP_SVE_VMVVU_HSD, 0, C_SCAN_MOVPRFX, 2), |
| 3816 | _SVE_INSNC ("fcmla", 0x64000000, 0xff208000, sve_size_hsd, 0, OP5 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16, IMM_ROT2), OP_SVE_VMVVU_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3817 | _SVE_INSNC ("fcmla", 0x64a01000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_H, 0, C_SCAN_MOVPRFX, 0), | |
| 3818 | _SVE_INSNC ("fcmla", 0x64e01000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_S, 0, C_SCAN_MOVPRFX, 0), | |
| 582e12bf RS |
3819 | _SVE_INSN ("fcmeq", 0x65122000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), |
| 3820 | _SVE_INSN ("fcmeq", 0x65006000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0), | |
| 3821 | _SVE_INSN ("fcmge", 0x65102000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), | |
| 3822 | _SVE_INSN ("fcmge", 0x65004000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0), | |
| 3823 | _SVE_INSN ("fcmgt", 0x65102010, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), | |
| 3824 | _SVE_INSN ("fcmgt", 0x65004010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0), | |
| 3825 | _SVE_INSN ("fcmle", 0x65112010, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), | |
| 3826 | _SVE_INSN ("fcmlt", 0x65112000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), | |
| 3827 | _SVE_INSN ("fcmne", 0x65132000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), | |
| 3828 | _SVE_INSN ("fcmne", 0x65006010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0), | |
| 3829 | _SVE_INSN ("fcmuo", 0x6500c000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0), | |
| eae424ae TC |
3830 | _SVE_INSNC ("fcpy", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0), |
| 3831 | _SVE_INSNC ("fcvt", 0x6588a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
| 3832 | _SVE_INSNC ("fcvt", 0x6589a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
| 3833 | _SVE_INSNC ("fcvt", 0x65c8a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
| 3834 | _SVE_INSNC ("fcvt", 0x65c9a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
| 3835 | _SVE_INSNC ("fcvt", 0x65caa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
| 3836 | _SVE_INSNC ("fcvt", 0x65cba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
| 3837 | _SVE_INSNC ("fcvtzs", 0x655aa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX, 0), | |
| 3838 | _SVE_INSNC ("fcvtzs", 0x655ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, C_SCAN_MOVPRFX, 0), | |
| 3839 | _SVE_INSNC ("fcvtzs", 0x655ea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, C_SCAN_MOVPRFX, 0), | |
| 3840 | _SVE_INSNC ("fcvtzs", 0x659ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX, 0), | |
| 3841 | _SVE_INSNC ("fcvtzs", 0x65d8a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX, 0), | |
| 3842 | _SVE_INSNC ("fcvtzs", 0x65dca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX, 0), | |
| 3843 | _SVE_INSNC ("fcvtzs", 0x65dea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0), | |
| 3844 | _SVE_INSNC ("fcvtzu", 0x655ba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX, 0), | |
| 3845 | _SVE_INSNC ("fcvtzu", 0x655da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, C_SCAN_MOVPRFX, 0), | |
| 3846 | _SVE_INSNC ("fcvtzu", 0x655fa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, C_SCAN_MOVPRFX, 0), | |
| 3847 | _SVE_INSNC ("fcvtzu", 0x659da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX, 0), | |
| 3848 | _SVE_INSNC ("fcvtzu", 0x65d9a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX, 0), | |
| 3849 | _SVE_INSNC ("fcvtzu", 0x65dda000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX, 0), | |
| 3850 | _SVE_INSNC ("fcvtzu", 0x65dfa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0), | |
| 3851 | _SVE_INSNC ("fdiv", 0x650d8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3852 | _SVE_INSNC ("fdivr", 0x650c8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 582e12bf RS |
3853 | _SVE_INSN ("fdup", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_HAS_ALIAS, 0), |
| 3854 | _SVE_INSN ("fexpa", 0x0420b800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0), | |
| eae424ae TC |
3855 | _SVE_INSNC ("fmad", 0x65208000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), |
| 3856 | _SVE_INSNC ("fmax", 0x65068000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3857 | _SVE_INSNC ("fmax", 0x651e8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3858 | _SVE_INSNC ("fmaxnm", 0x65048000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3859 | _SVE_INSNC ("fmaxnm", 0x651c8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 582e12bf RS |
3860 | _SVE_INSN ("fmaxnmv", 0x65042000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0), |
| 3861 | _SVE_INSN ("fmaxv", 0x65062000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0), | |
| eae424ae TC |
3862 | _SVE_INSNC ("fmin", 0x65078000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
| 3863 | _SVE_INSNC ("fmin", 0x651f8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3864 | _SVE_INSNC ("fminnm", 0x65058000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3865 | _SVE_INSNC ("fminnm", 0x651d8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 582e12bf RS |
3866 | _SVE_INSN ("fminnmv", 0x65052000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0), |
| 3867 | _SVE_INSN ("fminv", 0x65072000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0), | |
| eae424ae TC |
3868 | _SVE_INSNC ("fmla", 0x65200000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), |
| 3869 | _SVE_INSNC ("fmla", 0x64200000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0), | |
| 3870 | _SVE_INSNC ("fmla", 0x64a00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX, 0), | |
| 3871 | _SVE_INSNC ("fmla", 0x64e00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0), | |
| 3872 | _SVE_INSNC ("fmls", 0x65202000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3873 | _SVE_INSNC ("fmls", 0x64200400, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0), | |
| 3874 | _SVE_INSNC ("fmls", 0x64a00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX, 0), | |
| 3875 | _SVE_INSNC ("fmls", 0x64e00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0), | |
| 3876 | _SVE_INSNC ("fmsb", 0x6520a000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 582e12bf | 3877 | _SVE_INSN ("fmul", 0x65000800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), |
| eae424ae TC |
3878 | _SVE_INSNC ("fmul", 0x65028000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
| 3879 | _SVE_INSNC ("fmul", 0x651a8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_TWO), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 582e12bf RS |
3880 | _SVE_INSN ("fmul", 0x64202000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0), |
| 3881 | _SVE_INSN ("fmul", 0x64a02000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, 0), | |
| 3882 | _SVE_INSN ("fmul", 0x64e02000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, 0), | |
| eae424ae TC |
3883 | _SVE_INSNC ("fmulx", 0x650a8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
| 3884 | _SVE_INSNC ("fneg", 0x041da000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3885 | _SVE_INSNC ("fnmad", 0x6520c000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3886 | _SVE_INSNC ("fnmla", 0x65204000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3887 | _SVE_INSNC ("fnmls", 0x65206000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3888 | _SVE_INSNC ("fnmsb", 0x6520e000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 582e12bf RS |
3889 | _SVE_INSN ("frecpe", 0x650e3000, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0), |
| 3890 | _SVE_INSN ("frecps", 0x65001800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), | |
| eae424ae TC |
3891 | _SVE_INSNC ("frecpx", 0x650ca000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), |
| 3892 | _SVE_INSNC ("frinta", 0x6504a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3893 | _SVE_INSNC ("frinti", 0x6507a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3894 | _SVE_INSNC ("frintm", 0x6502a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3895 | _SVE_INSNC ("frintn", 0x6500a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3896 | _SVE_INSNC ("frintp", 0x6501a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3897 | _SVE_INSNC ("frintx", 0x6506a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 3898 | _SVE_INSNC ("frintz", 0x6503a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 582e12bf RS |
3899 | _SVE_INSN ("frsqrte", 0x650f3000, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0), |
| 3900 | _SVE_INSN ("frsqrts", 0x65001c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), | |
| eae424ae TC |
3901 | _SVE_INSNC ("fscale", 0x65098000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
| 3902 | _SVE_INSNC ("fsqrt", 0x650da000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
| 582e12bf | 3903 | _SVE_INSN ("fsub", 0x65000400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), |
| eae424ae TC |
3904 | _SVE_INSNC ("fsub", 0x65018000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
| 3905 | _SVE_INSNC ("fsub", 0x65198000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3906 | _SVE_INSNC ("fsubr", 0x65038000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3907 | _SVE_INSNC ("fsubr", 0x651b8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
| 3908 | _SVE_INSNC ("ftmad", 0x65108000, 0xff38fc00, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM3), OP_SVE_VVVU_HSD, 0, C_SCAN_MOVPRFX, 1), | |
| 582e12bf RS |
3909 | _SVE_INSN ("ftsmul", 0x65000c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), |
| 3910 | _SVE_INSN ("ftssel", 0x0420b000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), | |
| c0890d26 | 3911 | _SVE_INSN ("incb", 0x0430e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| eae424ae | 3912 | _SVE_INSNC ("incd", 0x04f0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 | 3913 | _SVE_INSN ("incd", 0x04f0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| eae424ae | 3914 | _SVE_INSNC ("inch", 0x0470c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 | 3915 | _SVE_INSN ("inch", 0x0470e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| eae424ae | 3916 | _SVE_INSNC ("incp", 0x252c8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 | 3917 | _SVE_INSN ("incp", 0x252c8800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), |
| eae424ae | 3918 | _SVE_INSNC ("incw", 0x04b0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
3919 | _SVE_INSN ("incw", 0x04b0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 3920 | _SVE_INSN ("index", 0x04204c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, Rn, Rm), OP_SVE_VRR_BHSD, 0, 0), | |
| 3921 | _SVE_INSN ("index", 0x04204000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_SIMM5, SVE_SIMM5B), OP_SVE_VUU_BHSD, 0, 0), | |
| 3922 | _SVE_INSN ("index", 0x04204400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, Rn, SIMM5), OP_SVE_VRU_BHSD, 0, 0), | |
| 3923 | _SVE_INSN ("index", 0x04204800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_SIMM5, Rm), OP_SVE_VUR_BHSD, 0, 0), | |
| eae424ae TC |
3924 | _SVE_INSNC ("insr", 0x05243800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_Rm), OP_SVE_VR_BHSD, 0, C_SCAN_MOVPRFX, 0), |
| 3925 | _SVE_INSNC ("insr", 0x05343800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_Vm), OP_SVE_VV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
| c0890d26 RS |
3926 | _SVE_INSN ("lasta", 0x0520a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg3, SVE_Zn), OP_SVE_RUV_BHSD, 0, 0), |
| 3927 | _SVE_INSN ("lasta", 0x05228000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), | |
| 3928 | _SVE_INSN ("lastb", 0x0521a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg3, SVE_Zn), OP_SVE_RUV_BHSD, 0, 0), | |
| 3929 | _SVE_INSN ("lastb", 0x05238000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), | |
| 3930 | _SVE_INSN ("ld1b", 0x84004000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), | |
| 3931 | _SVE_INSN ("ld1b", 0xa4004000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0), | |
| 3932 | _SVE_INSN ("ld1b", 0xa4204000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_HZU, F_OD(1), 0), | |
| 3933 | _SVE_INSN ("ld1b", 0xa4404000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_SZU, F_OD(1), 0), | |
| 3934 | _SVE_INSN ("ld1b", 0xa4604000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_DZU, F_OD(1), 0), | |
| 3935 | _SVE_INSN ("ld1b", 0xc4004000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3936 | _SVE_INSN ("ld1b", 0xc440c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 3937 | _SVE_INSN ("ld1b", 0x8420c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SZS, F_OD(1), 0), | |
| 3938 | _SVE_INSN ("ld1b", 0xa400a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_BZU, F_OD(1), 0), | |
| 3939 | _SVE_INSN ("ld1b", 0xa420a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
| 3940 | _SVE_INSN ("ld1b", 0xa440a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 3941 | _SVE_INSN ("ld1b", 0xa460a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 3942 | _SVE_INSN ("ld1b", 0xc420c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DZD, F_OD(1), 0), | |
| 3943 | _SVE_INSN ("ld1d", 0xa5e04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(1), 0), | |
| 3944 | _SVE_INSN ("ld1d", 0xc5804000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3945 | _SVE_INSN ("ld1d", 0xc5a04000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW3_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3946 | _SVE_INSN ("ld1d", 0xc5c0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 3947 | _SVE_INSN ("ld1d", 0xc5e0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL3), OP_SVE_DZD, F_OD(1), 0), | |
| 3948 | _SVE_INSN ("ld1d", 0xa5e0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 3949 | _SVE_INSN ("ld1d", 0xc5a0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x8), OP_SVE_DZD, F_OD(1), 0), | |
| 3950 | _SVE_INSN ("ld1h", 0x84804000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), | |
| 3951 | _SVE_INSN ("ld1h", 0x84a04000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_SZS, F_OD(1), 0), | |
| 3952 | _SVE_INSN ("ld1h", 0xa4a04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(1), 0), | |
| 3953 | _SVE_INSN ("ld1h", 0xa4c04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_SZU, F_OD(1), 0), | |
| 3954 | _SVE_INSN ("ld1h", 0xa4e04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_DZU, F_OD(1), 0), | |
| 3955 | _SVE_INSN ("ld1h", 0xc4804000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3956 | _SVE_INSN ("ld1h", 0xc4a04000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3957 | _SVE_INSN ("ld1h", 0xc4c0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 3958 | _SVE_INSN ("ld1h", 0xc4e0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DZD, F_OD(1), 0), | |
| 3959 | _SVE_INSN ("ld1h", 0x84a0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SZS, F_OD(1), 0), | |
| 3960 | _SVE_INSN ("ld1h", 0xa4a0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
| 3961 | _SVE_INSN ("ld1h", 0xa4c0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 3962 | _SVE_INSN ("ld1h", 0xa4e0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 3963 | _SVE_INSN ("ld1h", 0xc4a0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DZD, F_OD(1), 0), | |
| 3964 | _SVE_INSN ("ld1rb", 0x84408000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_BZU, F_OD(1), 0), | |
| 3965 | _SVE_INSN ("ld1rb", 0x8440a000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_HZU, F_OD(1), 0), | |
| 3966 | _SVE_INSN ("ld1rb", 0x8440c000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_SZU, F_OD(1), 0), | |
| 3967 | _SVE_INSN ("ld1rb", 0x8440e000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_DZU, F_OD(1), 0), | |
| 3968 | _SVE_INSN ("ld1rd", 0x85c0e000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x8), OP_SVE_DZU, F_OD(1), 0), | |
| 3969 | _SVE_INSN ("ld1rh", 0x84c0a000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_HZU, F_OD(1), 0), | |
| 3970 | _SVE_INSN ("ld1rh", 0x84c0c000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_SZU, F_OD(1), 0), | |
| 3971 | _SVE_INSN ("ld1rh", 0x84c0e000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_DZU, F_OD(1), 0), | |
| 582e12bf RS |
3972 | _SVE_INSN ("ld1rqb", 0xa4002000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_BZU, F_OD(1), 0), |
| 3973 | _SVE_INSN ("ld1rqb", 0xa4000000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0), | |
| 3974 | _SVE_INSN ("ld1rqd", 0xa5802000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_DZU, F_OD(1), 0), | |
| 3975 | _SVE_INSN ("ld1rqd", 0xa5800000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(1), 0), | |
| 3976 | _SVE_INSN ("ld1rqh", 0xa4802000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_HZU, F_OD(1), 0), | |
| 3977 | _SVE_INSN ("ld1rqh", 0xa4800000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(1), 0), | |
| 3978 | _SVE_INSN ("ld1rqw", 0xa5002000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_SZU, F_OD(1), 0), | |
| 3979 | _SVE_INSN ("ld1rqw", 0xa5000000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(1), 0), | |
| c0890d26 RS |
3980 | _SVE_INSN ("ld1rsb", 0x85c08000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_DZU, F_OD(1), 0), |
| 3981 | _SVE_INSN ("ld1rsb", 0x85c0a000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_SZU, F_OD(1), 0), | |
| 3982 | _SVE_INSN ("ld1rsb", 0x85c0c000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_HZU, F_OD(1), 0), | |
| 3983 | _SVE_INSN ("ld1rsh", 0x85408000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_DZU, F_OD(1), 0), | |
| 3984 | _SVE_INSN ("ld1rsh", 0x8540a000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_SZU, F_OD(1), 0), | |
| 3985 | _SVE_INSN ("ld1rsw", 0x84c08000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x4), OP_SVE_DZU, F_OD(1), 0), | |
| 3986 | _SVE_INSN ("ld1rw", 0x8540c000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x4), OP_SVE_SZU, F_OD(1), 0), | |
| 3987 | _SVE_INSN ("ld1rw", 0x8540e000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x4), OP_SVE_DZU, F_OD(1), 0), | |
| 3988 | _SVE_INSN ("ld1sb", 0x84000000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), | |
| 3989 | _SVE_INSN ("ld1sb", 0xa5804000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_DZU, F_OD(1), 0), | |
| 3990 | _SVE_INSN ("ld1sb", 0xa5a04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_SZU, F_OD(1), 0), | |
| 3991 | _SVE_INSN ("ld1sb", 0xa5c04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_HZU, F_OD(1), 0), | |
| 3992 | _SVE_INSN ("ld1sb", 0xc4000000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
| 3993 | _SVE_INSN ("ld1sb", 0xc4408000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 3994 | _SVE_INSN ("ld1sb", 0x84208000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SZS, F_OD(1), 0), | |
| 3995 | _SVE_INSN ("ld1sb", 0xa580a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 3996 | _SVE_INSN ("ld1sb", 0xa5a0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 3997 | _SVE_INSN ("ld1sb", 0xa5c0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
| 3998 | _SVE_INSN ("ld1sb", 0xc4208000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DZD, F_OD(1), 0), | |
| 3999 | _SVE_INSN ("ld1sh", 0x84800000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), | |
| 4000 | _SVE_INSN ("ld1sh", 0x84a00000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_SZS, F_OD(1), 0), | |
| 4001 | _SVE_INSN ("ld1sh", 0xa5004000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_DZU, F_OD(1), 0), | |
| 4002 | _SVE_INSN ("ld1sh", 0xa5204000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_SZU, F_OD(1), 0), | |
| 4003 | _SVE_INSN ("ld1sh", 0xc4800000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
| 4004 | _SVE_INSN ("ld1sh", 0xc4a00000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_DZD, F_OD(1), 0), | |
| 4005 | _SVE_INSN ("ld1sh", 0xc4c08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 4006 | _SVE_INSN ("ld1sh", 0xc4e08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DZD, F_OD(1), 0), | |
| 4007 | _SVE_INSN ("ld1sh", 0x84a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SZS, F_OD(1), 0), | |
| 4008 | _SVE_INSN ("ld1sh", 0xa500a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4009 | _SVE_INSN ("ld1sh", 0xa520a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 4010 | _SVE_INSN ("ld1sh", 0xc4a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DZD, F_OD(1), 0), | |
| 4011 | _SVE_INSN ("ld1sw", 0xa4804000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_DZU, F_OD(1), 0), | |
| 4012 | _SVE_INSN ("ld1sw", 0xc5000000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
| 4013 | _SVE_INSN ("ld1sw", 0xc5200000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_DZD, F_OD(1), 0), | |
| 4014 | _SVE_INSN ("ld1sw", 0xc5408000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 4015 | _SVE_INSN ("ld1sw", 0xc5608000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0), | |
| 4016 | _SVE_INSN ("ld1sw", 0xa480a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4017 | _SVE_INSN ("ld1sw", 0xc5208000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0), | |
| 4018 | _SVE_INSN ("ld1w", 0x85004000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), | |
| 4019 | _SVE_INSN ("ld1w", 0x85204000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_SZS, F_OD(1), 0), | |
| 4020 | _SVE_INSN ("ld1w", 0xa5404000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(1), 0), | |
| 4021 | _SVE_INSN ("ld1w", 0xa5604000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_DZU, F_OD(1), 0), | |
| 4022 | _SVE_INSN ("ld1w", 0xc5004000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
| 4023 | _SVE_INSN ("ld1w", 0xc5204000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_DZD, F_OD(1), 0), | |
| 4024 | _SVE_INSN ("ld1w", 0xc540c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 4025 | _SVE_INSN ("ld1w", 0xc560c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0), | |
| 4026 | _SVE_INSN ("ld1w", 0x8520c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_SZS, F_OD(1), 0), | |
| 4027 | _SVE_INSN ("ld1w", 0xa540a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 4028 | _SVE_INSN ("ld1w", 0xa560a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4029 | _SVE_INSN ("ld1w", 0xc520c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0), | |
| 4030 | _SVE_INSN ("ld2b", 0xa420c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(2), 0), | |
| 4031 | _SVE_INSN ("ld2b", 0xa420e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, F_OD(2), 0), | |
| 4032 | _SVE_INSN ("ld2d", 0xa5a0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(2), 0), | |
| 4033 | _SVE_INSN ("ld2d", 0xa5a0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, F_OD(2), 0), | |
| 4034 | _SVE_INSN ("ld2h", 0xa4a0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(2), 0), | |
| 4035 | _SVE_INSN ("ld2h", 0xa4a0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, F_OD(2), 0), | |
| 4036 | _SVE_INSN ("ld2w", 0xa520c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(2), 0), | |
| 4037 | _SVE_INSN ("ld2w", 0xa520e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, F_OD(2), 0), | |
| 4038 | _SVE_INSN ("ld3b", 0xa440c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(3), 0), | |
| 4039 | _SVE_INSN ("ld3b", 0xa440e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_BZU, F_OD(3), 0), | |
| 4040 | _SVE_INSN ("ld3d", 0xa5c0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(3), 0), | |
| 4041 | _SVE_INSN ("ld3d", 0xa5c0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_DZU, F_OD(3), 0), | |
| 4042 | _SVE_INSN ("ld3h", 0xa4c0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(3), 0), | |
| 4043 | _SVE_INSN ("ld3h", 0xa4c0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_HZU, F_OD(3), 0), | |
| 4044 | _SVE_INSN ("ld3w", 0xa540c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(3), 0), | |
| 4045 | _SVE_INSN ("ld3w", 0xa540e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_SZU, F_OD(3), 0), | |
| 4046 | _SVE_INSN ("ld4b", 0xa460c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(4), 0), | |
| 4047 | _SVE_INSN ("ld4b", 0xa460e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, F_OD(4), 0), | |
| 4048 | _SVE_INSN ("ld4d", 0xa5e0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(4), 0), | |
| 4049 | _SVE_INSN ("ld4d", 0xa5e0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, F_OD(4), 0), | |
| 4050 | _SVE_INSN ("ld4h", 0xa4e0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(4), 0), | |
| 4051 | _SVE_INSN ("ld4h", 0xa4e0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, F_OD(4), 0), | |
| 4052 | _SVE_INSN ("ld4w", 0xa560c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(4), 0), | |
| 4053 | _SVE_INSN ("ld4w", 0xa560e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, F_OD(4), 0), | |
| c8d59609 | 4054 | |
| c0890d26 RS |
4055 | _SVE_INSN ("ldff1b", 0x84006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), |
| 4056 | _SVE_INSN ("ldff1b", 0xa4006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_BZU, F_OD(1), 0), | |
| c8d59609 | 4057 | _SVE_INSN ("ldff1b", 0xa4006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_BZU, F_OD(1), 0), |
| c0890d26 | 4058 | _SVE_INSN ("ldff1b", 0xa4206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_HZU, F_OD(1), 0), |
| c8d59609 | 4059 | _SVE_INSN ("ldff1b", 0xa4206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, F_OD(1), 0), |
| c0890d26 | 4060 | _SVE_INSN ("ldff1b", 0xa4406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_SZU, F_OD(1), 0), |
| c8d59609 | 4061 | _SVE_INSN ("ldff1b", 0xa4406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0), |
| c0890d26 | 4062 | _SVE_INSN ("ldff1b", 0xa4606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_DZU, F_OD(1), 0), |
| c8d59609 | 4063 | _SVE_INSN ("ldff1b", 0xa4606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
| c0890d26 RS |
4064 | _SVE_INSN ("ldff1b", 0xc4006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
| 4065 | _SVE_INSN ("ldff1b", 0xc440e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 4066 | _SVE_INSN ("ldff1b", 0x8420e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SZS, F_OD(1), 0), | |
| 4067 | _SVE_INSN ("ldff1b", 0xc420e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DZD, F_OD(1), 0), | |
| c8d59609 | 4068 | |
| c0890d26 | 4069 | _SVE_INSN ("ldff1d", 0xa5e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, F_OD(1), 0), |
| c8d59609 | 4070 | _SVE_INSN ("ldff1d", 0xa5e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
| c0890d26 RS |
4071 | _SVE_INSN ("ldff1d", 0xc5806000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
| 4072 | _SVE_INSN ("ldff1d", 0xc5a06000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW3_22), OP_SVE_DZD, F_OD(1), 0), | |
| 4073 | _SVE_INSN ("ldff1d", 0xc5c0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 4074 | _SVE_INSN ("ldff1d", 0xc5e0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL3), OP_SVE_DZD, F_OD(1), 0), | |
| 4075 | _SVE_INSN ("ldff1d", 0xc5a0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x8), OP_SVE_DZD, F_OD(1), 0), | |
| c8d59609 | 4076 | |
| c0890d26 RS |
4077 | _SVE_INSN ("ldff1h", 0x84806000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), |
| 4078 | _SVE_INSN ("ldff1h", 0x84a06000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_SZS, F_OD(1), 0), | |
| 4079 | _SVE_INSN ("ldff1h", 0xa4a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, F_OD(1), 0), | |
| c8d59609 | 4080 | _SVE_INSN ("ldff1h", 0xa4a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, F_OD(1), 0), |
| c0890d26 | 4081 | _SVE_INSN ("ldff1h", 0xa4c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_SZU, F_OD(1), 0), |
| c8d59609 | 4082 | _SVE_INSN ("ldff1h", 0xa4c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0), |
| c0890d26 | 4083 | _SVE_INSN ("ldff1h", 0xa4e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_DZU, F_OD(1), 0), |
| c8d59609 | 4084 | _SVE_INSN ("ldff1h", 0xa4e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
| c0890d26 RS |
4085 | _SVE_INSN ("ldff1h", 0xc4806000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
| 4086 | _SVE_INSN ("ldff1h", 0xc4a06000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_DZD, F_OD(1), 0), | |
| 4087 | _SVE_INSN ("ldff1h", 0xc4c0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 4088 | _SVE_INSN ("ldff1h", 0xc4e0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DZD, F_OD(1), 0), | |
| 4089 | _SVE_INSN ("ldff1h", 0x84a0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SZS, F_OD(1), 0), | |
| 4090 | _SVE_INSN ("ldff1h", 0xc4a0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DZD, F_OD(1), 0), | |
| c8d59609 | 4091 | |
| c0890d26 RS |
4092 | _SVE_INSN ("ldff1sb", 0x84002000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), |
| 4093 | _SVE_INSN ("ldff1sb", 0xa5806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_DZU, F_OD(1), 0), | |
| c8d59609 | 4094 | _SVE_INSN ("ldff1sb", 0xa5806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
| c0890d26 | 4095 | _SVE_INSN ("ldff1sb", 0xa5a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_SZU, F_OD(1), 0), |
| c8d59609 | 4096 | _SVE_INSN ("ldff1sb", 0xa5a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0), |
| c0890d26 | 4097 | _SVE_INSN ("ldff1sb", 0xa5c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_HZU, F_OD(1), 0), |
| c8d59609 | 4098 | _SVE_INSN ("ldff1sb", 0xa5c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, F_OD(1), 0), |
| c0890d26 RS |
4099 | _SVE_INSN ("ldff1sb", 0xc4002000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
| 4100 | _SVE_INSN ("ldff1sb", 0xc440a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 4101 | _SVE_INSN ("ldff1sb", 0x8420a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SZS, F_OD(1), 0), | |
| 4102 | _SVE_INSN ("ldff1sb", 0xc420a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DZD, F_OD(1), 0), | |
| c8d59609 | 4103 | |
| c0890d26 RS |
4104 | _SVE_INSN ("ldff1sh", 0x84802000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), |
| 4105 | _SVE_INSN ("ldff1sh", 0x84a02000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_SZS, F_OD(1), 0), | |
| 4106 | _SVE_INSN ("ldff1sh", 0xa5006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_DZU, F_OD(1), 0), | |
| c8d59609 | 4107 | _SVE_INSN ("ldff1sh", 0xa5006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
| c0890d26 | 4108 | _SVE_INSN ("ldff1sh", 0xa5206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_SZU, F_OD(1), 0), |
| c8d59609 | 4109 | _SVE_INSN ("ldff1sh", 0xa5206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0), |
| c0890d26 RS |
4110 | _SVE_INSN ("ldff1sh", 0xc4802000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
| 4111 | _SVE_INSN ("ldff1sh", 0xc4a02000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_DZD, F_OD(1), 0), | |
| 4112 | _SVE_INSN ("ldff1sh", 0xc4c0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 4113 | _SVE_INSN ("ldff1sh", 0xc4e0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DZD, F_OD(1), 0), | |
| 4114 | _SVE_INSN ("ldff1sh", 0x84a0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SZS, F_OD(1), 0), | |
| 4115 | _SVE_INSN ("ldff1sh", 0xc4a0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DZD, F_OD(1), 0), | |
| c8d59609 | 4116 | |
| c0890d26 | 4117 | _SVE_INSN ("ldff1sw", 0xa4806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_DZU, F_OD(1), 0), |
| c8d59609 | 4118 | _SVE_INSN ("ldff1sw", 0xa4806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
| c0890d26 RS |
4119 | _SVE_INSN ("ldff1sw", 0xc5002000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
| 4120 | _SVE_INSN ("ldff1sw", 0xc5202000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_DZD, F_OD(1), 0), | |
| 4121 | _SVE_INSN ("ldff1sw", 0xc540a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 4122 | _SVE_INSN ("ldff1sw", 0xc560a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0), | |
| 4123 | _SVE_INSN ("ldff1sw", 0xc520a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0), | |
| c8d59609 | 4124 | |
| c0890d26 RS |
4125 | _SVE_INSN ("ldff1w", 0x85006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), |
| 4126 | _SVE_INSN ("ldff1w", 0x85206000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_SZS, F_OD(1), 0), | |
| 4127 | _SVE_INSN ("ldff1w", 0xa5406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, F_OD(1), 0), | |
| c8d59609 | 4128 | _SVE_INSN ("ldff1w", 0xa5406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0), |
| c0890d26 | 4129 | _SVE_INSN ("ldff1w", 0xa5606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_DZU, F_OD(1), 0), |
| c8d59609 | 4130 | _SVE_INSN ("ldff1w", 0xa5606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
| c0890d26 RS |
4131 | _SVE_INSN ("ldff1w", 0xc5006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
| 4132 | _SVE_INSN ("ldff1w", 0xc5206000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_DZD, F_OD(1), 0), | |
| 4133 | _SVE_INSN ("ldff1w", 0xc540e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
| 4134 | _SVE_INSN ("ldff1w", 0xc560e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0), | |
| 4135 | _SVE_INSN ("ldff1w", 0x8520e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_SZS, F_OD(1), 0), | |
| 4136 | _SVE_INSN ("ldff1w", 0xc520e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0), | |
| c8d59609 | 4137 | |
| c0890d26 RS |
4138 | _SVE_INSN ("ldnf1b", 0xa410a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_BZU, F_OD(1), 0), |
| 4139 | _SVE_INSN ("ldnf1b", 0xa430a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
| 4140 | _SVE_INSN ("ldnf1b", 0xa450a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 4141 | _SVE_INSN ("ldnf1b", 0xa470a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4142 | _SVE_INSN ("ldnf1d", 0xa5f0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4143 | _SVE_INSN ("ldnf1h", 0xa4b0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
| 4144 | _SVE_INSN ("ldnf1h", 0xa4d0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 4145 | _SVE_INSN ("ldnf1h", 0xa4f0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4146 | _SVE_INSN ("ldnf1sb", 0xa590a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4147 | _SVE_INSN ("ldnf1sb", 0xa5b0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 4148 | _SVE_INSN ("ldnf1sb", 0xa5d0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
| 4149 | _SVE_INSN ("ldnf1sh", 0xa510a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4150 | _SVE_INSN ("ldnf1sh", 0xa530a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 4151 | _SVE_INSN ("ldnf1sw", 0xa490a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4152 | _SVE_INSN ("ldnf1w", 0xa550a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 4153 | _SVE_INSN ("ldnf1w", 0xa570a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4154 | _SVE_INSN ("ldnt1b", 0xa400c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0), | |
| 4155 | _SVE_INSN ("ldnt1b", 0xa400e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_BZU, F_OD(1), 0), | |
| 4156 | _SVE_INSN ("ldnt1d", 0xa580c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(1), 0), | |
| 4157 | _SVE_INSN ("ldnt1d", 0xa580e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
| 4158 | _SVE_INSN ("ldnt1h", 0xa480c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(1), 0), | |
| 4159 | _SVE_INSN ("ldnt1h", 0xa480e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
| 4160 | _SVE_INSN ("ldnt1w", 0xa500c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(1), 0), | |
| 4161 | _SVE_INSN ("ldnt1w", 0xa500e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
| 4162 | _SVE_INSN ("ldr", 0x85800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_Pt, SVE_ADDR_RI_S9xVL), {}, 0, 0), | |
| 4163 | _SVE_INSN ("ldr", 0x85804000, 0xffc0e000, sve_misc, 0, OP2 (SVE_Zt, SVE_ADDR_RI_S9xVL), {}, 0, 0), | |
| 4164 | _SVE_INSN ("lsl", 0x04208c00, 0xff20fc00, sve_size_bhs, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVD_BHS, 0, 0), | |
| 4165 | _SVE_INSN ("lsl", 0x04209c00, 0xff20fc00, sve_shift_unpred, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHLIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0), | |
| eae424ae TC |
4166 | _SVE_INSNC ("lsl", 0x04138000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| 4167 | _SVE_INSNC ("lsl", 0x041b8000, 0xff3fe000, sve_size_bhs, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVD_BHS, 0, C_SCAN_MOVPRFX, 2), | |
| 4168 | _SVE_INSNC ("lsl", 0x04038000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHLIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| 4169 | _SVE_INSNC ("lslr", 0x04178000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 RS |
4170 | _SVE_INSN ("lsr", 0x04208400, 0xff20fc00, sve_size_bhs, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVD_BHS, 0, 0), |
| 4171 | _SVE_INSN ("lsr", 0x04209400, 0xff20fc00, sve_shift_unpred, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0), | |
| eae424ae TC |
4172 | _SVE_INSNC ("lsr", 0x04118000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| 4173 | _SVE_INSNC ("lsr", 0x04198000, 0xff3fe000, sve_size_bhs, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVD_BHS, 0, C_SCAN_MOVPRFX, 2), | |
| 4174 | _SVE_INSNC ("lsr", 0x04018000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| 4175 | _SVE_INSNC ("lsrr", 0x04158000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| 4176 | _SVE_INSNC ("mad", 0x0400c000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_16, SVE_Za_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
| 4177 | _SVE_INSNC ("mla", 0x04004000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
| 4178 | _SVE_INSNC ("mls", 0x04006000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
| 4179 | _SVE_INSNC ("movprfx", 0x0420bc00, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), {}, F_SCAN, C_SCAN_MOVPRFX, 0), | |
| 4180 | _SVE_INSNC ("movprfx", 0x04102000, 0xff3ee000, sve_movprfx, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VPV_BHSD, F_SCAN, C_SCAN_MOVPRFX, 0), | |
| 4181 | _SVE_INSNC ("msb", 0x0400e000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_16, SVE_Za_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
| 4182 | _SVE_INSNC ("mul", 0x2530c000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_SIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), | |
| 4183 | _SVE_INSNC ("mul", 0x04100000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 RS |
4184 | _SVE_INSN ("nand", 0x25804210, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), |
| 4185 | _SVE_INSN ("nands", 0x25c04210, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
| eae424ae | 4186 | _SVE_INSNC ("neg", 0x0417a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4187 | _SVE_INSN ("nor", 0x25804200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), |
| 4188 | _SVE_INSN ("nors", 0x25c04200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
| eae424ae | 4189 | _SVE_INSNC ("not", 0x041ea000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4190 | _SVE_INSN ("orn", 0x25804010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), |
| 4191 | _SVE_INSN ("orns", 0x25c04010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
| 4192 | _SVE_INSN ("orr", 0x04603000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, F_HAS_ALIAS, 0), | |
| eae424ae TC |
4193 | _SVE_INSNC ("orr", 0x05000000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_LIMM), OP_SVE_VVU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 1), |
| 4194 | _SVE_INSNC ("orr", 0x04180000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 RS |
4195 | _SVE_INSN ("orr", 0x25804000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), |
| 4196 | _SVE_INSN ("orrs", 0x25c04000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), | |
| 4197 | _SVE_INSN ("orv", 0x04182000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), | |
| 4198 | _SVE_INSN ("pfalse", 0x2518e400, 0xfffffff0, sve_misc, 0, OP1 (SVE_Pd), OP_SVE_B, 0, 0), | |
| 4199 | _SVE_INSN ("pfirst", 0x2558c000, 0xfffffe10, sve_misc, 0, OP3 (SVE_Pd, SVE_Pg4_5, SVE_Pd), OP_SVE_BUB, 0, 2), | |
| 4200 | _SVE_INSN ("pnext", 0x2519c400, 0xff3ffe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pg4_5, SVE_Pd), OP_SVE_VUV_BHSD, 0, 2), | |
| 4201 | _SVE_INSN ("prfb", 0x8400c000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RX), {}, 0, 0), | |
| 4202 | _SVE_INSN ("prfb", 0x84200000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_UUS, 0, 0), | |
| 4203 | _SVE_INSN ("prfb", 0xc4200000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_UUD, 0, 0), | |
| 4204 | _SVE_INSN ("prfb", 0xc4608000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_UUD, 0, 0), | |
| 4205 | _SVE_INSN ("prfb", 0x8400e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_UUS, 0, 0), | |
| 4206 | _SVE_INSN ("prfb", 0x85c00000, 0xffc0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RI_S6xVL), {}, 0, 0), | |
| 4207 | _SVE_INSN ("prfb", 0xc400e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_UUD, 0, 0), | |
| 4208 | _SVE_INSN ("prfd", 0x84206000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW3_22), OP_SVE_UUS, 0, 0), | |
| 4209 | _SVE_INSN ("prfd", 0x8580c000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RX_LSL3), {}, 0, 0), | |
| 4210 | _SVE_INSN ("prfd", 0xc4206000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW3_22), OP_SVE_UUD, 0, 0), | |
| 4211 | _SVE_INSN ("prfd", 0xc460e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_LSL3), OP_SVE_UUD, 0, 0), | |
| 4212 | _SVE_INSN ("prfd", 0x8580e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x8), OP_SVE_UUS, 0, 0), | |
| 4213 | _SVE_INSN ("prfd", 0x85c06000, 0xffc0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RI_S6xVL), {}, 0, 0), | |
| 4214 | _SVE_INSN ("prfd", 0xc580e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x8), OP_SVE_UUD, 0, 0), | |
| 4215 | _SVE_INSN ("prfh", 0x84202000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_UUS, 0, 0), | |
| 4216 | _SVE_INSN ("prfh", 0x8480c000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RX_LSL1), {}, 0, 0), | |
| 4217 | _SVE_INSN ("prfh", 0xc4202000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_UUD, 0, 0), | |
| 4218 | _SVE_INSN ("prfh", 0xc460a000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_UUD, 0, 0), | |
| 4219 | _SVE_INSN ("prfh", 0x8480e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_UUS, 0, 0), | |
| 4220 | _SVE_INSN ("prfh", 0x85c02000, 0xffc0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RI_S6xVL), {}, 0, 0), | |
| 4221 | _SVE_INSN ("prfh", 0xc480e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_UUD, 0, 0), | |
| 4222 | _SVE_INSN ("prfw", 0x84204000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_UUS, 0, 0), | |
| 4223 | _SVE_INSN ("prfw", 0x8500c000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RX_LSL2), {}, 0, 0), | |
| 4224 | _SVE_INSN ("prfw", 0xc4204000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_UUD, 0, 0), | |
| 4225 | _SVE_INSN ("prfw", 0xc460c000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_UUD, 0, 0), | |
| 4226 | _SVE_INSN ("prfw", 0x8500e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_UUS, 0, 0), | |
| 4227 | _SVE_INSN ("prfw", 0x85c04000, 0xffc0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RI_S6xVL), {}, 0, 0), | |
| 4228 | _SVE_INSN ("prfw", 0xc500e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_UUD, 0, 0), | |
| 4229 | _SVE_INSN ("ptest", 0x2550c000, 0xffffc21f, sve_misc, 0, OP2 (SVE_Pg4_10, SVE_Pn), OP_SVE_UB, 0, 0), | |
| 4230 | _SVE_INSN ("ptrue", 0x2518e000, 0xff3ffc10, sve_size_bhsd, 0, OP2 (SVE_Pd, SVE_PATTERN), OP_SVE_VU_BHSD, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 4231 | _SVE_INSN ("ptrues", 0x2519e000, 0xff3ffc10, sve_size_bhsd, 0, OP2 (SVE_Pd, SVE_PATTERN), OP_SVE_VU_BHSD, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 4232 | _SVE_INSN ("punpkhi", 0x05314000, 0xfffffe10, sve_misc, 0, OP2 (SVE_Pd, SVE_Pn), OP_SVE_HB, 0, 0), | |
| 4233 | _SVE_INSN ("punpklo", 0x05304000, 0xfffffe10, sve_misc, 0, OP2 (SVE_Pd, SVE_Pn), OP_SVE_HB, 0, 0), | |
| eae424ae | 4234 | _SVE_INSNC ("rbit", 0x05278000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4235 | _SVE_INSN ("rdffr", 0x2519f000, 0xfffffff0, sve_misc, 0, OP1 (SVE_Pd), OP_SVE_B, 0, 0), |
| 4236 | _SVE_INSN ("rdffr", 0x2518f000, 0xfffffe10, sve_misc, 0, OP2 (SVE_Pd, SVE_Pg4_5), OP_SVE_BZ, 0, 0), | |
| 4237 | _SVE_INSN ("rdffrs", 0x2558f000, 0xfffffe10, sve_misc, 0, OP2 (SVE_Pd, SVE_Pg4_5), OP_SVE_BZ, 0, 0), | |
| 4238 | _SVE_INSN ("rdvl", 0x04bf5000, 0xfffff800, sve_misc, 0, OP2 (Rd, SVE_SIMM6), OP_SVE_XU, 0, 0), | |
| 4239 | _SVE_INSN ("rev", 0x05344000, 0xff3ffe10, sve_size_bhsd, 0, OP2 (SVE_Pd, SVE_Pn), OP_SVE_VV_BHSD, 0, 0), | |
| 4240 | _SVE_INSN ("rev", 0x05383800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_BHSD, 0, 0), | |
| eae424ae TC |
4241 | _SVE_INSNC ("revb", 0x05248000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), |
| 4242 | _SVE_INSNC ("revh", 0x05a58000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0), | |
| 4243 | _SVE_INSNC ("revw", 0x05e68000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0), | |
| 4244 | _SVE_INSNC ("sabd", 0x040c0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 | 4245 | _SVE_INSN ("saddv", 0x04002000, 0xff3fe000, sve_size_bhs, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_DUV_BHS, 0, 0), |
| eae424ae TC |
4246 | _SVE_INSNC ("scvtf", 0x6552a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX, 0), |
| 4247 | _SVE_INSNC ("scvtf", 0x6554a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX, 0), | |
| 4248 | _SVE_INSNC ("scvtf", 0x6594a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX, 0), | |
| 4249 | _SVE_INSNC ("scvtf", 0x65d0a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX, 0), | |
| 4250 | _SVE_INSNC ("scvtf", 0x6556a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, C_SCAN_MOVPRFX, 0), | |
| 4251 | _SVE_INSNC ("scvtf", 0x65d4a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX, 0), | |
| 4252 | _SVE_INSNC ("scvtf", 0x65d6a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0), | |
| 4253 | _SVE_INSNC ("sdiv", 0x04940000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2), | |
| 4254 | _SVE_INSNC ("sdivr", 0x04960000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2), | |
| 4255 | _SVE_INSNC ("sdot", 0x44800000, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD_BH, 0, C_SCAN_MOVPRFX, 0), | |
| 4256 | _SVE_INSNC ("sdot", 0x44a00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), | |
| 4257 | _SVE_INSNC ("sdot", 0x44e00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D_H, 0, C_SCAN_MOVPRFX, 0), | |
| c0890d26 RS |
4258 | _SVE_INSN ("sel", 0x0520c000, 0xff20c000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg4_10, SVE_Zn, SVE_Zm_16), OP_SVE_VUVV_BHSD, F_HAS_ALIAS, 0), |
| 4259 | _SVE_INSN ("sel", 0x25004210, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BUBB, F_HAS_ALIAS, 0), | |
| 4260 | _SVE_INSN ("setffr", 0x252c9000, 0xffffffff, sve_misc, 0, OP0 (), {}, 0, 0), | |
| eae424ae TC |
4261 | _SVE_INSNC ("smax", 0x2528c000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_SIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| 4262 | _SVE_INSNC ("smax", 0x04080000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 | 4263 | _SVE_INSN ("smaxv", 0x04082000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), |
| eae424ae TC |
4264 | _SVE_INSNC ("smin", 0x252ac000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_SIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| 4265 | _SVE_INSNC ("smin", 0x040a0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 | 4266 | _SVE_INSN ("sminv", 0x040a2000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), |
| eae424ae TC |
4267 | _SVE_INSNC ("smulh", 0x04120000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| 4268 | _SVE_INSNC ("splice", 0x052c8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 | 4269 | _SVE_INSN ("sqadd", 0x04201000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), |
| eae424ae | 4270 | _SVE_INSNC ("sqadd", 0x2524c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| c0890d26 RS |
4271 | _SVE_INSN ("sqdecb", 0x0430f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4272 | _SVE_INSN ("sqdecb", 0x0420f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
| eae424ae | 4273 | _SVE_INSNC ("sqdecd", 0x04e0c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4274 | _SVE_INSN ("sqdecd", 0x04f0f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4275 | _SVE_INSN ("sqdecd", 0x04e0f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
| eae424ae | 4276 | _SVE_INSNC ("sqdech", 0x0460c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4277 | _SVE_INSN ("sqdech", 0x0470f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4278 | _SVE_INSN ("sqdech", 0x0460f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
| eae424ae | 4279 | _SVE_INSNC ("sqdecp", 0x252a8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4280 | _SVE_INSN ("sqdecp", 0x252a8c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), |
| 4281 | _SVE_INSN ("sqdecp", 0x252a8800, 0xff3ffe00, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_5, Rd), OP_SVE_XVW_BHSD, 0, 2), | |
| eae424ae | 4282 | _SVE_INSNC ("sqdecw", 0x04a0c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4283 | _SVE_INSN ("sqdecw", 0x04b0f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4284 | _SVE_INSN ("sqdecw", 0x04a0f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
| 4285 | _SVE_INSN ("sqincb", 0x0430f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 4286 | _SVE_INSN ("sqincb", 0x0420f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
| eae424ae | 4287 | _SVE_INSNC ("sqincd", 0x04e0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4288 | _SVE_INSN ("sqincd", 0x04f0f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4289 | _SVE_INSN ("sqincd", 0x04e0f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
| eae424ae | 4290 | _SVE_INSNC ("sqinch", 0x0460c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4291 | _SVE_INSN ("sqinch", 0x0470f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4292 | _SVE_INSN ("sqinch", 0x0460f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
| eae424ae | 4293 | _SVE_INSNC ("sqincp", 0x25288000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4294 | _SVE_INSN ("sqincp", 0x25288c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), |
| 4295 | _SVE_INSN ("sqincp", 0x25288800, 0xff3ffe00, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_5, Rd), OP_SVE_XVW_BHSD, 0, 2), | |
| eae424ae | 4296 | _SVE_INSNC ("sqincw", 0x04a0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4297 | _SVE_INSN ("sqincw", 0x04b0f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4298 | _SVE_INSN ("sqincw", 0x04a0f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
| 4299 | _SVE_INSN ("sqsub", 0x04201800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| eae424ae | 4300 | _SVE_INSNC ("sqsub", 0x2526c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| c0890d26 RS |
4301 | _SVE_INSN ("st1b", 0xe4004000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BUU, F_OD(1), 0), |
| 4302 | _SVE_INSN ("st1b", 0xe4008000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_DUD, F_OD(1), 0), | |
| 4303 | _SVE_INSN ("st1b", 0xe400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DUD, F_OD(1), 0), | |
| 4304 | _SVE_INSN ("st1b", 0xe4204000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_HUU, F_OD(1), 0), | |
| 4305 | _SVE_INSN ("st1b", 0xe4404000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_SUU, F_OD(1), 0), | |
| 4306 | _SVE_INSN ("st1b", 0xe4408000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_SUS, F_OD(1), 0), | |
| 4307 | _SVE_INSN ("st1b", 0xe4604000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_DUU, F_OD(1), 0), | |
| 4308 | _SVE_INSN ("st1b", 0xe400e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_BUU, F_OD(1), 0), | |
| 4309 | _SVE_INSN ("st1b", 0xe420e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HUU, F_OD(1), 0), | |
| 4310 | _SVE_INSN ("st1b", 0xe440a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DUD, F_OD(1), 0), | |
| 4311 | _SVE_INSN ("st1b", 0xe440e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SUU, F_OD(1), 0), | |
| 4312 | _SVE_INSN ("st1b", 0xe460a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SUS, F_OD(1), 0), | |
| 4313 | _SVE_INSN ("st1b", 0xe460e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DUU, F_OD(1), 0), | |
| 4314 | _SVE_INSN ("st1d", 0xe5808000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_DUD, F_OD(1), 0), | |
| 4315 | _SVE_INSN ("st1d", 0xe580a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DUD, F_OD(1), 0), | |
| 4316 | _SVE_INSN ("st1d", 0xe5a08000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW3_14), OP_SVE_DUD, F_OD(1), 0), | |
| 4317 | _SVE_INSN ("st1d", 0xe5a0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL3), OP_SVE_DUD, F_OD(1), 0), | |
| 4318 | _SVE_INSN ("st1d", 0xe5e04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DUU, F_OD(1), 0), | |
| 4319 | _SVE_INSN ("st1d", 0xe5c0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x8), OP_SVE_DUD, F_OD(1), 0), | |
| 4320 | _SVE_INSN ("st1d", 0xe5e0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DUU, F_OD(1), 0), | |
| 4321 | _SVE_INSN ("st1h", 0xe4808000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_DUD, F_OD(1), 0), | |
| 4322 | _SVE_INSN ("st1h", 0xe480a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DUD, F_OD(1), 0), | |
| 4323 | _SVE_INSN ("st1h", 0xe4a04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HUU, F_OD(1), 0), | |
| 4324 | _SVE_INSN ("st1h", 0xe4a08000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_14), OP_SVE_DUD, F_OD(1), 0), | |
| 4325 | _SVE_INSN ("st1h", 0xe4a0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DUD, F_OD(1), 0), | |
| 4326 | _SVE_INSN ("st1h", 0xe4c04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_SUU, F_OD(1), 0), | |
| 4327 | _SVE_INSN ("st1h", 0xe4c08000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_SUS, F_OD(1), 0), | |
| 4328 | _SVE_INSN ("st1h", 0xe4e04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_DUU, F_OD(1), 0), | |
| 4329 | _SVE_INSN ("st1h", 0xe4e08000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_14), OP_SVE_SUS, F_OD(1), 0), | |
| 4330 | _SVE_INSN ("st1h", 0xe4a0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HUU, F_OD(1), 0), | |
| 4331 | _SVE_INSN ("st1h", 0xe4c0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DUD, F_OD(1), 0), | |
| 4332 | _SVE_INSN ("st1h", 0xe4c0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SUU, F_OD(1), 0), | |
| 4333 | _SVE_INSN ("st1h", 0xe4e0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SUS, F_OD(1), 0), | |
| 4334 | _SVE_INSN ("st1h", 0xe4e0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DUU, F_OD(1), 0), | |
| 4335 | _SVE_INSN ("st1w", 0xe5008000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_DUD, F_OD(1), 0), | |
| 4336 | _SVE_INSN ("st1w", 0xe500a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DUD, F_OD(1), 0), | |
| 4337 | _SVE_INSN ("st1w", 0xe5208000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_14), OP_SVE_DUD, F_OD(1), 0), | |
| 4338 | _SVE_INSN ("st1w", 0xe520a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DUD, F_OD(1), 0), | |
| 4339 | _SVE_INSN ("st1w", 0xe5404000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SUU, F_OD(1), 0), | |
| 4340 | _SVE_INSN ("st1w", 0xe5408000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_SUS, F_OD(1), 0), | |
| 4341 | _SVE_INSN ("st1w", 0xe5604000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_DUU, F_OD(1), 0), | |
| 4342 | _SVE_INSN ("st1w", 0xe5608000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_14), OP_SVE_SUS, F_OD(1), 0), | |
| 4343 | _SVE_INSN ("st1w", 0xe540a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DUD, F_OD(1), 0), | |
| 4344 | _SVE_INSN ("st1w", 0xe540e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SUU, F_OD(1), 0), | |
| 4345 | _SVE_INSN ("st1w", 0xe560a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_SUS, F_OD(1), 0), | |
| 4346 | _SVE_INSN ("st1w", 0xe560e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DUU, F_OD(1), 0), | |
| 4347 | _SVE_INSN ("st2b", 0xe4206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BUU, F_OD(2), 0), | |
| 4348 | _SVE_INSN ("st2b", 0xe430e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, F_OD(2), 0), | |
| 4349 | _SVE_INSN ("st2d", 0xe5a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DUU, F_OD(2), 0), | |
| 4350 | _SVE_INSN ("st2d", 0xe5b0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, F_OD(2), 0), | |
| 4351 | _SVE_INSN ("st2h", 0xe4a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HUU, F_OD(2), 0), | |
| 4352 | _SVE_INSN ("st2h", 0xe4b0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, F_OD(2), 0), | |
| 4353 | _SVE_INSN ("st2w", 0xe5206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SUU, F_OD(2), 0), | |
| 4354 | _SVE_INSN ("st2w", 0xe530e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, F_OD(2), 0), | |
| 4355 | _SVE_INSN ("st3b", 0xe4406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BUU, F_OD(3), 0), | |
| 4356 | _SVE_INSN ("st3b", 0xe450e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_BUU, F_OD(3), 0), | |
| 4357 | _SVE_INSN ("st3d", 0xe5c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DUU, F_OD(3), 0), | |
| 4358 | _SVE_INSN ("st3d", 0xe5d0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_DUU, F_OD(3), 0), | |
| 4359 | _SVE_INSN ("st3h", 0xe4c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HUU, F_OD(3), 0), | |
| 4360 | _SVE_INSN ("st3h", 0xe4d0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_HUU, F_OD(3), 0), | |
| 4361 | _SVE_INSN ("st3w", 0xe5406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SUU, F_OD(3), 0), | |
| 4362 | _SVE_INSN ("st3w", 0xe550e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_SUU, F_OD(3), 0), | |
| 4363 | _SVE_INSN ("st4b", 0xe4606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BUU, F_OD(4), 0), | |
| 4364 | _SVE_INSN ("st4b", 0xe470e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, F_OD(4), 0), | |
| 4365 | _SVE_INSN ("st4d", 0xe5e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DUU, F_OD(4), 0), | |
| 4366 | _SVE_INSN ("st4d", 0xe5f0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, F_OD(4), 0), | |
| 4367 | _SVE_INSN ("st4h", 0xe4e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HUU, F_OD(4), 0), | |
| 4368 | _SVE_INSN ("st4h", 0xe4f0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, F_OD(4), 0), | |
| 4369 | _SVE_INSN ("st4w", 0xe5606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SUU, F_OD(4), 0), | |
| 4370 | _SVE_INSN ("st4w", 0xe570e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, F_OD(4), 0), | |
| 4371 | _SVE_INSN ("stnt1b", 0xe4006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BUU, F_OD(1), 0), | |
| 4372 | _SVE_INSN ("stnt1b", 0xe410e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_BUU, F_OD(1), 0), | |
| 4373 | _SVE_INSN ("stnt1d", 0xe5806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DUU, F_OD(1), 0), | |
| 4374 | _SVE_INSN ("stnt1d", 0xe590e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DUU, F_OD(1), 0), | |
| 4375 | _SVE_INSN ("stnt1h", 0xe4806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HUU, F_OD(1), 0), | |
| 4376 | _SVE_INSN ("stnt1h", 0xe490e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HUU, F_OD(1), 0), | |
| 4377 | _SVE_INSN ("stnt1w", 0xe5006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SUU, F_OD(1), 0), | |
| 4378 | _SVE_INSN ("stnt1w", 0xe510e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SUU, F_OD(1), 0), | |
| 4379 | _SVE_INSN ("str", 0xe5800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_Pt, SVE_ADDR_RI_S9xVL), {}, 0, 0), | |
| 4380 | _SVE_INSN ("str", 0xe5804000, 0xffc0e000, sve_misc, 0, OP2 (SVE_Zt, SVE_ADDR_RI_S9xVL), {}, 0, 0), | |
| 4381 | _SVE_INSN ("sub", 0x04200400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| eae424ae TC |
4382 | _SVE_INSNC ("sub", 0x2521c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| 4383 | _SVE_INSNC ("sub", 0x04010000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| 4384 | _SVE_INSNC ("subr", 0x2523c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), | |
| 4385 | _SVE_INSNC ("subr", 0x04030000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 RS |
4386 | _SVE_INSN ("sunpkhi", 0x05313800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0), |
| 4387 | _SVE_INSN ("sunpklo", 0x05303800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0), | |
| eae424ae TC |
4388 | _SVE_INSNC ("sxtb", 0x0410a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), |
| 4389 | _SVE_INSNC ("sxth", 0x0492a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0), | |
| 4390 | _SVE_INSNC ("sxtw", 0x04d4a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0), | |
| c0890d26 RS |
4391 | _SVE_INSN ("tbl", 0x05203000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_VVV_BHSD, F_OD(1), 0), |
| 4392 | _SVE_INSN ("trn1", 0x05205000, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), | |
| 4393 | _SVE_INSN ("trn1", 0x05207000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| 4394 | _SVE_INSN ("trn2", 0x05205400, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), | |
| 4395 | _SVE_INSN ("trn2", 0x05207400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| eae424ae | 4396 | _SVE_INSNC ("uabd", 0x040d0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| c0890d26 | 4397 | _SVE_INSN ("uaddv", 0x04012000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_DUV_BHSD, 0, 0), |
| eae424ae TC |
4398 | _SVE_INSNC ("ucvtf", 0x6553a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX, 0), |
| 4399 | _SVE_INSNC ("ucvtf", 0x6555a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX, 0), | |
| 4400 | _SVE_INSNC ("ucvtf", 0x6595a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX, 0), | |
| 4401 | _SVE_INSNC ("ucvtf", 0x65d1a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX, 0), | |
| 4402 | _SVE_INSNC ("ucvtf", 0x6557a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, C_SCAN_MOVPRFX, 0), | |
| 4403 | _SVE_INSNC ("ucvtf", 0x65d5a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX, 0), | |
| 4404 | _SVE_INSNC ("ucvtf", 0x65d7a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0), | |
| 4405 | _SVE_INSNC ("udiv", 0x04950000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2), | |
| 4406 | _SVE_INSNC ("udivr", 0x04970000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2), | |
| 4407 | _SVE_INSNC ("udot", 0x44800400, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD_BH, 0, C_SCAN_MOVPRFX, 0), | |
| 4408 | _SVE_INSNC ("udot", 0x44a00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), | |
| 4409 | _SVE_INSNC ("udot", 0x44e00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D_H, 0, C_SCAN_MOVPRFX, 0), | |
| 4410 | _SVE_INSNC ("umax", 0x2529c000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_UIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), | |
| 4411 | _SVE_INSNC ("umax", 0x04090000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 | 4412 | _SVE_INSN ("umaxv", 0x04092000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), |
| eae424ae TC |
4413 | _SVE_INSNC ("umin", 0x252bc000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_UIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| 4414 | _SVE_INSNC ("umin", 0x040b0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
| c0890d26 | 4415 | _SVE_INSN ("uminv", 0x040b2000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), |
| eae424ae | 4416 | _SVE_INSNC ("umulh", 0x04130000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
| c0890d26 | 4417 | _SVE_INSN ("uqadd", 0x04201400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), |
| eae424ae | 4418 | _SVE_INSNC ("uqadd", 0x2525c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| c0890d26 RS |
4419 | _SVE_INSN ("uqdecb", 0x0420fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4420 | _SVE_INSN ("uqdecb", 0x0430fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| eae424ae | 4421 | _SVE_INSNC ("uqdecd", 0x04e0cc00, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4422 | _SVE_INSN ("uqdecd", 0x04e0fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4423 | _SVE_INSN ("uqdecd", 0x04f0fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| eae424ae | 4424 | _SVE_INSNC ("uqdech", 0x0460cc00, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4425 | _SVE_INSN ("uqdech", 0x0460fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4426 | _SVE_INSN ("uqdech", 0x0470fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| eae424ae | 4427 | _SVE_INSNC ("uqdecp", 0x252b8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4428 | _SVE_INSN ("uqdecp", 0x252b8800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_WV_BHSD, 0, 0), |
| 4429 | _SVE_INSN ("uqdecp", 0x252b8c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), | |
| eae424ae | 4430 | _SVE_INSNC ("uqdecw", 0x04a0cc00, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4431 | _SVE_INSN ("uqdecw", 0x04a0fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4432 | _SVE_INSN ("uqdecw", 0x04b0fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 4433 | _SVE_INSN ("uqincb", 0x0420f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 4434 | _SVE_INSN ("uqincb", 0x0430f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| eae424ae | 4435 | _SVE_INSNC ("uqincd", 0x04e0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4436 | _SVE_INSN ("uqincd", 0x04e0f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4437 | _SVE_INSN ("uqincd", 0x04f0f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| eae424ae | 4438 | _SVE_INSNC ("uqinch", 0x0460c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4439 | _SVE_INSN ("uqinch", 0x0460f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4440 | _SVE_INSN ("uqinch", 0x0470f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| eae424ae | 4441 | _SVE_INSNC ("uqincp", 0x25298000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4442 | _SVE_INSN ("uqincp", 0x25298800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_WV_BHSD, 0, 0), |
| 4443 | _SVE_INSN ("uqincp", 0x25298c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), | |
| eae424ae | 4444 | _SVE_INSNC ("uqincw", 0x04a0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
| c0890d26 RS |
4445 | _SVE_INSN ("uqincw", 0x04a0f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
| 4446 | _SVE_INSN ("uqincw", 0x04b0f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
| 4447 | _SVE_INSN ("uqsub", 0x04201c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| eae424ae | 4448 | _SVE_INSNC ("uqsub", 0x2527c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
| c0890d26 RS |
4449 | _SVE_INSN ("uunpkhi", 0x05333800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0), |
| 4450 | _SVE_INSN ("uunpklo", 0x05323800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0), | |
| eae424ae TC |
4451 | _SVE_INSNC ("uxtb", 0x0411a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), |
| 4452 | _SVE_INSNC ("uxth", 0x0493a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0), | |
| 4453 | _SVE_INSNC ("uxtw", 0x04d5a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0), | |
| c0890d26 RS |
4454 | _SVE_INSN ("uzp1", 0x05204800, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), |
| 4455 | _SVE_INSN ("uzp1", 0x05206800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| 4456 | _SVE_INSN ("uzp2", 0x05204c00, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), | |
| 4457 | _SVE_INSN ("uzp2", 0x05206c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| 4458 | _SVE_INSN ("whilele", 0x25200410, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0), | |
| 4459 | _SVE_INSN ("whilele", 0x25201410, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
| 4460 | _SVE_INSN ("whilelo", 0x25200c00, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0), | |
| 4461 | _SVE_INSN ("whilelo", 0x25201c00, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
| 4462 | _SVE_INSN ("whilels", 0x25200c10, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0), | |
| 4463 | _SVE_INSN ("whilels", 0x25201c10, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
| 4464 | _SVE_INSN ("whilelt", 0x25200400, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0), | |
| 4465 | _SVE_INSN ("whilelt", 0x25201400, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
| 4466 | _SVE_INSN ("wrffr", 0x25289000, 0xfffffe1f, sve_misc, 0, OP1 (SVE_Pn), OP_SVE_B, 0, 0), | |
| 4467 | _SVE_INSN ("zip1", 0x05204000, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), | |
| 4468 | _SVE_INSN ("zip1", 0x05206000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| 4469 | _SVE_INSN ("zip2", 0x05204400, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), | |
| 4470 | _SVE_INSN ("zip2", 0x05206400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
| eae424ae | 4471 | _SVE_INSNC ("bic", 0x05800000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, C_SCAN_MOVPRFX, 1), |
| c0890d26 RS |
4472 | _SVE_INSN ("cmple", 0x24008000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0), |
| 4473 | _SVE_INSN ("cmplo", 0x24000010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0), | |
| 4474 | _SVE_INSN ("cmpls", 0x24000000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0), | |
| 4475 | _SVE_INSN ("cmplt", 0x24008010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0), | |
| eae424ae | 4476 | _SVE_INSNC ("eon", 0x05400000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, C_SCAN_MOVPRFX, 1), |
| 582e12bf RS |
4477 | _SVE_INSN ("facle", 0x6500c010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0), |
| 4478 | _SVE_INSN ("faclt", 0x6500e010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0), | |
| 4479 | _SVE_INSN ("fcmle", 0x65004000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0), | |
| 4480 | _SVE_INSN ("fcmlt", 0x65004010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0), | |
| 4481 | _SVE_INSN ("fmov", 0x2538c000, 0xff3fffe0, sve_size_hsd, 0, OP2 (SVE_Zd, FPIMM0), OP_SVE_V_HSD, F_ALIAS | F_PSEUDO, 0), | |
| eae424ae TC |
4482 | _SVE_INSNC ("fmov", 0x05104000, 0xff30ffe0, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, FPIMM0), OP_SVE_VM_HSD, F_ALIAS | F_PSEUDO, C_SCAN_MOVPRFX, 0), |
| 4483 | _SVE_INSNC ("orn", 0x05000000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, C_SCAN_MOVPRFX, 1), | |
| 4bd13cde | 4484 | |
| 65a55fbb TC |
4485 | /* SIMD Dot Product (optional in v8.2-A). */ |
| 4486 | DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), | |
| 4487 | DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), | |
| ff329288 TC |
4488 | DOT_INSN ("udot", 0x2f00e000, 0xbf00f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), |
| 4489 | DOT_INSN ("sdot", 0xf00e000, 0xbf00f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), | |
| e9dbdd80 TC |
4490 | /* Crypto SHA2 (optional in ARMv8.2-a). */ |
| 4491 | SHA2_INSN ("sha512h", 0xce608000, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0), | |
| 4492 | SHA2_INSN ("sha512h2", 0xce608400, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0), | |
| 4493 | SHA2_INSN ("sha512su0", 0xcec08000, 0xfffffc00, cryptosha2, OP2 (Vd, Vn), QL_V2SAME2D, 0), | |
| 4494 | SHA2_INSN ("sha512su1", 0xce608800, 0xffe0fc00, cryptosha2, OP3 (Vd, Vn, Vm), QL_V3SAME2D, 0), | |
| 4495 | /* Crypto SHA3 (optional in ARMv8.2-a). */ | |
| 4496 | SHA3_INSN ("eor3", 0xce000000, 0xffe08000, cryptosha3, OP4 (Vd, Vn, Vm, Va), QL_V4SAME16B, 0), | |
| 4497 | SHA3_INSN ("rax1", 0xce608c00, 0xffe0fc00, cryptosha3, OP3 (Vd, Vn, Vm), QL_V3SAME2D, 0), | |
| 4498 | SHA3_INSN ("xar", 0xce800000, 0xffe00000, cryptosha3, OP4 (Vd, Vn, Vm, IMM), QL_XAR, 0), | |
| 4499 | SHA3_INSN ("bcax", 0xce200000, 0xffe08000, cryptosha3, OP4 (Vd, Vn, Vm, Va), QL_V4SAME16B, 0), | |
| 4500 | /* Crypto SM3 (optional in ARMv8.2-a). */ | |
| 4501 | SM4_INSN ("sm3ss1", 0xce400000, 0xffe08000, cryptosm3, OP4 (Vd, Vn, Vm, Va), QL_V4SAME4S, 0), | |
| 4502 | SM4_INSN ("sm3tt1a", 0xce408000, 0xffe0cc00, cryptosm3, OP3 (Vd, Vn, Em), QL_SM3TT, 0), | |
| 4503 | SM4_INSN ("sm3tt1b", 0xce408400, 0xffe0cc00, cryptosm3, OP3 (Vd, Vn, Em), QL_SM3TT, 0), | |
| 4504 | SM4_INSN ("sm3tt2a", 0xce408800, 0xffe0cc00, cryptosm3, OP3 (Vd, Vn, Em), QL_SM3TT, 0), | |
| 4505 | SM4_INSN ("sm3tt2b", 0xce408c00, 0xffe0cc00, cryptosm3, OP3 (Vd, Vn, Em), QL_SM3TT, 0), | |
| 4506 | SM4_INSN ("sm3partw1", 0xce60c000, 0xffe0fc00, cryptosm3, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0), | |
| 4507 | SM4_INSN ("sm3partw2", 0xce60c400, 0xffe0fc00, cryptosm3, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0), | |
| 4508 | /* Crypto SM4 (optional in ARMv8.2-a). */ | |
| 4509 | SM4_INSN ("sm4e", 0xcec08400, 0xfffffc00, cryptosm4, OP2 (Vd, Vn), QL_V2SAME4S, 0), | |
| 4510 | SM4_INSN ("sm4ekey", 0xce60c800, 0xffe0fc00, cryptosm4, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0), | |
| 4511 | /* Crypto FP16 (optional in ARMv8.2-a). */ | |
| 4512 | FP16_V8_2_INSN ("fmlal", 0xe20ec00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML2S, 0), | |
| 4513 | FP16_V8_2_INSN ("fmlsl", 0xea0ec00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML2S, 0), | |
| 4514 | FP16_V8_2_INSN ("fmlal2", 0x2e20cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML2S, 0), | |
| 4515 | FP16_V8_2_INSN ("fmlsl2", 0x2ea0cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML2S, 0), | |
| 4516 | ||
| 4517 | FP16_V8_2_INSN ("fmlal", 0x4e20ec00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0), | |
| 4518 | FP16_V8_2_INSN ("fmlsl", 0x4ea0ec00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0), | |
| 4519 | FP16_V8_2_INSN ("fmlal2", 0x6e20cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0), | |
| 4520 | FP16_V8_2_INSN ("fmlsl2", 0x6ea0cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0), | |
| 4521 | ||
| 369c9167 TC |
4522 | FP16_V8_2_INSN ("fmlal", 0xf800000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0), |
| 4523 | FP16_V8_2_INSN ("fmlsl", 0xf804000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0), | |
| 4524 | FP16_V8_2_INSN ("fmlal2", 0x2f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0), | |
| 4525 | FP16_V8_2_INSN ("fmlsl2", 0x2f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0), | |
| e9dbdd80 | 4526 | |
| 369c9167 TC |
4527 | FP16_V8_2_INSN ("fmlal", 0x4f800000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0), |
| 4528 | FP16_V8_2_INSN ("fmlsl", 0x4f804000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0), | |
| 4529 | FP16_V8_2_INSN ("fmlal2", 0x6f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0), | |
| 4530 | FP16_V8_2_INSN ("fmlsl2", 0x6f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0), | |
| e9dbdd80 TC |
4531 | /* System extensions ARMv8.4-a. */ |
| 4532 | V8_4_INSN ("cfinv", 0xd500401f, 0xffffffff, ic_system, OP0 (), {}, 0), | |
| 4533 | V8_4_INSN ("rmif", 0xba000400, 0xffe07c10, ic_system, OP3 (Rn, IMM_2, MASK), QL_RMIF, 0), | |
| 4534 | V8_4_INSN ("setf8", 0x3a00080d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0), | |
| 4535 | V8_4_INSN ("setf16", 0x3a00480d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0), | |
| 4536 | /* Memory access instructions ARMv8.4-a. */ | |
| 4537 | V8_4_INSN ("stlurb" , 0x19000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
| 4538 | V8_4_INSN ("ldapurb", 0x19400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
| 4539 | V8_4_INSN ("ldapursb", 0x19c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
| 4540 | V8_4_INSN ("ldapursb", 0x19800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), | |
| 4541 | V8_4_INSN ("stlurh", 0x59000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
| 4542 | V8_4_INSN ("ldapurh", 0x59400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
| 4543 | V8_4_INSN ("ldapursh", 0x59c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
| 4544 | V8_4_INSN ("ldapursh", 0x59800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), | |
| 4545 | V8_4_INSN ("stlur", 0x99000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
| 4546 | V8_4_INSN ("ldapur", 0x99400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
| 4547 | V8_4_INSN ("ldapursw", 0x99800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), | |
| 4548 | V8_4_INSN ("stlur", 0xd9000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), | |
| 4549 | V8_4_INSN ("ldapur", 0xd9400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), | |
| eae424ae | 4550 | {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, |
| a06ea964 NC |
4551 | }; |
| 4552 | ||
| 4553 | #ifdef AARCH64_OPERANDS | |
| 4554 | #undef AARCH64_OPERANDS | |
| 4555 | #endif | |
| 4556 | ||
| 4557 | /* Macro-based operand decription; this will be fed into aarch64-gen for it | |
| 4558 | to generate the structure aarch64_operands and the function | |
| 4559 | aarch64_insert_operand and aarch64_extract_operand. | |
| 4560 | ||
| 4561 | These inserters and extracters in the description execute the conversion | |
| 4562 | between the aarch64_opnd_info and value in the operand-related instruction | |
| 4563 | field(s). */ | |
| 4564 | ||
| 4565 | /* Y expects arguments (left to right) to be operand class, inserter/extractor | |
| 4566 | name suffix, operand name, flags, related bitfield(s) and description. | |
| 4567 | X only differs from Y by having the operand inserter and extractor names | |
| 4568 | listed separately. */ | |
| 4569 | ||
| 4570 | #define AARCH64_OPERANDS \ | |
| 4571 | Y(INT_REG, regno, "Rd", 0, F(FLD_Rd), "an integer register") \ | |
| 4572 | Y(INT_REG, regno, "Rn", 0, F(FLD_Rn), "an integer register") \ | |
| 4573 | Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \ | |
| 4574 | Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register") \ | |
| 4575 | Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register") \ | |
| bd7ceb8d SD |
4576 | Y(INT_REG, regno, "Rt_SP", OPD_F_MAYBE_SP, F(FLD_Rt), \ |
| 4577 | "an integer or stack pointer register") \ | |
| a06ea964 NC |
4578 | Y(INT_REG, regno, "Rs", 0, F(FLD_Rs), "an integer register") \ |
| 4579 | Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register") \ | |
| 4580 | X(INT_REG, ins_regno, ext_regrt_sysins, "Rt_SYS", 0, F(FLD_Rt), \ | |
| 4581 | "an integer register") \ | |
| 4582 | Y(INT_REG, regno, "Rd_SP", OPD_F_MAYBE_SP, F(FLD_Rd), \ | |
| 4583 | "an integer or stack pointer register") \ | |
| 4584 | Y(INT_REG, regno, "Rn_SP", OPD_F_MAYBE_SP, F(FLD_Rn), \ | |
| 4585 | "an integer or stack pointer register") \ | |
| c84364ec SN |
4586 | Y(INT_REG, regno, "Rm_SP", OPD_F_MAYBE_SP, F(FLD_Rm), \ |
| 4587 | "an integer or stack pointer register") \ | |
| ee804238 JW |
4588 | X(INT_REG, 0, ext_regno_pair, "PAIRREG", 0, F(), \ |
| 4589 | "the second reg of a pair") \ | |
| a06ea964 NC |
4590 | Y(MODIFIED_REG, reg_extended, "Rm_EXT", 0, F(), \ |
| 4591 | "an integer register with optional extension") \ | |
| 4592 | Y(MODIFIED_REG, reg_shifted, "Rm_SFT", 0, F(), \ | |
| 4593 | "an integer register with optional shift") \ | |
| 4594 | Y(FP_REG, regno, "Fd", 0, F(FLD_Rd), "a floating-point register") \ | |
| 4595 | Y(FP_REG, regno, "Fn", 0, F(FLD_Rn), "a floating-point register") \ | |
| 4596 | Y(FP_REG, regno, "Fm", 0, F(FLD_Rm), "a floating-point register") \ | |
| 4597 | Y(FP_REG, regno, "Fa", 0, F(FLD_Ra), "a floating-point register") \ | |
| 4598 | Y(FP_REG, ft, "Ft", 0, F(FLD_Rt), "a floating-point register") \ | |
| 4599 | Y(FP_REG, regno, "Ft2", 0, F(FLD_Rt2), "a floating-point register") \ | |
| 4600 | Y(SISD_REG, regno, "Sd", 0, F(FLD_Rd), "a SIMD scalar register") \ | |
| 4601 | Y(SISD_REG, regno, "Sn", 0, F(FLD_Rn), "a SIMD scalar register") \ | |
| 4602 | Y(SISD_REG, regno, "Sm", 0, F(FLD_Rm), "a SIMD scalar register") \ | |
| f42f1a1d | 4603 | Y(SIMD_REG, regno, "Va", 0, F(FLD_Ra), "a SIMD vector register") \ |
| a06ea964 NC |
4604 | Y(SIMD_REG, regno, "Vd", 0, F(FLD_Rd), "a SIMD vector register") \ |
| 4605 | Y(SIMD_REG, regno, "Vn", 0, F(FLD_Rn), "a SIMD vector register") \ | |
| 4606 | Y(SIMD_REG, regno, "Vm", 0, F(FLD_Rm), "a SIMD vector register") \ | |
| 4607 | Y(FP_REG, regno, "VdD1", 0, F(FLD_Rd), \ | |
| 4608 | "the top half of a 128-bit FP/SIMD register") \ | |
| 4609 | Y(FP_REG, regno, "VnD1", 0, F(FLD_Rn), \ | |
| 4610 | "the top half of a 128-bit FP/SIMD register") \ | |
| 4611 | Y(SIMD_ELEMENT, reglane, "Ed", 0, F(FLD_Rd), \ | |
| 4612 | "a SIMD vector element") \ | |
| 4613 | Y(SIMD_ELEMENT, reglane, "En", 0, F(FLD_Rn), \ | |
| 4614 | "a SIMD vector element") \ | |
| 4615 | Y(SIMD_ELEMENT, reglane, "Em", 0, F(FLD_Rm), \ | |
| 4616 | "a SIMD vector element") \ | |
| 369c9167 TC |
4617 | Y(SIMD_ELEMENT, reglane, "Em16", 0, F(FLD_Rm), \ |
| 4618 | "a SIMD vector element limited to V0-V15") \ | |
| a06ea964 NC |
4619 | Y(SIMD_REGLIST, reglist, "LVn", 0, F(FLD_Rn), \ |
| 4620 | "a SIMD vector register list") \ | |
| 4621 | Y(SIMD_REGLIST, ldst_reglist, "LVt", 0, F(), \ | |
| 4622 | "a SIMD vector register list") \ | |
| 4623 | Y(SIMD_REGLIST, ldst_reglist_r, "LVt_AL", 0, F(), \ | |
| 4624 | "a SIMD vector register list") \ | |
| 4625 | Y(SIMD_REGLIST, ldst_elemlist, "LEt", 0, F(), \ | |
| 4626 | "a SIMD vector element list") \ | |
| a6a51754 | 4627 | Y(IMMEDIATE, imm, "CRn", 0, F(FLD_CRn), \ |
| a06ea964 | 4628 | "a 4-bit opcode field named for historical reasons C0 - C15") \ |
| a6a51754 | 4629 | Y(IMMEDIATE, imm, "CRm", 0, F(FLD_CRm), \ |
| a06ea964 NC |
4630 | "a 4-bit opcode field named for historical reasons C0 - C15") \ |
| 4631 | Y(IMMEDIATE, imm, "IDX", 0, F(FLD_imm4), \ | |
| 4632 | "an immediate as the index of the least significant byte") \ | |
| f42f1a1d TC |
4633 | Y(IMMEDIATE, imm, "MASK", 0, F(FLD_imm4_2), \ |
| 4634 | "an immediate as the index of the least significant byte") \ | |
| a06ea964 NC |
4635 | Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSL", 0, F(), \ |
| 4636 | "a left shift amount for an AdvSIMD register") \ | |
| 4637 | Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSR", 0, F(), \ | |
| 4638 | "a right shift amount for an AdvSIMD register") \ | |
| 4639 | Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM", 0, F(), \ | |
| 4640 | "an immediate") \ | |
| 4641 | Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM_SFT", 0, F(), \ | |
| 4642 | "an 8-bit unsigned immediate with optional shift") \ | |
| 4643 | Y(IMMEDIATE, advsimd_imm_modified, "SIMD_FPIMM", 0, F(), \ | |
| 4644 | "an 8-bit floating-point constant") \ | |
| 4645 | X(IMMEDIATE, 0, ext_shll_imm, "SHLL_IMM", 0, F(), \ | |
| 4646 | "an immediate shift amount of 8, 16 or 32") \ | |
| 4647 | X(IMMEDIATE, 0, 0, "IMM0", 0, F(), "0") \ | |
| 4648 | X(IMMEDIATE, 0, 0, "FPIMM0", 0, F(), "0.0") \ | |
| aa2aa4c6 | 4649 | Y(IMMEDIATE, fpimm, "FPIMM", 0, F(FLD_imm8), \ |
| a06ea964 NC |
4650 | "an 8-bit floating-point constant") \ |
| 4651 | Y(IMMEDIATE, imm, "IMMR", 0, F(FLD_immr), \ | |
| 4652 | "the right rotate amount") \ | |
| 4653 | Y(IMMEDIATE, imm, "IMMS", 0, F(FLD_imm6), \ | |
| 4654 | "the leftmost bit number to be moved from the source") \ | |
| 4655 | Y(IMMEDIATE, imm, "WIDTH", 0, F(FLD_imm6), \ | |
| 4656 | "the width of the bit-field") \ | |
| f42f1a1d TC |
4657 | Y(IMMEDIATE, imm, "IMM", 0, F(FLD_imm6), "an immediate") \ |
| 4658 | Y(IMMEDIATE, imm, "IMM_2", 0, F(FLD_imm6_2), "an immediate") \ | |
| a06ea964 NC |
4659 | Y(IMMEDIATE, imm, "UIMM3_OP1", 0, F(FLD_op1), \ |
| 4660 | "a 3-bit unsigned immediate") \ | |
| 4661 | Y(IMMEDIATE, imm, "UIMM3_OP2", 0, F(FLD_op2), \ | |
| 4662 | "a 3-bit unsigned immediate") \ | |
| 4663 | Y(IMMEDIATE, imm, "UIMM4", 0, F(FLD_CRm), \ | |
| 4664 | "a 4-bit unsigned immediate") \ | |
| 193614f2 SD |
4665 | Y(IMMEDIATE, imm, "UIMM4_ADDG", 0, F(FLD_imm4_3), \ |
| 4666 | "a 4-bit unsigned Logical Address Tag modifier") \ | |
| a06ea964 NC |
4667 | Y(IMMEDIATE, imm, "UIMM7", 0, F(FLD_CRm, FLD_op2), \ |
| 4668 | "a 7-bit unsigned immediate") \ | |
| 193614f2 SD |
4669 | Y(IMMEDIATE, imm, "UIMM10", OPD_F_SHIFT_BY_4, F(FLD_immr), \ |
| 4670 | "a 10-bit unsigned multiple of 16") \ | |
| a06ea964 NC |
4671 | Y(IMMEDIATE, imm, "BIT_NUM", 0, F(FLD_b5, FLD_b40), \ |
| 4672 | "the bit number to be tested") \ | |
| 4673 | Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16), \ | |
| 4674 | "a 16-bit unsigned immediate") \ | |
| 4675 | Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \ | |
| 4676 | "a 5-bit unsigned immediate") \ | |
| e950b345 RS |
4677 | Y(IMMEDIATE, imm, "SIMM5", OPD_F_SEXT, F(FLD_imm5), \ |
| 4678 | "a 5-bit signed immediate") \ | |
| a06ea964 NC |
4679 | Y(IMMEDIATE, imm, "NZCV", 0, F(FLD_nzcv), \ |
| 4680 | "a flag bit specifier giving an alternative value for each flag") \ | |
| 4681 | Y(IMMEDIATE, limm, "LIMM", 0, F(FLD_N,FLD_immr,FLD_imms), \ | |
| 4682 | "Logical immediate") \ | |
| 4683 | Y(IMMEDIATE, aimm, "AIMM", 0, F(FLD_shift,FLD_imm12), \ | |
| 4684 | "a 12-bit unsigned immediate with optional left shift of 12 bits")\ | |
| 4685 | Y(IMMEDIATE, imm_half, "HALF", 0, F(FLD_imm16), \ | |
| 4686 | "a 16-bit immediate with optional left shift") \ | |
| 4687 | Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale), \ | |
| 4688 | "the number of bits after the binary point in the fixed-point value")\ | |
| 4689 | X(IMMEDIATE, 0, 0, "IMM_MOV", 0, F(), "an immediate") \ | |
| 582e12bf | 4690 | Y(IMMEDIATE, imm_rotate2, "IMM_ROT1", 0, F(FLD_rotate1), \ |
| c2c4ff8d | 4691 | "a 2-bit rotation specifier for complex arithmetic operations") \ |
| 582e12bf | 4692 | Y(IMMEDIATE, imm_rotate2, "IMM_ROT2", 0, F(FLD_rotate2), \ |
| c2c4ff8d | 4693 | "a 2-bit rotation specifier for complex arithmetic operations") \ |
| 582e12bf | 4694 | Y(IMMEDIATE, imm_rotate1, "IMM_ROT3", 0, F(FLD_rotate3), \ |
| c2c4ff8d | 4695 | "a 1-bit rotation specifier for complex arithmetic operations") \ |
| 68a64283 YZ |
4696 | Y(COND, cond, "COND", 0, F(), "a condition") \ |
| 4697 | Y(COND, cond, "COND1", 0, F(), \ | |
| 4698 | "one of the standard conditions, excluding AL and NV.") \ | |
| a06ea964 NC |
4699 | X(ADDRESS, 0, ext_imm, "ADDR_ADRP", OPD_F_SEXT, F(FLD_immhi, FLD_immlo),\ |
| 4700 | "21-bit PC-relative address of a 4KB page") \ | |
| 4701 | Y(ADDRESS, imm, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ | |
| 4702 | F(FLD_imm14), "14-bit PC-relative address") \ | |
| 4703 | Y(ADDRESS, imm, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ | |
| 4704 | F(FLD_imm19), "19-bit PC-relative address") \ | |
| 4705 | Y(ADDRESS, imm, "ADDR_PCREL21", OPD_F_SEXT, F(FLD_immhi,FLD_immlo), \ | |
| 4706 | "21-bit PC-relative address") \ | |
| 4707 | Y(ADDRESS, imm, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ | |
| 4708 | F(FLD_imm26), "26-bit PC-relative address") \ | |
| 4709 | Y(ADDRESS, addr_simple, "ADDR_SIMPLE", 0, F(), \ | |
| 4710 | "an address with base register (no offset)") \ | |
| 4711 | Y(ADDRESS, addr_regoff, "ADDR_REGOFF", 0, F(), \ | |
| 4712 | "an address with register offset") \ | |
| 4713 | Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD_imm7,FLD_index2), \ | |
| 4714 | "an address with 7-bit signed immediate offset") \ | |
| 4715 | Y(ADDRESS, addr_simm, "ADDR_SIMM9", 0, F(FLD_imm9,FLD_index), \ | |
| 4716 | "an address with 9-bit signed immediate offset") \ | |
| 4717 | Y(ADDRESS, addr_simm, "ADDR_SIMM9_2", 0, F(FLD_imm9,FLD_index), \ | |
| 4718 | "an address with 9-bit negative or unaligned immediate offset") \ | |
| 3f06e550 SN |
4719 | Y(ADDRESS, addr_simm10, "ADDR_SIMM10", 0, F(FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index),\ |
| 4720 | "an address with 10-bit scaled, signed immediate offset") \ | |
| fb3265b3 SD |
4721 | Y(ADDRESS, addr_simm, "ADDR_SIMM11", 0, F(FLD_imm7,FLD_index2),\ |
| 4722 | "an address with 11-bit signed immediate (multiple of 16) offset")\ | |
| a06ea964 NC |
4723 | Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD_Rn,FLD_imm12), \ |
| 4724 | "an address with scaled, unsigned immediate offset") \ | |
| fb3265b3 SD |
4725 | Y(ADDRESS, addr_simm, "ADDR_SIMM13", 0, F(FLD_imm9,FLD_index),\ |
| 4726 | "an address with 13-bit signed immediate (multiple of 16) offset")\ | |
| a06ea964 NC |
4727 | Y(ADDRESS, addr_simple, "SIMD_ADDR_SIMPLE", 0, F(), \ |
| 4728 | "an address with base register (no offset)") \ | |
| f42f1a1d TC |
4729 | Y(ADDRESS, addr_offset, "ADDR_OFFSET", 0, F(FLD_Rn,FLD_imm9,FLD_index),\ |
| 4730 | "an address with an optional 8-bit signed immediate offset") \ | |
| a06ea964 NC |
4731 | Y(ADDRESS, simd_addr_post, "SIMD_ADDR_POST", 0, F(), \ |
| 4732 | "a post-indexed address with immediate or register increment") \ | |
| 4733 | Y(SYSTEM, sysreg, "SYSREG", 0, F(), "a system register") \ | |
| 4734 | Y(SYSTEM, pstatefield, "PSTATEFIELD", 0, F(), \ | |
| 4735 | "a PSTATE field name") \ | |
| 4736 | Y(SYSTEM, sysins_op, "SYSREG_AT", 0, F(), \ | |
| 4737 | "an address translation operation specifier") \ | |
| 4738 | Y(SYSTEM, sysins_op, "SYSREG_DC", 0, F(), \ | |
| 4739 | "a data cache maintenance operation specifier") \ | |
| 4740 | Y(SYSTEM, sysins_op, "SYSREG_IC", 0, F(), \ | |
| 9ed608f9 | 4741 | "an instruction cache maintenance operation specifier") \ |
| a06ea964 NC |
4742 | Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(), \ |
| 4743 | "a TBL invalidation operation specifier") \ | |
| 2ac435d4 SD |
4744 | Y(SYSTEM, sysins_op, "SYSREG_SR", 0, F(), \ |
| 4745 | "a Speculation Restriction option name (RCTX)") \ | |
| a06ea964 NC |
4746 | Y(SYSTEM, barrier, "BARRIER", 0, F(), \ |
| 4747 | "a barrier option name") \ | |
| 4748 | Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(), \ | |
| 4749 | "the ISB option name SY or an optional 4-bit unsigned immediate") \ | |
| 4750 | Y(SYSTEM, prfop, "PRFOP", 0, F(), \ | |
| 1e6f4800 | 4751 | "a prefetch operation specifier") \ |
| 4df068de | 4752 | Y(SYSTEM, hint, "BARRIER_PSB", 0, F (), \ |
| f11ad6bc | 4753 | "the PSB option name CSYNC") \ |
| ff605452 SD |
4754 | Y(SYSTEM, hint, "BTI", 0, F (), \ |
| 4755 | "BTI targets j/c/jc") \ | |
| 582e12bf RS |
4756 | Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \ |
| 4757 | 4 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
| 4758 | "an address with a 4-bit signed offset, multiplied by 16") \ | |
| 98907a70 RS |
4759 | Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4xVL", \ |
| 4760 | 0 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
| 4761 | "an address with a 4-bit signed offset, multiplied by VL") \ | |
| 4762 | Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4x2xVL", \ | |
| 4763 | 1 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
| 4764 | "an address with a 4-bit signed offset, multiplied by 2*VL") \ | |
| 4765 | Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4x3xVL", \ | |
| 4766 | 2 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
| 4767 | "an address with a 4-bit signed offset, multiplied by 3*VL") \ | |
| 4768 | Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4x4xVL", \ | |
| 4769 | 3 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
| 4770 | "an address with a 4-bit signed offset, multiplied by 4*VL") \ | |
| 4771 | Y(ADDRESS, sve_addr_ri_s6xvl, "SVE_ADDR_RI_S6xVL", \ | |
| 4772 | 0 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
| 4773 | "an address with a 6-bit signed offset, multiplied by VL") \ | |
| 4774 | Y(ADDRESS, sve_addr_ri_s9xvl, "SVE_ADDR_RI_S9xVL", \ | |
| 4775 | 0 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
| 4776 | "an address with a 9-bit signed offset, multiplied by VL") \ | |
| 4df068de RS |
4777 | Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6", 0 << OPD_F_OD_LSB, \ |
| 4778 | F(FLD_Rn), "an address with a 6-bit unsigned offset") \ | |
| 4779 | Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6x2", 1 << OPD_F_OD_LSB, \ | |
| 4780 | F(FLD_Rn), \ | |
| 4781 | "an address with a 6-bit unsigned offset, multiplied by 2") \ | |
| 4782 | Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6x4", 2 << OPD_F_OD_LSB, \ | |
| 4783 | F(FLD_Rn), \ | |
| 4784 | "an address with a 6-bit unsigned offset, multiplied by 4") \ | |
| 4785 | Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB, \ | |
| 4786 | F(FLD_Rn), \ | |
| 4787 | "an address with a 6-bit unsigned offset, multiplied by 8") \ | |
| c8d59609 NC |
4788 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_R", 0 << OPD_F_OD_LSB, \ |
| 4789 | F(FLD_Rn,FLD_Rm), "an address with an optional scalar register offset") \ | |
| 4df068de RS |
4790 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR", 0 << OPD_F_OD_LSB, \ |
| 4791 | F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ | |
| 4792 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB, \ | |
| 4793 | F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ | |
| 4794 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB, \ | |
| 4795 | F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ | |
| 4796 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB, \ | |
| 4797 | F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ | |
| 4798 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX", \ | |
| 4799 | (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ | |
| 4800 | "an address with a scalar register offset") \ | |
| 4801 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL1", \ | |
| 4802 | (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ | |
| 4803 | "an address with a scalar register offset") \ | |
| 4804 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL2", \ | |
| 4805 | (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ | |
| 4806 | "an address with a scalar register offset") \ | |
| 4807 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL3", \ | |
| 4808 | (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ | |
| 4809 | "an address with a scalar register offset") \ | |
| 4810 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ", 0 << OPD_F_OD_LSB, \ | |
| 4811 | F(FLD_Rn,FLD_SVE_Zm_16), \ | |
| 4812 | "an address with a vector register offset") \ | |
| 4813 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB, \ | |
| 4814 | F(FLD_Rn,FLD_SVE_Zm_16), \ | |
| 4815 | "an address with a vector register offset") \ | |
| 4816 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ_LSL2", 2 << OPD_F_OD_LSB, \ | |
| 4817 | F(FLD_Rn,FLD_SVE_Zm_16), \ | |
| 4818 | "an address with a vector register offset") \ | |
| 4819 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ_LSL3", 3 << OPD_F_OD_LSB, \ | |
| 4820 | F(FLD_Rn,FLD_SVE_Zm_16), \ | |
| 4821 | "an address with a vector register offset") \ | |
| 4822 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW_14", \ | |
| 4823 | 0 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14), \ | |
| 4824 | "an address with a vector register offset") \ | |
| 4825 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW_22", \ | |
| 4826 | 0 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22), \ | |
| 4827 | "an address with a vector register offset") \ | |
| 4828 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW1_14", \ | |
| 4829 | 1 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14), \ | |
| 4830 | "an address with a vector register offset") \ | |
| 4831 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW1_22", \ | |
| 4832 | 1 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22), \ | |
| 4833 | "an address with a vector register offset") \ | |
| 4834 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW2_14", \ | |
| 4835 | 2 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14), \ | |
| 4836 | "an address with a vector register offset") \ | |
| 4837 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW2_22", \ | |
| 4838 | 2 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22), \ | |
| 4839 | "an address with a vector register offset") \ | |
| 4840 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW3_14", \ | |
| 4841 | 3 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14), \ | |
| 4842 | "an address with a vector register offset") \ | |
| 4843 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW3_22", \ | |
| 4844 | 3 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22), \ | |
| 4845 | "an address with a vector register offset") \ | |
| 4846 | Y(ADDRESS, sve_addr_zi_u5, "SVE_ADDR_ZI_U5", 0 << OPD_F_OD_LSB, \ | |
| 4847 | F(FLD_SVE_Zn), "an address with a 5-bit unsigned offset") \ | |
| 4848 | Y(ADDRESS, sve_addr_zi_u5, "SVE_ADDR_ZI_U5x2", 1 << OPD_F_OD_LSB, \ | |
| 4849 | F(FLD_SVE_Zn), \ | |
| 4850 | "an address with a 5-bit unsigned offset, multiplied by 2") \ | |
| 4851 | Y(ADDRESS, sve_addr_zi_u5, "SVE_ADDR_ZI_U5x4", 2 << OPD_F_OD_LSB, \ | |
| 4852 | F(FLD_SVE_Zn), \ | |
| 4853 | "an address with a 5-bit unsigned offset, multiplied by 4") \ | |
| 4854 | Y(ADDRESS, sve_addr_zi_u5, "SVE_ADDR_ZI_U5x8", 3 << OPD_F_OD_LSB, \ | |
| 4855 | F(FLD_SVE_Zn), \ | |
| 4856 | "an address with a 5-bit unsigned offset, multiplied by 8") \ | |
| 4857 | Y(ADDRESS, sve_addr_zz_lsl, "SVE_ADDR_ZZ_LSL", 0, \ | |
| 4858 | F(FLD_SVE_Zn,FLD_SVE_Zm_16), \ | |
| 4859 | "an address with a vector register offset") \ | |
| 4860 | Y(ADDRESS, sve_addr_zz_sxtw, "SVE_ADDR_ZZ_SXTW", 0, \ | |
| 4861 | F(FLD_SVE_Zn,FLD_SVE_Zm_16), \ | |
| 4862 | "an address with a vector register offset") \ | |
| 4863 | Y(ADDRESS, sve_addr_zz_uxtw, "SVE_ADDR_ZZ_UXTW", 0, \ | |
| 4864 | F(FLD_SVE_Zn,FLD_SVE_Zm_16), \ | |
| 4865 | "an address with a vector register offset") \ | |
| e950b345 RS |
4866 | Y(IMMEDIATE, sve_aimm, "SVE_AIMM", 0, F(FLD_SVE_imm9), \ |
| 4867 | "a 9-bit unsigned arithmetic operand") \ | |
| 4868 | Y(IMMEDIATE, sve_asimm, "SVE_ASIMM", 0, F(FLD_SVE_imm9), \ | |
| 4869 | "a 9-bit signed arithmetic operand") \ | |
| 165d4950 RS |
4870 | Y(IMMEDIATE, fpimm, "SVE_FPIMM8", 0, F(FLD_SVE_imm8), \ |
| 4871 | "an 8-bit floating-point immediate") \ | |
| 4872 | Y(IMMEDIATE, sve_float_half_one, "SVE_I1_HALF_ONE", 0, \ | |
| 4873 | F(FLD_SVE_i1), "either 0.5 or 1.0") \ | |
| 4874 | Y(IMMEDIATE, sve_float_half_two, "SVE_I1_HALF_TWO", 0, \ | |
| 4875 | F(FLD_SVE_i1), "either 0.5 or 2.0") \ | |
| 4876 | Y(IMMEDIATE, sve_float_zero_one, "SVE_I1_ZERO_ONE", 0, \ | |
| 4877 | F(FLD_SVE_i1), "either 0.0 or 1.0") \ | |
| 582e12bf RS |
4878 | Y(IMMEDIATE, imm_rotate1, "SVE_IMM_ROT1", 0, F(FLD_SVE_rot1), \ |
| 4879 | "a 1-bit rotation specifier for complex arithmetic operations") \ | |
| 4880 | Y(IMMEDIATE, imm_rotate2, "SVE_IMM_ROT2", 0, F(FLD_SVE_rot2), \ | |
| 4881 | "a 2-bit rotation specifier for complex arithmetic operations") \ | |
| e950b345 RS |
4882 | Y(IMMEDIATE, inv_limm, "SVE_INV_LIMM", 0, \ |
| 4883 | F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \ | |
| 4884 | "an inverted 13-bit logical immediate") \ | |
| 4885 | Y(IMMEDIATE, limm, "SVE_LIMM", 0, \ | |
| 4886 | F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \ | |
| 4887 | "a 13-bit logical immediate") \ | |
| 4888 | Y(IMMEDIATE, sve_limm_mov, "SVE_LIMM_MOV", 0, \ | |
| 4889 | F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \ | |
| 4890 | "a 13-bit logical move immediate") \ | |
| 245d2e3f RS |
4891 | Y(IMMEDIATE, imm, "SVE_PATTERN", 0, F(FLD_SVE_pattern), \ |
| 4892 | "an enumeration value such as POW2") \ | |
| 2442d846 RS |
4893 | Y(IMMEDIATE, sve_scale, "SVE_PATTERN_SCALED", 0, \ |
| 4894 | F(FLD_SVE_pattern), "an enumeration value such as POW2") \ | |
| 245d2e3f RS |
4895 | Y(IMMEDIATE, imm, "SVE_PRFOP", 0, F(FLD_SVE_prfop), \ |
| 4896 | "an enumeration value such as PLDL1KEEP") \ | |
| f11ad6bc RS |
4897 | Y(PRED_REG, regno, "SVE_Pd", 0, F(FLD_SVE_Pd), \ |
| 4898 | "an SVE predicate register") \ | |
| 4899 | Y(PRED_REG, regno, "SVE_Pg3", 0, F(FLD_SVE_Pg3), \ | |
| 4900 | "an SVE predicate register") \ | |
| 4901 | Y(PRED_REG, regno, "SVE_Pg4_5", 0, F(FLD_SVE_Pg4_5), \ | |
| 4902 | "an SVE predicate register") \ | |
| 4903 | Y(PRED_REG, regno, "SVE_Pg4_10", 0, F(FLD_SVE_Pg4_10), \ | |
| 4904 | "an SVE predicate register") \ | |
| 4905 | Y(PRED_REG, regno, "SVE_Pg4_16", 0, F(FLD_SVE_Pg4_16), \ | |
| 4906 | "an SVE predicate register") \ | |
| 4907 | Y(PRED_REG, regno, "SVE_Pm", 0, F(FLD_SVE_Pm), \ | |
| 4908 | "an SVE predicate register") \ | |
| 4909 | Y(PRED_REG, regno, "SVE_Pn", 0, F(FLD_SVE_Pn), \ | |
| 4910 | "an SVE predicate register") \ | |
| 4911 | Y(PRED_REG, regno, "SVE_Pt", 0, F(FLD_SVE_Pt), \ | |
| 4912 | "an SVE predicate register") \ | |
| 047cd301 RS |
4913 | Y(INT_REG, regno, "SVE_Rm", 0, F(FLD_SVE_Rm), \ |
| 4914 | "an integer register or zero") \ | |
| 4915 | Y(INT_REG, regno, "SVE_Rn_SP", OPD_F_MAYBE_SP, F(FLD_SVE_Rn), \ | |
| 4916 | "an integer register or SP") \ | |
| e950b345 RS |
4917 | Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_PRED", 0, \ |
| 4918 | F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-left immediate operand") \ | |
| 4919 | Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED", 0, \ | |
| 4920 | F(FLD_SVE_tszh,FLD_imm5), "a shift-left immediate operand") \ | |
| 4921 | Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_PRED", 0, \ | |
| 4922 | F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-right immediate operand") \ | |
| 4923 | Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED", 0, \ | |
| 4924 | F(FLD_SVE_tszh,FLD_imm5), "a shift-right immediate operand") \ | |
| 4925 | Y(IMMEDIATE, imm, "SVE_SIMM5", OPD_F_SEXT, F(FLD_SVE_imm5), \ | |
| 4926 | "a 5-bit signed immediate") \ | |
| 4927 | Y(IMMEDIATE, imm, "SVE_SIMM5B", OPD_F_SEXT, F(FLD_SVE_imm5b), \ | |
| 4928 | "a 5-bit signed immediate") \ | |
| 4929 | Y(IMMEDIATE, imm, "SVE_SIMM6", OPD_F_SEXT, F(FLD_SVE_imms), \ | |
| 4930 | "a 6-bit signed immediate") \ | |
| 4931 | Y(IMMEDIATE, imm, "SVE_SIMM8", OPD_F_SEXT, F(FLD_SVE_imm8), \ | |
| 4932 | "an 8-bit signed immediate") \ | |
| 4933 | Y(IMMEDIATE, imm, "SVE_UIMM3", 0, F(FLD_SVE_imm3), \ | |
| 4934 | "a 3-bit unsigned immediate") \ | |
| 4935 | Y(IMMEDIATE, imm, "SVE_UIMM7", 0, F(FLD_SVE_imm7), \ | |
| 4936 | "a 7-bit unsigned immediate") \ | |
| 4937 | Y(IMMEDIATE, imm, "SVE_UIMM8", 0, F(FLD_SVE_imm8), \ | |
| 4938 | "an 8-bit unsigned immediate") \ | |
| 4939 | Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3), \ | |
| 4940 | "an 8-bit unsigned immediate") \ | |
| 047cd301 RS |
4941 | Y(SIMD_REG, regno, "SVE_VZn", 0, F(FLD_SVE_Zn), "a SIMD register") \ |
| 4942 | Y(SIMD_REG, regno, "SVE_Vd", 0, F(FLD_SVE_Vd), "a SIMD register") \ | |
| 4943 | Y(SIMD_REG, regno, "SVE_Vm", 0, F(FLD_SVE_Vm), "a SIMD register") \ | |
| 4944 | Y(SIMD_REG, regno, "SVE_Vn", 0, F(FLD_SVE_Vn), "a SIMD register") \ | |
| f11ad6bc RS |
4945 | Y(SVE_REG, regno, "SVE_Za_5", 0, F(FLD_SVE_Za_5), \ |
| 4946 | "an SVE vector register") \ | |
| 4947 | Y(SVE_REG, regno, "SVE_Za_16", 0, F(FLD_SVE_Za_16), \ | |
| 4948 | "an SVE vector register") \ | |
| 4949 | Y(SVE_REG, regno, "SVE_Zd", 0, F(FLD_SVE_Zd), \ | |
| 4950 | "an SVE vector register") \ | |
| 4951 | Y(SVE_REG, regno, "SVE_Zm_5", 0, F(FLD_SVE_Zm_5), \ | |
| 4952 | "an SVE vector register") \ | |
| 4953 | Y(SVE_REG, regno, "SVE_Zm_16", 0, F(FLD_SVE_Zm_16), \ | |
| 4954 | "an SVE vector register") \ | |
| 582e12bf RS |
4955 | Y(SVE_REG, sve_quad_index, "SVE_Zm3_INDEX", \ |
| 4956 | 3 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \ | |
| 4957 | "an indexed SVE vector register") \ | |
| 4958 | Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \ | |
| 4959 | 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \ | |
| 4960 | "an indexed SVE vector register") \ | |
| 4961 | Y(SVE_REG, sve_quad_index, "SVE_Zm4_INDEX", \ | |
| 4962 | 4 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \ | |
| 4963 | "an indexed SVE vector register") \ | |
| f11ad6bc RS |
4964 | Y(SVE_REG, regno, "SVE_Zn", 0, F(FLD_SVE_Zn), \ |
| 4965 | "an SVE vector register") \ | |
| 4966 | Y(SVE_REG, sve_index, "SVE_Zn_INDEX", 0, F(FLD_SVE_Zn), \ | |
| 4967 | "an indexed SVE vector register") \ | |
| 4968 | Y(SVE_REG, sve_reglist, "SVE_ZnxN", 0, F(FLD_SVE_Zn), \ | |
| 4969 | "a list of SVE vector registers") \ | |
| 4970 | Y(SVE_REG, regno, "SVE_Zt", 0, F(FLD_SVE_Zt), \ | |
| 4971 | "an SVE vector register") \ | |
| 4972 | Y(SVE_REG, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt), \ | |
| f42f1a1d | 4973 | "a list of SVE vector registers") \ |
| b83b4b13 SD |
4974 | Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \ |
| 4975 | "a 16-bit unsigned immediate for TME tcancel") \ | |
| f42f1a1d TC |
4976 | Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \ |
| 4977 | "an indexed SM3 vector immediate") |