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[opcodes, ARM, 14/16] Add mode availability to coprocessor table entries
[thirdparty/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
6394c606 25#include "disassemble.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
65b48a81 29#include "libiberty.h"
0dbde4cf 30#include "floatformat.h"
252b5132 31
baf0cc5e 32/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 33#include "coff/internal.h"
34#include "libcoff.h"
2d5d5a8f 35#include "bfd.h"
252b5132
RH		 36#include "elf-bfd.h"
37#include "elf/internal.h"
38#include "elf/arm.h"
e49d43ff 39#include "mach-o.h"
252b5132 40
6b5d3a4d 41/* FIXME: Belongs in global header. */
01c7f630 42#ifndef strneq
58efb6c0
NC		 43#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
44#endif
45
1fbaefec
PB		 46/* Cached mapping symbol state. */
47enum map_type
48{
49 MAP_ARM,
50 MAP_THUMB,
51 MAP_DATA
52};
53
b0e28b39
DJ		 54struct arm_private_data
55{
56 /* The features to use when disassembling optional instructions. */
57 arm_feature_set features;
58
1fbaefec
PB		 59 /* Track the last type (although this doesn't seem to be useful) */
60 enum map_type last_type;
61
62 /* Tracking symbol table information */
63 int last_mapping_sym;
796d6298
TC		 64
65 /* The end range of the current range being disassembled. */
66 bfd_vma last_stop_offset;
1fbaefec 67 bfd_vma last_mapping_addr;
b0e28b39
DJ		 68};
69
6b5d3a4d
ZW		 70struct opcode32
71{
823d2571
TG		 72 arm_feature_set arch; /* Architecture defining this insn. */
73 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 74 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 75 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 76};
77
6b0dd094
AV		 78enum isa {
79 ANY,
80 T32,
81 ARM
82};
83
84
85/* Shared (between Arm and Thumb mode) opcode. */
86struct sopcode32
87{
88 enum isa isa; /* Execution mode instruction availability. */
89 arm_feature_set arch; /* Architecture defining this insn. */
90 unsigned long value; /* If arch is 0 then value is a sentinel. */
91 unsigned long mask; /* Recognise insn if (op & mask) == value. */
92 const char * assembler; /* How to disassemble this insn. */
93};
94
6b5d3a4d
ZW		 95struct opcode16
96{
823d2571 97 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 98 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 99 const char *assembler; /* How to disassemble this insn. */
100};
b7693d02 101
8f06b2d8 102/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 103
2fbad815 104 %% %
4a5329c6 105
c22aaad1 106 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 107 %q print shifter argument
e2efe87d
MGD		 108 %u print condition code (unconditional in ARM mode,
109 UNPREDICTABLE if not AL in Thumb)
4a5329c6 110 %A print address for ldc/stc/ldf/stf instruction
16980d0b 111 %B print vstm/vldm register list
4a5329c6 112 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 113 %F print the COUNT field of a LFM/SFM instruction.
114 %P print floating point precision in arithmetic insn
115 %Q print floating point precision in ldf/stf insn
116 %R print floating point rounding mode
117
33399f07 118 %<bitfield>c print as a condition code (for vsel)
4a5329c6 119 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 120 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
121 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 122 %<bitfield>d print the bitfield in decimal
16980d0b 123 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 124 %<bitfield>x print the bitfield in hex
125 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 126 %<bitfield>f print a floating point constant if >7 else a
127 floating point register
4a5329c6
ZW		 128 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
129 %<bitfield>g print as an iWMMXt 64-bit register
130 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 131 %<bitfield>D print as a NEON D register
132 %<bitfield>Q print as a NEON Q register
c28eeff2 133 %<bitfield>V print as a NEON D or Q register
6f1c2142 134 %<bitfield>E print a quarter-float immediate value
4a5329c6 135
16980d0b 136 %y<code> print a single precision VFP reg.
2fbad815 137 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 138 %z<code> print a double precision VFP reg
2fbad815 139 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 140
16980d0b
JB		 141 %<bitfield>'c print specified char iff bitfield is all ones
142 %<bitfield>`c print specified char iff bitfield is all zeroes
143 %<bitfield>?ab... select from array of values in big endian order
43e65147 144
2fbad815 145 %L print as an iWMMXt N/M width field.
4a5329c6 146 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 147 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 148 versions.
149 %i print 5-bit immediate in bits 8,3..0
150 (print "32" when 0)
fe56b6ce 151 %r print register offset address for wldt/wstr instruction. */
2fbad815 152
21d799b5 153enum opcode_sentinel_enum
05413229
NC		 154{
155 SENTINEL_IWMMXT_START = 1,
156 SENTINEL_IWMMXT_END,
157 SENTINEL_GENERIC_START
158} opcode_sentinels;
159
aefd8a40 160#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 161#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
162#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 163#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 164
8f06b2d8 165/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 166
6b0dd094 167static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 168{
2fbad815 169 /* XScale instructions. */
6b0dd094 170 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 171 0x0e200010, 0x0fff0ff0,
172 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 173 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 174 0x0e280010, 0x0fff0ff0,
175 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 176 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 177 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 178 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 179 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 180 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 181 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 182
2fbad815 183 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 184 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
185 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 186 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 187 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 188 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 189 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 190 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 191 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 192 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 193 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 194 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 195 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 196 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 197 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 198 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 199 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 200 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 201 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 202 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 203 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 204 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 205 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 206 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 207 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 208 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 209 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 210 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 211 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 212 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 213 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 214 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 215 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 216 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 217 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 218 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 219 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 220 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 221 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 222 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 223 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 224 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 225 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 226 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 227 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 228 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 229 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 230 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 231 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 232 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 233 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 234 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 235 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 236 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 237 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 238 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 239 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 240 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 241 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 242 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 243 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 244 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 245 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 246 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 247 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 248 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 249 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 250 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 251 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 252 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 253 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 254 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 255 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 256 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 257 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 258 0x0e800120, 0x0f800ff0,
259 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 260 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 261 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 262 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 263 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 264 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 265 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 266 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 267 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 268 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 269 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 270 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 271 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 272 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 273 0x0e8000a0, 0x0f800ff0,
274 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 275 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 276 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 277 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 278 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 279 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 280 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 281 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 282 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 283 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 284 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 285 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 286 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 287 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 288 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 289 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 290 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 291 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 292 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 293 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 294 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 295 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 296 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 297 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 298 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 299 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 300 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 301 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 302 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 303 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 304 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 305 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 306 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 307 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 308 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 309 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 310 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 311 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 312 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 313 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 314 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 315 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 316 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 317 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 318 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 319 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 320 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 321 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 322 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 323 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 324 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 325 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 326 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 327 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 328 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 329 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 330 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 331 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 332 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 333 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 334 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 335 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 336 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 337 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 338 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 339
fe56b6ce 340 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 341 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 342 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 343 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 344 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 345 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 346 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 347 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 348 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 349 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 350 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 351 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 352 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 353 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 354 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 355 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 356 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 357 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 358 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 359 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 360 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 361 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 362 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 363 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 364 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 365 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 366 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 367 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 368 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 369 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 370 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 371 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 372 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 373 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 374 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 375 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 376 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 377 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 378 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 379 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 380 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 381 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 382 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 383 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 384 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 385 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 386 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 387 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 388 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 389 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 390 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 391 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 392 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 393 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 394 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 395 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 396 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 397 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 398 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 399 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 400 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 401 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 402 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 403 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 404 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 405 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 406 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 407 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 408 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 409 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 410 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 411 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 412 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 413 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 414 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 415 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 416 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 417 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 418 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 419 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 420 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 421 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 422 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 423 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 424 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 425 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 426 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 427
16a1fa25 428 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 429 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 430 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 431 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 432 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
433
fe56b6ce 434 /* Register load/store. */
6b0dd094 435 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 436 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 437 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 438 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 439 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 440 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 441 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 442 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 443 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 444 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 445 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 446 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 447 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 448 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 449 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 450 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 451 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 452 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 453 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 454 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 455 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 456 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 457 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 458 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 459 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 460 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 461 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 462 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 463 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 464 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 465 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571
TG		 466 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
467
6b0dd094 468 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 469 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 470 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 471 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 472 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 473 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 474 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 475 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 476
fe56b6ce 477 /* Data transfer between ARM and NEON registers. */
6b0dd094 478 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 479 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
6b0dd094 480 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 481 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
6b0dd094 482 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 483 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
6b0dd094 484 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 485 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
6b0dd094 486 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 487 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
6b0dd094 488 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 489 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
6b0dd094 490 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 491 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 492 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 493 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 494 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 495 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 496 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 497 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 498 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 499 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 500 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 501 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 502 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 503 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 504 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 505 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 506 /* Half-precision conversion instructions. */
6b0dd094 507 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 508 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 509 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 510 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 511 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 512 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 513 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 514 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 515
fe56b6ce 516 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 517 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 518 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
6b0dd094 519 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 520 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
6b0dd094 521 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 522 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 523 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 524 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 525 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 526 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 527 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 528 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 529 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 530 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 531 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 532 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
6b0dd094 533 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 534 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 535 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 536 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
6b0dd094 537 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 538 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
6b0dd094 539 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 540 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 541 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 542 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 543 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 544 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 545 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 546 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 547 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 548 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 549 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 550 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
6b0dd094 551 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 552 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 553 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 554 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 555 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 556 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 557 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 558 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 559 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 560 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 561 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 562 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 563 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 564 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 565 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 566 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 567 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 568 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 569 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 570 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 571 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 572 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 573 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 574 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 575 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 576 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 577 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 578 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 579 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 580 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 581 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 582 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 583 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 584 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 585 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 586 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 587 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 588 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 589 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 590 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 591 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 592 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 593 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 594 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 595 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 596 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 597 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 598 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 599 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 600 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 601 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 602 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 603 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 604 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 605 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 606 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 607 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 608 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 609 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 610 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 611 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 612 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 613 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 614 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 615 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 616 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 617 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 618 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 619 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 620 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 621 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 622 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 623 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 624 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 625 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 626 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 627 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 628 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 629 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 630 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 631 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 632 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 633 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 634 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 635 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 636 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 637 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 638 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 639 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 640 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 641 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 642 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 643 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 644 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 645 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 646 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 647 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 648 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 649 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 650 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 651 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 652 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 653 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 654 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 655
656 /* Cirrus coprocessor instructions. */
6b0dd094 657 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 658 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 659 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 660 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 661 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 662 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 663 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 664 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 665 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 666 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 667 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 668 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 669 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 670 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 671 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 672 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 673 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 674 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 675 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 676 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 677 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 678 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 679 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 680 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 681 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 682 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 683 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 684 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 685 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 686 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 687 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 688 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 689 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 690 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 691 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 692 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 693 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 694 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 695 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 696 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 697 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 698 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 699 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 700 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 701 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 702 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 703 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 704 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 705 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 706 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 707 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 708 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 709 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 710 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 711 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 712 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 713 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 714 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 715 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 716 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 717 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 718 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 719 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 720 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 721 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 722 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 723 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 724 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 725 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 726 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 727 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 728 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 729 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 730 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 731 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 732 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 733 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 734 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 735 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 736 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 737 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 738 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 739 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 740 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 741 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 742 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 743 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 744 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 745 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 746 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 747 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 748 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 749 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 750 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 751 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 752 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 753 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 754 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 755 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 756 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 757 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 758 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 759 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 760 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 761 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 762 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 763 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 764 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 765 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 766 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 767 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 768 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 769 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 770 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 771 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 772 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 773 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 774 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 775 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 776 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 777 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 778 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 779 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 780 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 781 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 782 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 783 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 784 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 785 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 786 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 787 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 788 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 789 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 790 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 791 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 792 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 793 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 794 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 795 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 796 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 797 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 798 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 799 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 800 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 801 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 802 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 803 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 804 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 805 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 806 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 807 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 808 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 809 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 810 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 811 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 812 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 813 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 814 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 815 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 816 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 817 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 818 0x0e000600, 0x0ff00f10,
819 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 820 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 821 0x0e100600, 0x0ff00f10,
822 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 823 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 824 0x0e200600, 0x0ff00f10,
825 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 826 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 827 0x0e300600, 0x0ff00f10,
828 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 829
62f3b8c8 830 /* VFP Fused multiply add instructions. */
6b0dd094 831 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 832 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 833 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 834 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 835 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 836 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 837 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 838 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 839 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 840 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 841 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 842 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 843 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 844 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 845 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 846 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 847
33399f07 848 /* FP v5. */
6b0dd094 849 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 850 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 851 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 852 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 853 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 854 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 855 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 856 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 857 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 858 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 859 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 860 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 861 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 862 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 863 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 864 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 865 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 866 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 867 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 868 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 869 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 870 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 871 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 872 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 873
05413229 874 /* Generic coprocessor instructions. */
6b0dd094
AV		 875 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
876 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571 877 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
6b0dd094 878 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571
TG		 879 0x0c500000, 0x0ff00000,
880 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 881 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 882 0x0e000000, 0x0f000010,
883 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 884 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 885 0x0e10f010, 0x0f10f010,
886 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 887 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 888 0x0e100010, 0x0f100010,
889 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 890 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 891 0x0e000010, 0x0f100010,
892 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 893 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 894 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 895 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 896 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 897
05413229 898 /* V6 coprocessor instructions. */
6b0dd094 899 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 900 0xfc500000, 0xfff00000,
901 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 902 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 903 0xfc400000, 0xfff00000,
904 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 905
c28eeff2 906 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 907 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 908 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 909 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 910 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 911 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 912 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 913 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 914 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 915 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 916 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 917 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 918 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 919 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 920 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 921 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 922 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 923 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 924 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 925 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 926 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 927
c604a79a 928 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 929 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 930 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 931 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a
JW		 932 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
933
dec41383 934 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 935 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 936 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 937 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 938 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 939 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 940 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 941 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 942 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 943 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 944 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 945 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 946 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 947 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 948 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 949 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 950 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
951
05413229 952 /* V5 coprocessor instructions. */
6b0dd094 953 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 954 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 955 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 956 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 957 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 958 0xfe000000, 0xff000010,
959 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 960 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 961 0xfe000010, 0xff100010,
962 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 963 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 964 0xfe100010, 0xff100010,
965 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
966
b0c11777
RL		 967 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
968 cp_num: bit <11:8> == 0b1001.
969 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 970 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 971 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 972 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 973 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 974 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 975 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 976 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 977 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 978 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 979 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 980 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 981 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 982 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 983 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 984 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 985 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 986 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 987 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 988 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 989 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 990 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 991 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 992 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 993 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 994 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 995 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 996 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 997 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 998 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 999 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1000 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1001 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1002 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1003 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1004 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1005 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1006 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1007 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1008 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1009 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1010 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1011 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1012 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1013 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1014 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1015 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1016 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1017 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1018 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1019 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1020 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1021 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1022 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1023 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1024 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1025 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1026 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1027 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1028 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1029 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1030 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1031 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1032 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1033 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1034 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1035 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1036 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1037 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1038 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1039 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1040
49e8a725 1041 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1042 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1043 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1044
6b0dd094 1045 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1046};
1047
16980d0b
JB		 1048/* Neon opcode table: This does not encode the top byte -- that is
1049 checked by the print_insn_neon routine, as it depends on whether we are
1050 doing thumb32 or arm32 disassembly. */
1051
1052/* print_insn_neon recognizes the following format control codes:
1053
1054 %% %
1055
c22aaad1 1056 %c print condition code
e2efe87d
MGD		 1057 %u print condition code (unconditional in ARM mode,
1058 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1059 %A print v{st,ld}[1234] operands
1060 %B print v{st,ld}[1234] any one operands
1061 %C print v{st,ld}[1234] single->all operands
1062 %D print scalar
1063 %E print vmov, vmvn, vorr, vbic encoded constant
1064 %F print vtbl,vtbx register list
1065
1066 %<bitfield>r print as an ARM register
1067 %<bitfield>d print the bitfield in decimal
1068 %<bitfield>e print the 2^N - bitfield in decimal
1069 %<bitfield>D print as a NEON D register
1070 %<bitfield>Q print as a NEON Q register
1071 %<bitfield>R print as a NEON D or Q register
1072 %<bitfield>Sn print byte scaled width limited by n
1073 %<bitfield>Tn print short scaled width limited by n
1074 %<bitfield>Un print long scaled width limited by n
43e65147 1075
16980d0b
JB		 1076 %<bitfield>'c print specified char iff bitfield is all ones
1077 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1078 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1079
1080static const struct opcode32 neon_opcodes[] =
1081{
fe56b6ce 1082 /* Extract. */
823d2571
TG		 1083 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1084 0xf2b00840, 0xffb00850,
1085 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1087 0xf2b00000, 0xffb00810,
1088 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1089
fe56b6ce 1090 /* Move data element to all lanes. */
823d2571
TG		 1091 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1092 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1093 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1094 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1095 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1096 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1097
fe56b6ce 1098 /* Table lookup. */
823d2571
TG		 1099 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1100 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1101 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1102 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1103
8e79c3df 1104 /* Half-precision conversions. */
823d2571
TG		 1105 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1106 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1107 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1108 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1109
1110 /* NEON fused multiply add instructions. */
823d2571 1111 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1112 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1113 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1114 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1116 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1117 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1118 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1119
fe56b6ce 1120 /* Two registers, miscellaneous. */
823d2571
TG		 1121 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1122 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1123 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1124 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1125 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1126 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1127 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1128 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1129 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1130 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1131 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1132 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1133 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1134 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1135 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1136 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1137 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1138 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1139 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1140 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1141 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1142 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1143 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1144 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1145 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1146 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1147 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1148 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1149 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1150 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1151 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1152 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1153 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1154 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1155 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1156 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1159 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1160 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1161 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164 0xf3b20300, 0xffb30fd0,
1165 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1167 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1168 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1169 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1170 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1171 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1172 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1173 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1174 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1175 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1176 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1177 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1178 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1179 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1180 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1181 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1182 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1183 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1184 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1185 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1186 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1187 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1188 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1189 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1190 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1191 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1192 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1193 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1194 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1195 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1196 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1197 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1198 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1199 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1200 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1201 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1202 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1203 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1204 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1205 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1206 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1207 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1208 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1209 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1210 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1211 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1212 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1213 0xf3bb0600, 0xffbf0e10,
823d2571 1214 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1215 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1216 0xf3b70600, 0xffbf0e10,
1217 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1218
fe56b6ce 1219 /* Three registers of the same length. */
823d2571
TG		 1220 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1221 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1222 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1223 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1224 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1225 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1226 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1227 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1228 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1229 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1230 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1231 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1232 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1233 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1234 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1235 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1236 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1237 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1238 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1239 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1240 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1241 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1242 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1243 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1244 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1245 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1246 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1247 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1248 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1249 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1250 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1251 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1252 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1253 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1254 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1255 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1256 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1257 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1258 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1259 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1260 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1261 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1262 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1263 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1265 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1266 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1267 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1268 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1269 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1270 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1271 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1272 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1273 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1274 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1275 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1276 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1277 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1278 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1279 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1280 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1281 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1282 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1283 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1284 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1285 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1286 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1287 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1288 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1289 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1290 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1291 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1292 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1293 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1294 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1295 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1296 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1297 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1299 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1300 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1301 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1302 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1303 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1304 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1305 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1306 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1307 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1308 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1309 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1310 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1311 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1312 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1313 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1314 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1315 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1316 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1317 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1318 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1319 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1320 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1321 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1323 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1324 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1325 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1327 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1328 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1329 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1331 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1337 0xf2000b00, 0xff800f10,
1338 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1339 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1340 0xf2000b10, 0xff800f10,
1341 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1343 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1348 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1349 0xf3000b00, 0xff800f10,
1350 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1351 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1352 0xf2000000, 0xfe800f10,
1353 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1354 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1355 0xf2000010, 0xfe800f10,
1356 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1357 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1358 0xf2000100, 0xfe800f10,
1359 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1361 0xf2000200, 0xfe800f10,
1362 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1363 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1364 0xf2000210, 0xfe800f10,
1365 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1366 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1367 0xf2000300, 0xfe800f10,
1368 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1369 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1370 0xf2000310, 0xfe800f10,
1371 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1372 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1373 0xf2000400, 0xfe800f10,
1374 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1375 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1376 0xf2000410, 0xfe800f10,
1377 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1378 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1379 0xf2000500, 0xfe800f10,
1380 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1382 0xf2000510, 0xfe800f10,
1383 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1384 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1385 0xf2000600, 0xfe800f10,
1386 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1387 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1388 0xf2000610, 0xfe800f10,
1389 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1391 0xf2000700, 0xfe800f10,
1392 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1393 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1394 0xf2000710, 0xfe800f10,
1395 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397 0xf2000910, 0xfe800f10,
1398 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1400 0xf2000a00, 0xfe800f10,
1401 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403 0xf2000a10, 0xfe800f10,
1404 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1405 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1406 0xf3000b10, 0xff800f10,
1407 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1409 0xf3000c10, 0xff800f10,
1410 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1411
fe56b6ce 1412 /* One register and an immediate value. */
823d2571
TG		 1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1414 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1439
fe56b6ce 1440 /* Two registers and a shift amount. */
823d2571
TG		 1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452 0xf2880950, 0xfeb80fd0,
1453 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1457 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf2900950, 0xfeb00fd0,
1476 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf2a00950, 0xfea00fd0,
1521 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1522 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1523 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1525 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1527 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1528 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1529 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1531 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1533 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1535 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1537 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1540 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1541 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1543 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1544 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1545 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1546 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1547 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1548 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1549 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1551 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1552 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1553 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1558 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1559 0xf2a00e10, 0xfea00e90,
1560 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1561 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1562 0xf2a00c10, 0xfea00e90,
1563 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1564
fe56b6ce 1565 /* Three registers of different lengths. */
823d2571
TG		 1566 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1567 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1570 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1571 0xf2800400, 0xff800f50,
1572 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1574 0xf2800600, 0xff800f50,
1575 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1576 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1577 0xf2800900, 0xff800f50,
1578 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1580 0xf2800b00, 0xff800f50,
1581 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1582 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1583 0xf2800d00, 0xff800f50,
1584 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586 0xf3800400, 0xff800f50,
1587 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1588 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1589 0xf3800600, 0xff800f50,
1590 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1592 0xf2800000, 0xfe800f50,
1593 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1594 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1595 0xf2800100, 0xfe800f50,
1596 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598 0xf2800200, 0xfe800f50,
1599 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1601 0xf2800300, 0xfe800f50,
1602 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604 0xf2800500, 0xfe800f50,
1605 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1607 0xf2800700, 0xfe800f50,
1608 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610 0xf2800800, 0xfe800f50,
1611 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613 0xf2800a00, 0xfe800f50,
1614 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1615 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1616 0xf2800c00, 0xfe800f50,
1617 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1618
fe56b6ce 1619 /* Two registers and a scalar. */
823d2571
TG		 1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1623 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1624 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1625 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1631 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1632 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1633 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1635 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1637 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1639 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1640 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1641 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1643 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1645 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1647 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1649 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1651 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1652 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1653 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1655 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1656 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1657 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1658 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1659 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1661 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1663 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1664 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1665 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1667 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1669 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1671 0xf2800240, 0xfe800f50,
1672 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674 0xf2800640, 0xfe800f50,
1675 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1677 0xf2800a40, 0xfe800f50,
1678 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1680 0xf2800e40, 0xff800f50,
1681 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1683 0xf2800f40, 0xff800f50,
1684 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1686 0xf3800e40, 0xff800f50,
1687 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1689 0xf3800f40, 0xff800f50,
1690 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1691 },
16980d0b 1692
fe56b6ce 1693 /* Element and structure load/store. */
823d2571
TG		 1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1701 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1703 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1705 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1706 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1707 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1709 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1711 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1713 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1715 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1717 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1718 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1719 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1721 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1722 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1723 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1725 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1727 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1729 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1730 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1731 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1732
1733 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1734};
1735
8f06b2d8
PB		 1736/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1737 ordered: they must be searched linearly from the top to obtain a correct
1738 match. */
1739
1740/* print_insn_arm recognizes the following format control codes:
1741
1742 %% %
1743
1744 %a print address for ldr/str instruction
1745 %s print address for ldr/str halfword/signextend instruction
c1e26897 1746 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 1747 %b print branch destination
1748 %c print condition code (always bits 28-31)
1749 %m print register mask for ldm/stm instruction
1750 %o print operand2 (immediate or register + shift)
1751 %p print 'p' iff bits 12-15 are 15
1752 %t print 't' iff bit 21 set and bit 24 clear
1753 %B print arm BLX(1) destination
1754 %C print the PSR sub type.
62b3e311
PB		 1755 %U print barrier type.
1756 %P print address for pli instruction.
8f06b2d8
PB		 1757
1758 %<bitfield>r print as an ARM register
9eb6c0f1 1759 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 1760 %<bitfield>R as %r but r15 is UNPREDICTABLE
1761 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1762 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 1763 %<bitfield>d print the bitfield in decimal
43e65147 1764 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 1765 %<bitfield>x print the bitfield in hex
1766 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 1767
16980d0b
JB		 1768 %<bitfield>'c print specified char iff bitfield is all ones
1769 %<bitfield>`c print specified char iff bitfield is all zeroes
1770 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 1771
8f06b2d8
PB		 1772 %e print arm SMI operand (bits 0..7,8..19).
1773 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 1774 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1775 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 1776
8f06b2d8
PB		 1777static const struct opcode32 arm_opcodes[] =
1778{
1779 /* ARM instructions. */
823d2571
TG		 1780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1781 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1783 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1784
1785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1786 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1788 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1790 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1792 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1794 0x00800090, 0x0fa000f0,
1795 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1797 0x00a00090, 0x0fa000f0,
1798 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1799
105bde57 1800 /* V8.2 RAS extension instructions. */
4d1464f2 1801 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 1802 0xe320f010, 0xffffffff, "esb"},
1803
53c4b28b 1804 /* V8 instructions. */
823d2571
TG		 1805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1806 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 1807 /* Defined in V8 but is in NOP space so available to all arch. */
1808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 1809 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 1810 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 1811 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1812 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 1813 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1815 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1817 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 1818 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1819 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1820 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1821 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1822 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1823 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1824 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1825 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1826 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1827 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1828 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1829 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1830 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1831 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1832 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1833 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1834 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1835 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1836 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 1837 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 1838 /* CRC32 instructions. */
823d2571
TG		 1839 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1840 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1841 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1842 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1843 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1844 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1845 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1846 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1847 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1848 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1849 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1850 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 1851
ddfded2f
MW		 1852 /* Privileged Access Never extension instructions. */
1853 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1854 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1855
90ec0d68 1856 /* Virtualization Extension instructions. */
823d2571
TG		 1857 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1858 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 1859
eea54501 1860 /* Integer Divide Extension instructions. */
823d2571
TG		 1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1862 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1864 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 1865
60e5ef9f 1866 /* MP Extension instructions. */
823d2571 1867 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 1868
c597cc3d
SD		 1869 /* Speculation Barriers. */
1870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
1871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
1872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
1873
62b3e311 1874 /* V7 instructions. */
823d2571
TG		 1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 1882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1883 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 1884
c19d1205 1885 /* ARM V6T2 instructions. */
823d2571
TG		 1886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1887 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1889 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1891 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1893 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1894
1895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1896 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1898 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1899
ff8646ee 1900 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 1901 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 1902 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 1903 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1905 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1907 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 1908
f4c65163 1909 /* ARM Security extension instructions. */
823d2571
TG		 1910 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1911 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 1912
8f06b2d8 1913 /* ARM V6K instructions. */
823d2571
TG		 1914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1915 0xf57ff01f, 0xffffffff, "clrex"},
1916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1917 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1919 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1921 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1923 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1925 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1927 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 1928
7fadb25d
SD		 1929 /* ARMv8.5-A instructions. */
1930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
1931
8f06b2d8 1932 /* ARM V6K NOP hints. */
823d2571
TG		 1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1934 0x0320f001, 0x0fffffff, "yield%c"},
1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1936 0x0320f002, 0x0fffffff, "wfe%c"},
1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1938 0x0320f003, 0x0fffffff, "wfi%c"},
1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1940 0x0320f004, 0x0fffffff, "sev%c"},
1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1942 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 1943
fe56b6ce 1944 /* ARM V6 instructions. */
823d2571
TG		 1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1956 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1958 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1960 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1962 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1964 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1966 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1968 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1970 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1972 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1974 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1976 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1978 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1980 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1982 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1984 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1986 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1988 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1990 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1992 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1994 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1996 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1998 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2000 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2002 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2004 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2006 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2008 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2010 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2012 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
2013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2014 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2016 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2018 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2020 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2022 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2024 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2026 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2028 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2030 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2032 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2034 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2036 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2038 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2040 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2042 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2044 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2046 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2048 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2050 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2052 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2054 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2056 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2058 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2060 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2062 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2064 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2066 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2068 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2070 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2072 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2074 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2076 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2078 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2080 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2082 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2084 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2086 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2088 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2090 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2092 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2094 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2096 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2098 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2100 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2102 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2104 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2106 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2108 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2110 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2112 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2114 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2116 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2118 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2120 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2122 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2124 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2126 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2128 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2130 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2132 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2134 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2136 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2138 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2140 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2142 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2144 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2146 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2148 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2150 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2152 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2154 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2156 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2158 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2160 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2162 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2164 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2166 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2168 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2170 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2172 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2174 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2176 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2178 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2180 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2182 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2184 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2186 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2188 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 2189
8f06b2d8 2190 /* V5J instruction. */
823d2571
TG		 2191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2192 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 2193
8f06b2d8 2194 /* V5 Instructions. */
823d2571
TG		 2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2196 0xe1200070, 0xfff000f0,
2197 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2199 0xfa000000, 0xfe000000, "blx\t%B"},
2200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2201 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2203 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2204
2205 /* V5E "El Segundo" Instructions. */
2206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2207 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2209 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2211 0xf450f000, 0xfc70f000, "pld\t%a"},
2212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2213 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2215 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2217 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2219 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2220
2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2222 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2224 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2225
2226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2227 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2229 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2231 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2233 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2234
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2236 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2238 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2240 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2242 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2243
2244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2245 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2247 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2248
2249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2250 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2252 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2254 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2256 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 2257
8f06b2d8 2258 /* ARM Instructions. */
823d2571
TG		 2259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2260 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2261
2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2263 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2265 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2267 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2269 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2271 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2273 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2274
2275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2276 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2278 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2280 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2282 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2283
2284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2285 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2287 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2289 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2291 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2292
2293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2294 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2296 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2298 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2299
2300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2301 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2303 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2305 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2306
2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2308 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2310 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2312 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2313
2314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2315 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2317 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2319 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2320
2321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2322 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2324 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2326 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2327
2328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2329 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2331 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2333 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2334
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2336 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2338 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2340 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2341
2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2343 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2345 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2347 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2348
2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2350 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2352 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2354 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2355
2356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2357 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2359 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2361 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2362
2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2364 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2366 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2368 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 2369
2370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2371 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2373 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2375 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2376
2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2378 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2380 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2382 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2383
2384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2385 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2387 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2389 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2390
2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2392 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2394 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2396 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2398 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2400 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2402 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2404 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2405
2406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2407 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2409 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2411 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2412
2413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2414 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2416 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2418 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2419
2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2421 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2423 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2424
2425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2426 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2427
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2429 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2431 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2432
2433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2434 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2436 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2438 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2440 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2442 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2444 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2446 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2448 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2450 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2452 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2454 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2456 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2458 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2460 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2462 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2464 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2466 0x092d0000, 0x0fff0000, "push%c\t%m"},
2467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2468 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2470 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2471
2472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2473 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2475 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2477 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2479 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2481 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2483 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2485 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2487 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2489 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2491 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2493 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2495 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2497 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2499 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2501 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2503 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2505 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2507 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2509 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2510
2511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2512 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2514 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2515
2516 /* The rest. */
4ab90a7a
AV		 2517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2518 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 2519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2520 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2521 {ARM_FEATURE_CORE_LOW (0),
2522 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2523};
2524
2525/* print_insn_thumb16 recognizes the following format control codes:
2526
2527 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2528 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2529 %<bitfield>I print bitfield as a signed decimal
2530 (top bit of range being the sign bit)
2531 %N print Thumb register mask (with LR)
2532 %O print Thumb register mask (with PC)
2533 %M print Thumb register mask
2534 %b print CZB's 6-bit unsigned branch destination
2535 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2536 %c print the condition code
2537 %C print the condition code, or "s" if not conditional
2538 %x print warning if conditional an not at end of IT block"
2539 %X print "\t; unpredictable <IT:code>" if conditional
2540 %I print IT instruction suffix and operands
4547cb56 2541 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2542 %<bitfield>r print bitfield as an ARM register
2543 %<bitfield>d print bitfield as a decimal
2544 %<bitfield>H print (bitfield * 2) as a decimal
2545 %<bitfield>W print (bitfield * 4) as a decimal
2546 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2547 %<bitfield>B print Thumb branch destination (signed displacement)
2548 %<bitfield>c print bitfield as a condition code
2549 %<bitnum>'c print specified char iff bit is one
2550 %<bitnum>?ab print a if bit is one else print b. */
2551
2552static const struct opcode16 thumb_opcodes[] =
2553{
2554 /* Thumb instructions. */
2555
16a1fa25
TP		 2556 /* ARMv8-M Security Extensions instructions. */
2557 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 2558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 2559
53c4b28b 2560 /* ARM V8 instructions. */
823d2571
TG		 2561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 2563 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 2564
8f06b2d8 2565 /* ARM V6K no-argument instructions. */
823d2571
TG		 2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2572
2573 /* ARM V6T2 instructions. */
ff8646ee
TP		 2574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2575 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2576 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2577 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 2578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2579
2580 /* ARM V6. */
823d2571
TG		 2581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2592
2593 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2595 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2596 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2598 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2599 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2601 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2602 /* Format 4. */
823d2571
TG		 2603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 2619 /* format 13 */
823d2571
TG		 2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 2622 /* format 5 */
823d2571
TG		 2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 2627 /* format 14 */
823d2571
TG		 2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 2630 /* format 2 */
823d2571
TG		 2631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2632 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2634 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2636 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2638 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 2639 /* format 8 */
823d2571
TG		 2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2641 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2643 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2645 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2646 /* format 7 */
823d2571
TG		 2647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2648 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2650 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2651 /* format 1 */
823d2571
TG		 2652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2654 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 2657 /* format 3 */
823d2571
TG		 2658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 2662 /* format 6 */
823d2571
TG		 2663 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2665 0x4800, 0xF800,
2666 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 2667 /* format 9 */
823d2571
TG		 2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2669 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2671 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2673 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2675 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 2676 /* format 10 */
823d2571
TG		 2677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2678 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2680 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 2681 /* format 11 */
823d2571
TG		 2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2683 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2685 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 2686 /* format 12 */
823d2571
TG		 2687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2688 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2690 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 2691 /* format 15 */
823d2571
TG		 2692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 2694 /* format 17 */
823d2571 2695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 2696 /* format 16 */
823d2571
TG		 2697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 2700 /* format 18 */
823d2571 2701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 2702
2703 /* The E800 .. FFFF range is unconditionally redirected to the
2704 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2705 are processed via that table. Thus, we can never encounter a
2706 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 2707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2708 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 2709};
2710
2711/* Thumb32 opcodes use the same table structure as the ARM opcodes.
2712 We adopt the convention that hw1 is the high 16 bits of .value and
2713 .mask, hw2 the low 16 bits.
2714
2715 print_insn_thumb32 recognizes the following format control codes:
2716
2717 %% %
2718
2719 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2720 %M print a modified 12-bit immediate (same location)
2721 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2722 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 2723 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 2724 %S print a possibly-shifted Rm
2725
32a94698 2726 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 2727 %a print the address of a plain load/store
2728 %w print the width and signedness of a core load/store
2729 %m print register mask for ldm/stm
4b5a202f 2730 %n print register mask for clrm
8f06b2d8
PB		 2731
2732 %E print the lsb and width fields of a bfc/bfi instruction
2733 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 2734 %G print a fallback offset for Branch Future instructions
e5d6e09e 2735 %W print an offset for BF instruction
1caf72a5 2736 %Y print an offset for BFL instruction
1889da70 2737 %Z print an offset for BFCSEL instruction
60f993ce
AV		 2738 %Q print an offset for Low Overhead Loop instructions
2739 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 2740 %b print a conditional branch offset
2741 %B print an unconditional branch offset
2742 %s print the shift field of an SSAT instruction
2743 %R print the rotation field of an SXT instruction
62b3e311
PB		 2744 %U print barrier type.
2745 %P print address for pli instruction.
c22aaad1
PB		 2746 %c print the condition code
2747 %x print warning if conditional an not at end of IT block"
2748 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 2749
2750 %<bitfield>d print bitfield in decimal
f0fba320 2751 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 2752 %<bitfield>W print bitfield*4 in decimal
2753 %<bitfield>r print bitfield as an ARM register
dd5181d5 2754 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 2755 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 2756 %<bitfield>c print bitfield as a condition code
2757
16980d0b
JB		 2758 %<bitfield>'c print specified char iff bitfield is all ones
2759 %<bitfield>`c print specified char iff bitfield is all zeroes
2760 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 2761
2762 With one exception at the bottom (done because BL and BLX(1) need
2763 to come dead last), this table was machine-sorted first in
2764 decreasing order of number of bits set in the mask, then in
2765 increasing numeric order of mask, then in increasing numeric order
2766 of opcode. This order is not the clearest for a human reader, but
2767 is guaranteed never to catch a special-case bit pattern with a more
2768 general mask, which is important, because this instruction encoding
2769 makes heavy use of special-case bit patterns. */
2770static const struct opcode32 thumb32_opcodes[] =
2771{
4b5a202f
AV		 2772 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
2773 instructions. */
60f993ce
AV		 2774 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2775 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
2776 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2777 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
2778 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2779 0xf02fc001, 0xfffff001, "le\t%P"},
2780 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2781 0xf00fc001, 0xfffff001, "le\tlr, %P"},
2782
4389b29a
AV		 2783 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2784 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 2785 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2786 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 2787 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2788 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 2789 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2790 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 2791 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2792 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 2793
4b5a202f
AV		 2794 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2795 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 2796
16a1fa25
TP		 2797 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
2798 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 2799 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2800 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2801 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2802 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 2803 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2804 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2805 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2806 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 2807
105bde57 2808 /* ARM V8.2 RAS extension instructions. */
4d1464f2 2809 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 2810 0xf3af8010, 0xffffffff, "esb"},
2811
53c4b28b 2812 /* V8 instructions. */
823d2571
TG		 2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2814 0xf3af8005, 0xffffffff, "sevl%c.w"},
2815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2816 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2818 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2820 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2822 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2824 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2826 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2828 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2830 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2832 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2834 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2836 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2838 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2840 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2842 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2844 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 2845
dd5181d5 2846 /* CRC32 instructions. */
823d2571 2847 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2848 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 2849 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2850 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 2851 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2852 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 2853 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2854 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 2855 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2856 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 2857 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2858 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 2859
c597cc3d
SD		 2860 /* Speculation Barriers. */
2861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
2863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
2864
62b3e311 2865 /* V7 instructions. */
823d2571
TG		 2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2874 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2875 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2876 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 2877
90ec0d68 2878 /* Virtualization Extension instructions. */
823d2571 2879 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 2880 /* We skip ERET as that is SUBS pc, lr, #0. */
2881
60e5ef9f 2882 /* MP Extension instructions. */
823d2571 2883 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 2884
f4c65163 2885 /* Security extension instructions. */
823d2571 2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 2887
7fadb25d
SD		 2888 /* ARMv8.5-A instructions. */
2889 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
2890
8f06b2d8 2891 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2898 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2900
ff8646ee 2901 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2902 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2904 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2906 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2908 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2910 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2912 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2914 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2916 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2918 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2920 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2922 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2924 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2926 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2928 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 2929 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2930 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 2931 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2932 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2934 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2936 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2938 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2940 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2942 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2944 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2946 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2948 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 2949 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2950 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2952 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2954 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2956 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2958 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2960 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2962 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2964 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2966 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2968 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2970 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2972 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2974 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2976 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2978 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2980 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2982 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2984 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2986 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2988 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2990 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2992 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2994 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2996 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2998 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3000 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3002 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3004 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3006 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3008 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3010 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3012 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3014 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3016 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3018 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3020 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3022 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3024 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3026 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3028 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3030 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3032 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3034 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3036 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3038 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3040 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3042 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3044 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3046 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3048 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3050 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3052 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3054 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3056 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 3057 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3058 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3060 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3062 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3064 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3066 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3068 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3070 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3072 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3074 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3076 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3078 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3080 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3082 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3084 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3086 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3088 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3090 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3092 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3094 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3096 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3098 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3100 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3102 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3104 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3106 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3108 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3110 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3112 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3114 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3116 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3118 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3120 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3122 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3124 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 3125 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3126 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3128 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3130 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3132 0xf810f000, 0xff70f000, "pld%c\t%a"},
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3134 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3136 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3138 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3140 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3142 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3144 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3146 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3148 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3150 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3152 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3154 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3156 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3158 0xfb100000, 0xfff000c0,
3159 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3161 0xfbc00080, 0xfff000c0,
3162 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3164 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3166 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3168 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 3169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3170 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3172 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3173 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3174 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3176 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3177 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3178 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3180 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3182 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3184 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3186 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3188 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3190 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3192 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3194 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3196 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3198 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 3199 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3200 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3202 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3204 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3206 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3208 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3210 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3212 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3214 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3216 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3218 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3220 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3222 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3224 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3226 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3228 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3230 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3232 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3234 0xe9400000, 0xff500000,
3235 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3237 0xe9500000, 0xff500000,
3238 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3240 0xe8600000, 0xff700000,
3241 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3243 0xe8700000, 0xff700000,
3244 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3246 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3248 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 3249
3250 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 3251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3252 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3254 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3256 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3258 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 3259
8f06b2d8 3260 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 3261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3262 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3264 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 3265
3266 /* Fallback. */
823d2571
TG		 3267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3268 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3269 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 3270};
ff4a8d2b 3271
8f06b2d8
PB		 3272static const char *const arm_conditional[] =
3273{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 3274 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 3275
3276static const char *const arm_fp_const[] =
3277{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3278
3279static const char *const arm_shift[] =
3280{"lsl", "lsr", "asr", "ror"};
3281
3282typedef struct
3283{
3284 const char *name;
3285 const char *description;
3286 const char *reg_names[16];
3287}
3288arm_regname;
3289
3290static const arm_regname regnames[] =
3291{
65b48a81 3292 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 3293 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 3294 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 3295 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3296 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 3297 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 3298 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3299 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3300 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 3301 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3302 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 3303 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 3304 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3305 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 3306};
3307
3308static const char *const iwmmxt_wwnames[] =
3309{"b", "h", "w", "d"};
3310
3311static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 3312{"b", "bus", "bc", "bss",
3313 "h", "hus", "hc", "hss",
3314 "w", "wus", "wc", "wss",
3315 "d", "dus", "dc", "dss"
8f06b2d8
PB		 3316};
3317
3318static const char *const iwmmxt_regnames[] =
3319{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3320 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3321};
3322
3323static const char *const iwmmxt_cregnames[] =
3324{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3325 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3326};
3327
3328/* Default to GCC register name set. */
3329static unsigned int regname_selected = 1;
3330
65b48a81 3331#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 3332#define arm_regnames regnames[regname_selected].reg_names
3333
3334static bfd_boolean force_thumb = FALSE;
3335
c22aaad1
PB		 3336/* Current IT instruction state. This contains the same state as the IT
3337 bits in the CPSR. */
3338static unsigned int ifthen_state;
3339/* IT state for the next instruction. */
3340static unsigned int ifthen_next_state;
3341/* The address of the insn for which the IT state is valid. */
3342static bfd_vma ifthen_address;
3343#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3344/* Indicates that the current Conditional state is unconditional or outside
3345 an IT block. */
3346#define COND_UNCOND 16
c22aaad1 3347
8f06b2d8
PB		 3348\f
3349/* Functions. */
8f06b2d8 3350
16980d0b
JB		 3351/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3352 Returns pointer to following character of the format string and
3353 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3354 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3355
3356static const char *
fe56b6ce
NC		 3357arm_decode_bitfield (const char *ptr,
3358 unsigned long insn,
3359 unsigned long *valuep,
3360 int *widthp)
16980d0b
JB		 3361{
3362 unsigned long value = 0;
3363 int width = 0;
43e65147
L		 3364
3365 do
16980d0b
JB		 3366 {
3367 int start, end;
3368 int bits;
3369
3370 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3371 start = start * 10 + *ptr - '0';
3372 if (*ptr == '-')
3373 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3374 end = end * 10 + *ptr - '0';
3375 else
3376 end = start;
3377 bits = end - start;
3378 if (bits < 0)
3379 abort ();
3380 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3381 width += bits + 1;
3382 }
3383 while (*ptr++ == ',');
3384 *valuep = value;
3385 if (widthp)
3386 *widthp = width;
3387 return ptr - 1;
3388}
3389
8f06b2d8 3390static void
37b37b2d 3391arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3392 bfd_boolean print_shift)
8f06b2d8
PB		 3393{
3394 func (stream, "%s", arm_regnames[given & 0xf]);
3395
3396 if ((given & 0xff0) != 0)
3397 {
3398 if ((given & 0x10) == 0)
3399 {
3400 int amount = (given & 0xf80) >> 7;
3401 int shift = (given & 0x60) >> 5;
3402
3403 if (amount == 0)
3404 {
3405 if (shift == 3)
3406 {
3407 func (stream, ", rrx");
3408 return;
3409 }
3410
3411 amount = 32;
3412 }
3413
37b37b2d
RE		 3414 if (print_shift)
3415 func (stream, ", %s #%d", arm_shift[shift], amount);
3416 else
3417 func (stream, ", #%d", amount);
8f06b2d8 3418 }
74bdfecf 3419 else if ((given & 0x80) == 0x80)
aefd8a40 3420 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3421 else if (print_shift)
8f06b2d8
PB		 3422 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3423 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3424 else
3425 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3426 }
3427}
3428
c1e26897
NC		 3429#define W_BIT 21
3430#define I_BIT 22
3431#define U_BIT 23
3432#define P_BIT 24
3433
3434#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3435#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3436#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3437#define PRE_BIT_SET (given & (1 << P_BIT))
3438
8f06b2d8
PB		 3439/* Print one coprocessor instruction on INFO->STREAM.
3440 Return TRUE if the instuction matched, FALSE if this is not a
3441 recognised coprocessor instruction. */
3442
3443static bfd_boolean
fe56b6ce
NC		 3444print_insn_coprocessor (bfd_vma pc,
3445 struct disassemble_info *info,
3446 long given,
8f06b2d8
PB		 3447 bfd_boolean thumb)
3448{
6b0dd094 3449 const struct sopcode32 *insn;
8f06b2d8
PB		 3450 void *stream = info->stream;
3451 fprintf_ftype func = info->fprintf_func;
3452 unsigned long mask;
2edcd244 3453 unsigned long value = 0;
c22aaad1 3454 int cond;
8afc7bea 3455 int cp_num;
823d2571
TG		 3456 struct arm_private_data *private_data = info->private_data;
3457 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3458
5b616bef 3459 allowed_arches = private_data->features;
8f06b2d8
PB		 3460
3461 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3462 {
ff4a8d2b
NC		 3463 unsigned long u_reg = 16;
3464 bfd_boolean is_unpredictable = FALSE;
05413229 3465 signed long value_in_comment = 0;
0313a2b8
NC		 3466 const char *c;
3467
823d2571 3468 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 3469 switch (insn->value)
3470 {
3471 case SENTINEL_IWMMXT_START:
3472 if (info->mach != bfd_mach_arm_XScale
3473 && info->mach != bfd_mach_arm_iWMMXt
3474 && info->mach != bfd_mach_arm_iWMMXt2)
3475 do
3476 insn++;
823d2571
TG		 3477 while ((! ARM_FEATURE_ZERO (insn->arch))
3478 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 3479 continue;
3480
3481 case SENTINEL_IWMMXT_END:
3482 continue;
3483
3484 case SENTINEL_GENERIC_START:
5b616bef 3485 allowed_arches = private_data->features;
05413229
NC		 3486 continue;
3487
3488 default:
3489 abort ();
3490 }
8f06b2d8
PB		 3491
3492 mask = insn->mask;
3493 value = insn->value;
8afc7bea
RL		 3494 cp_num = (given >> 8) & 0xf;
3495
8f06b2d8
PB		 3496 if (thumb)
3497 {
3498 /* The high 4 bits are 0xe for Arm conditional instructions, and
3499 0xe for arm unconditional instructions. The rest of the
3500 encoding is the same. */
3501 mask |= 0xf0000000;
3502 value |= 0xe0000000;
c22aaad1
PB		 3503 if (ifthen_state)
3504 cond = IFTHEN_COND;
3505 else
e2efe87d 3506 cond = COND_UNCOND;
8f06b2d8
PB		 3507 }
3508 else
3509 {
3510 /* Only match unconditional instuctions against unconditional
3511 patterns. */
3512 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 3513 {
3514 mask |= 0xf0000000;
e2efe87d 3515 cond = COND_UNCOND;
c22aaad1
PB		 3516 }
3517 else
3518 {
3519 cond = (given >> 28) & 0xf;
3520 if (cond == 0xe)
e2efe87d 3521 cond = COND_UNCOND;
c22aaad1 3522 }
8f06b2d8 3523 }
823d2571 3524
6b0dd094
AV		 3525 if ((insn->isa == T32 && !thumb)
3526 || (insn->isa == ARM && thumb))
3527 continue;
3528
0313a2b8
NC		 3529 if ((given & mask) != value)
3530 continue;
8f06b2d8 3531
823d2571 3532 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 3533 continue;
3534
8afc7bea
RL		 3535 if (insn->value == 0xfe000010 /* mcr2 */
3536 || insn->value == 0xfe100010 /* mrc2 */
3537 || insn->value == 0xfc100000 /* ldc2 */
3538 || insn->value == 0xfc000000) /* stc2 */
3539 {
b0c11777 3540 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3541 is_unpredictable = TRUE;
3542 }
3543 else if (insn->value == 0x0e000000 /* cdp */
3544 || insn->value == 0xfe000000 /* cdp2 */
3545 || insn->value == 0x0e000010 /* mcr */
3546 || insn->value == 0x0e100010 /* mrc */
3547 || insn->value == 0x0c100000 /* ldc */
3548 || insn->value == 0x0c000000) /* stc */
3549 {
3550 /* Floating-point instructions. */
b0c11777 3551 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3552 continue;
3553 }
3554
0313a2b8
NC		 3555 for (c = insn->assembler; *c; c++)
3556 {
3557 if (*c == '%')
8f06b2d8 3558 {
0313a2b8 3559 switch (*++c)
8f06b2d8 3560 {
0313a2b8
NC		 3561 case '%':
3562 func (stream, "%%");
3563 break;
3564
3565 case 'A':
05413229 3566 {
79862e45 3567 int rn = (given >> 16) & 0xf;
b0c11777 3568 bfd_vma offset = given & 0xff;
0313a2b8 3569
05413229 3570 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 3571
79862e45
DJ		 3572 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3573 {
3574 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 3575 if (cp_num == 9)
3576 /* vldr.16/vstr.16 will shift the address
3577 left by 1 bit only. */
3578 offset = offset * 2;
3579 else
3580 offset = offset * 4;
3581
79862e45
DJ		 3582 if (NEGATIVE_BIT_SET)
3583 offset = - offset;
3584 if (rn != 15)
3585 value_in_comment = offset;
3586 }
3587
c1e26897 3588 if (PRE_BIT_SET)
05413229
NC		 3589 {
3590 if (offset)
fe56b6ce 3591 func (stream, ", #%d]%s",
d908c8af 3592 (int) offset,
c1e26897 3593 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 3594 else if (NEGATIVE_BIT_SET)
3595 func (stream, ", #-0]");
05413229
NC		 3596 else
3597 func (stream, "]");
3598 }
3599 else
3600 {
0313a2b8 3601 func (stream, "]");
8f06b2d8 3602
c1e26897 3603 if (WRITEBACK_BIT_SET)
05413229
NC		 3604 {
3605 if (offset)
d908c8af 3606 func (stream, ", #%d", (int) offset);
26d97720
NS		 3607 else if (NEGATIVE_BIT_SET)
3608 func (stream, ", #-0");
05413229
NC		 3609 }
3610 else
fe56b6ce 3611 {
26d97720
NS		 3612 func (stream, ", {%s%d}",
3613 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 3614 (int) offset);
fe56b6ce
NC		 3615 value_in_comment = offset;
3616 }
05413229 3617 }
79862e45
DJ		 3618 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3619 {
3620 func (stream, "\t; ");
6844b2c2
MGD		 3621 /* For unaligned PCs, apply off-by-alignment
3622 correction. */
43e65147 3623 info->print_address_func (offset + pc
6844b2c2
MGD		 3624 + info->bytes_per_chunk * 2
3625 - (pc & 3),
dffaa15c 3626 info);
79862e45 3627 }
05413229 3628 }
0313a2b8 3629 break;
8f06b2d8 3630
0313a2b8
NC		 3631 case 'B':
3632 {
3633 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3634 int offset = (given >> 1) & 0x3f;
3635
3636 if (offset == 1)
3637 func (stream, "{d%d}", regno);
3638 else if (regno + offset > 32)
3639 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3640 else
3641 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3642 }
3643 break;
8f06b2d8 3644
e2efe87d
MGD		 3645 case 'u':
3646 if (cond != COND_UNCOND)
3647 is_unpredictable = TRUE;
3648
3649 /* Fall through. */
0313a2b8 3650 case 'c':
b0c11777
RL		 3651 if (cond != COND_UNCOND && cp_num == 9)
3652 is_unpredictable = TRUE;
3653
0313a2b8
NC		 3654 func (stream, "%s", arm_conditional[cond]);
3655 break;
8f06b2d8 3656
0313a2b8
NC		 3657 case 'I':
3658 /* Print a Cirrus/DSP shift immediate. */
3659 /* Immediates are 7bit signed ints with bits 0..3 in
3660 bits 0..3 of opcode and bits 4..6 in bits 5..7
3661 of opcode. */
3662 {
3663 int imm;
8f06b2d8 3664
0313a2b8 3665 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 3666
0313a2b8
NC		 3667 /* Is ``imm'' a negative number? */
3668 if (imm & 0x40)
24b4cf66 3669 imm -= 0x80;
8f06b2d8 3670
0313a2b8
NC		 3671 func (stream, "%d", imm);
3672 }
3673
3674 break;
8f06b2d8 3675
0313a2b8
NC		 3676 case 'F':
3677 switch (given & 0x00408000)
3678 {
3679 case 0:
3680 func (stream, "4");
3681 break;
3682 case 0x8000:
3683 func (stream, "1");
3684 break;
3685 case 0x00400000:
3686 func (stream, "2");
8f06b2d8 3687 break;
0313a2b8
NC		 3688 default:
3689 func (stream, "3");
3690 }
3691 break;
8f06b2d8 3692
0313a2b8
NC		 3693 case 'P':
3694 switch (given & 0x00080080)
3695 {
3696 case 0:
3697 func (stream, "s");
3698 break;
3699 case 0x80:
3700 func (stream, "d");
3701 break;
3702 case 0x00080000:
3703 func (stream, "e");
3704 break;
3705 default:
3706 func (stream, _("<illegal precision>"));
8f06b2d8 3707 break;
0313a2b8
NC		 3708 }
3709 break;
8f06b2d8 3710
0313a2b8
NC		 3711 case 'Q':
3712 switch (given & 0x00408000)
3713 {
3714 case 0:
3715 func (stream, "s");
8f06b2d8 3716 break;
0313a2b8
NC		 3717 case 0x8000:
3718 func (stream, "d");
8f06b2d8 3719 break;
0313a2b8
NC		 3720 case 0x00400000:
3721 func (stream, "e");
3722 break;
3723 default:
3724 func (stream, "p");
8f06b2d8 3725 break;
0313a2b8
NC		 3726 }
3727 break;
8f06b2d8 3728
0313a2b8
NC		 3729 case 'R':
3730 switch (given & 0x60)
3731 {
3732 case 0:
3733 break;
3734 case 0x20:
3735 func (stream, "p");
3736 break;
3737 case 0x40:
3738 func (stream, "m");
3739 break;
3740 default:
3741 func (stream, "z");
3742 break;
3743 }
3744 break;
16980d0b 3745
0313a2b8
NC		 3746 case '0': case '1': case '2': case '3': case '4':
3747 case '5': case '6': case '7': case '8': case '9':
3748 {
3749 int width;
8f06b2d8 3750
0313a2b8 3751 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 3752
0313a2b8
NC		 3753 switch (*c)
3754 {
ff4a8d2b
NC		 3755 case 'R':
3756 if (value == 15)
3757 is_unpredictable = TRUE;
3758 /* Fall through. */
0313a2b8 3759 case 'r':
ff4a8d2b
NC		 3760 if (c[1] == 'u')
3761 {
3762 /* Eat the 'u' character. */
3763 ++ c;
3764
3765 if (u_reg == value)
3766 is_unpredictable = TRUE;
3767 u_reg = value;
3768 }
0313a2b8
NC		 3769 func (stream, "%s", arm_regnames[value]);
3770 break;
c28eeff2
SN		 3771 case 'V':
3772 if (given & (1 << 6))
3773 goto Q;
3774 /* FALLTHROUGH */
0313a2b8
NC		 3775 case 'D':
3776 func (stream, "d%ld", value);
3777 break;
3778 case 'Q':
c28eeff2 3779 Q:
0313a2b8
NC		 3780 if (value & 1)
3781 func (stream, "<illegal reg q%ld.5>", value >> 1);
3782 else
3783 func (stream, "q%ld", value >> 1);
3784 break;
3785 case 'd':
3786 func (stream, "%ld", value);
05413229 3787 value_in_comment = value;
0313a2b8 3788 break;
6f1c2142
AM		 3789 case 'E':
3790 {
3791 /* Converts immediate 8 bit back to float value. */
3792 unsigned floatVal = (value & 0x80) << 24
3793 | (value & 0x3F) << 19
3794 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3795
3796 /* Quarter float have a maximum value of 31.0.
3797 Get floating point value multiplied by 1e7.
3798 The maximum value stays in limit of a 32-bit int. */
3799 unsigned decVal =
3800 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3801 (16 + (value & 0xF));
3802
3803 if (!(decVal % 1000000))
3804 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3805 floatVal, value & 0x80 ? '-' : ' ',
3806 decVal / 10000000,
3807 decVal % 10000000 / 1000000);
3808 else if (!(decVal % 10000))
3809 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3810 floatVal, value & 0x80 ? '-' : ' ',
3811 decVal / 10000000,
3812 decVal % 10000000 / 10000);
3813 else
3814 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3815 floatVal, value & 0x80 ? '-' : ' ',
3816 decVal / 10000000, decVal % 10000000);
3817 break;
3818 }
0313a2b8
NC		 3819 case 'k':
3820 {
3821 int from = (given & (1 << 7)) ? 32 : 16;
3822 func (stream, "%ld", from - value);
3823 }
3824 break;
8f06b2d8 3825
0313a2b8
NC		 3826 case 'f':
3827 if (value > 7)
3828 func (stream, "#%s", arm_fp_const[value & 7]);
3829 else
3830 func (stream, "f%ld", value);
3831 break;
4146fd53 3832
0313a2b8
NC		 3833 case 'w':
3834 if (width == 2)
3835 func (stream, "%s", iwmmxt_wwnames[value]);
3836 else
3837 func (stream, "%s", iwmmxt_wwssnames[value]);
3838 break;
4146fd53 3839
0313a2b8
NC		 3840 case 'g':
3841 func (stream, "%s", iwmmxt_regnames[value]);
3842 break;
3843 case 'G':
3844 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 3845 break;
8f06b2d8 3846
0313a2b8 3847 case 'x':
d1aaab3c 3848 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 3849 break;
8f06b2d8 3850
33399f07
MGD		 3851 case 'c':
3852 switch (value)
3853 {
3854 case 0:
3855 func (stream, "eq");
3856 break;
3857
3858 case 1:
3859 func (stream, "vs");
3860 break;
3861
3862 case 2:
3863 func (stream, "ge");
3864 break;
3865
3866 case 3:
3867 func (stream, "gt");
3868 break;
3869
3870 default:
3871 func (stream, "??");
3872 break;
3873 }
3874 break;
3875
0313a2b8
NC		 3876 case '`':
3877 c++;
3878 if (value == 0)
3879 func (stream, "%c", *c);
3880 break;
3881 case '\'':
3882 c++;
3883 if (value == ((1ul << width) - 1))
3884 func (stream, "%c", *c);
3885 break;
3886 case '?':
fe56b6ce 3887 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 3888 c += 1 << width;
3889 break;
3890 default:
3891 abort ();
3892 }
dffaa15c
AM		 3893 }
3894 break;
0313a2b8 3895
dffaa15c
AM		 3896 case 'y':
3897 case 'z':
3898 {
3899 int single = *c++ == 'y';
3900 int regno;
8f06b2d8 3901
dffaa15c
AM		 3902 switch (*c)
3903 {
3904 case '4': /* Sm pair */
3905 case '0': /* Sm, Dm */
3906 regno = given & 0x0000000f;
3907 if (single)
3908 {
3909 regno <<= 1;
3910 regno += (given >> 5) & 1;
3911 }
3912 else
3913 regno += ((given >> 5) & 1) << 4;
3914 break;
8f06b2d8 3915
dffaa15c
AM		 3916 case '1': /* Sd, Dd */
3917 regno = (given >> 12) & 0x0000000f;
3918 if (single)
3919 {
3920 regno <<= 1;
3921 regno += (given >> 22) & 1;
3922 }
3923 else
3924 regno += ((given >> 22) & 1) << 4;
3925 break;
7df76b80 3926
dffaa15c
AM		 3927 case '2': /* Sn, Dn */
3928 regno = (given >> 16) & 0x0000000f;
3929 if (single)
3930 {
3931 regno <<= 1;
3932 regno += (given >> 7) & 1;
3933 }
3934 else
3935 regno += ((given >> 7) & 1) << 4;
3936 break;
a7f8487e 3937
dffaa15c
AM		 3938 case '3': /* List */
3939 func (stream, "{");
3940 regno = (given >> 12) & 0x0000000f;
3941 if (single)
3942 {
3943 regno <<= 1;
3944 regno += (given >> 22) & 1;
3945 }
3946 else
3947 regno += ((given >> 22) & 1) << 4;
3948 break;
a7f8487e 3949
dffaa15c
AM		 3950 default:
3951 abort ();
3952 }
0313a2b8 3953
dffaa15c 3954 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 3955
dffaa15c
AM		 3956 if (*c == '3')
3957 {
3958 int count = given & 0xff;
b34976b6 3959
dffaa15c
AM		 3960 if (single == 0)
3961 count >>= 1;
0313a2b8 3962
dffaa15c
AM		 3963 if (--count)
3964 {
3965 func (stream, "-%c%d",
3966 single ? 's' : 'd',
3967 regno + count);
3968 }
0313a2b8 3969
dffaa15c 3970 func (stream, "}");
0313a2b8 3971 }
dffaa15c
AM		 3972 else if (*c == '4')
3973 func (stream, ", %c%d", single ? 's' : 'd',
3974 regno + 1);
3975 }
3976 break;
b34976b6 3977
dffaa15c
AM		 3978 case 'L':
3979 switch (given & 0x00400100)
0313a2b8 3980 {
dffaa15c
AM		 3981 case 0x00000000: func (stream, "b"); break;
3982 case 0x00400000: func (stream, "h"); break;
3983 case 0x00000100: func (stream, "w"); break;
3984 case 0x00400100: func (stream, "d"); break;
3985 default:
3986 break;
0313a2b8 3987 }
dffaa15c 3988 break;
2d447fca 3989
dffaa15c
AM		 3990 case 'Z':
3991 {
3992 /* given (20, 23) | given (0, 3) */
3993 value = ((given >> 16) & 0xf0) | (given & 0xf);
3994 func (stream, "%d", (int) value);
3995 }
3996 break;
0313a2b8 3997
dffaa15c
AM		 3998 case 'l':
3999 /* This is like the 'A' operator, except that if
4000 the width field "M" is zero, then the offset is
4001 *not* multiplied by four. */
4002 {
4003 int offset = given & 0xff;
4004 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 4005
dffaa15c 4006 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 4007
dffaa15c
AM		 4008 if (multiplier > 1)
4009 {
4010 value_in_comment = offset * multiplier;
4011 if (NEGATIVE_BIT_SET)
4012 value_in_comment = - value_in_comment;
4013 }
0313a2b8 4014
dffaa15c
AM		 4015 if (offset)
4016 {
4017 if (PRE_BIT_SET)
4018 func (stream, ", #%s%d]%s",
4019 NEGATIVE_BIT_SET ? "-" : "",
4020 offset * multiplier,
4021 WRITEBACK_BIT_SET ? "!" : "");
4022 else
4023 func (stream, "], #%s%d",
4024 NEGATIVE_BIT_SET ? "-" : "",
4025 offset * multiplier);
4026 }
4027 else
4028 func (stream, "]");
4029 }
4030 break;
2d447fca 4031
dffaa15c
AM		 4032 case 'r':
4033 {
4034 int imm4 = (given >> 4) & 0xf;
4035 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
4036 int ubit = ! NEGATIVE_BIT_SET;
4037 const char *rm = arm_regnames [given & 0xf];
4038 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 4039
dffaa15c
AM		 4040 switch (puw_bits)
4041 {
4042 case 1:
4043 case 3:
4044 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
4045 if (imm4)
4046 func (stream, ", lsl #%d", imm4);
4047 break;
0313a2b8 4048
dffaa15c
AM		 4049 case 4:
4050 case 5:
4051 case 6:
4052 case 7:
4053 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
4054 if (imm4 > 0)
4055 func (stream, ", lsl #%d", imm4);
4056 func (stream, "]");
4057 if (puw_bits == 5 || puw_bits == 7)
4058 func (stream, "!");
4059 break;
2d447fca 4060
dffaa15c
AM		 4061 default:
4062 func (stream, "INVALID");
4063 }
4064 }
4065 break;
0313a2b8 4066
dffaa15c
AM		 4067 case 'i':
4068 {
4069 long imm5;
4070 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
4071 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 4072 }
dffaa15c
AM		 4073 break;
4074
4075 default:
4076 abort ();
252b5132 4077 }
252b5132 4078 }
0313a2b8
NC		 4079 else
4080 func (stream, "%c", *c);
252b5132 4081 }
05413229
NC		 4082
4083 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 4084 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 4085
ff4a8d2b
NC		 4086 if (is_unpredictable)
4087 func (stream, UNPREDICTABLE_INSTRUCTION);
4088
0313a2b8 4089 return TRUE;
252b5132 4090 }
8f06b2d8 4091 return FALSE;
252b5132
RH		 4092}
4093
05413229
NC		 4094/* Decodes and prints ARM addressing modes. Returns the offset
4095 used in the address, if any, if it is worthwhile printing the
4096 offset as a hexadecimal value in a comment at the end of the
4097 line of disassembly. */
4098
4099static signed long
62b3e311
PB		 4100print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4101{
4102 void *stream = info->stream;
4103 fprintf_ftype func = info->fprintf_func;
f8b960bc 4104 bfd_vma offset = 0;
62b3e311
PB		 4105
4106 if (((given & 0x000f0000) == 0x000f0000)
4107 && ((given & 0x02000000) == 0))
4108 {
05413229 4109 offset = given & 0xfff;
62b3e311
PB		 4110
4111 func (stream, "[pc");
4112
c1e26897 4113 if (PRE_BIT_SET)
62b3e311 4114 {
26d97720
NS		 4115 /* Pre-indexed. Elide offset of positive zero when
4116 non-writeback. */
4117 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4118 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 4119
4120 if (NEGATIVE_BIT_SET)
4121 offset = -offset;
62b3e311
PB		 4122
4123 offset += pc + 8;
4124
4125 /* Cope with the possibility of write-back
4126 being used. Probably a very dangerous thing
4127 for the programmer to do, but who are we to
4128 argue ? */
26d97720 4129 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 4130 }
c1e26897 4131 else /* Post indexed. */
62b3e311 4132 {
d908c8af 4133 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 4134
c1e26897 4135 /* Ie ignore the offset. */
62b3e311
PB		 4136 offset = pc + 8;
4137 }
4138
4139 func (stream, "\t; ");
4140 info->print_address_func (offset, info);
05413229 4141 offset = 0;
62b3e311
PB		 4142 }
4143 else
4144 {
4145 func (stream, "[%s",
4146 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 4147
4148 if (PRE_BIT_SET)
62b3e311
PB		 4149 {
4150 if ((given & 0x02000000) == 0)
4151 {
26d97720 4152 /* Elide offset of positive zero when non-writeback. */
05413229 4153 offset = given & 0xfff;
26d97720 4154 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4155 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4156 }
4157 else
4158 {
26d97720 4159 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4160 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4161 }
4162
4163 func (stream, "]%s",
c1e26897 4164 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 4165 }
4166 else
4167 {
4168 if ((given & 0x02000000) == 0)
4169 {
26d97720 4170 /* Always show offset. */
05413229 4171 offset = given & 0xfff;
26d97720 4172 func (stream, "], #%s%d",
d908c8af 4173 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4174 }
4175 else
4176 {
4177 func (stream, "], %s",
c1e26897 4178 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4179 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4180 }
4181 }
84919466
MR		 4182 if (NEGATIVE_BIT_SET)
4183 offset = -offset;
62b3e311 4184 }
05413229
NC		 4185
4186 return (signed long) offset;
62b3e311
PB		 4187}
4188
16980d0b
JB		 4189/* Print one neon instruction on INFO->STREAM.
4190 Return TRUE if the instuction matched, FALSE if this is not a
4191 recognised neon instruction. */
4192
4193static bfd_boolean
4194print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4195{
4196 const struct opcode32 *insn;
4197 void *stream = info->stream;
4198 fprintf_ftype func = info->fprintf_func;
4199
4200 if (thumb)
4201 {
4202 if ((given & 0xef000000) == 0xef000000)
4203 {
0313a2b8 4204 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 4205 unsigned long bit28 = given & (1 << 28);
4206
4207 given &= 0x00ffffff;
4208 if (bit28)
4209 given |= 0xf3000000;
4210 else
4211 given |= 0xf2000000;
4212 }
4213 else if ((given & 0xff000000) == 0xf9000000)
4214 given ^= 0xf9000000 ^ 0xf4000000;
4215 else
4216 return FALSE;
4217 }
43e65147 4218
16980d0b
JB		 4219 for (insn = neon_opcodes; insn->assembler; insn++)
4220 {
4221 if ((given & insn->mask) == insn->value)
4222 {
05413229 4223 signed long value_in_comment = 0;
e2efe87d 4224 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 4225 const char *c;
4226
4227 for (c = insn->assembler; *c; c++)
4228 {
4229 if (*c == '%')
4230 {
4231 switch (*++c)
4232 {
4233 case '%':
4234 func (stream, "%%");
4235 break;
4236
e2efe87d
MGD		 4237 case 'u':
4238 if (thumb && ifthen_state)
4239 is_unpredictable = TRUE;
4240
4241 /* Fall through. */
c22aaad1
PB		 4242 case 'c':
4243 if (thumb && ifthen_state)
4244 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4245 break;
4246
16980d0b
JB		 4247 case 'A':
4248 {
43e65147 4249 static const unsigned char enc[16] =
16980d0b
JB		 4250 {
4251 0x4, 0x14, /* st4 0,1 */
4252 0x4, /* st1 2 */
4253 0x4, /* st2 3 */
4254 0x3, /* st3 4 */
4255 0x13, /* st3 5 */
4256 0x3, /* st1 6 */
4257 0x1, /* st1 7 */
4258 0x2, /* st2 8 */
4259 0x12, /* st2 9 */
4260 0x2, /* st1 10 */
4261 0, 0, 0, 0, 0
4262 };
4263 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4264 int rn = ((given >> 16) & 0xf);
4265 int rm = ((given >> 0) & 0xf);
4266 int align = ((given >> 4) & 0x3);
4267 int type = ((given >> 8) & 0xf);
4268 int n = enc[type] & 0xf;
4269 int stride = (enc[type] >> 4) + 1;
4270 int ix;
43e65147 4271
16980d0b
JB		 4272 func (stream, "{");
4273 if (stride > 1)
4274 for (ix = 0; ix != n; ix++)
4275 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4276 else if (n == 1)
4277 func (stream, "d%d", rd);
4278 else
4279 func (stream, "d%d-d%d", rd, rd + n - 1);
4280 func (stream, "}, [%s", arm_regnames[rn]);
4281 if (align)
8e560766 4282 func (stream, " :%d", 32 << align);
16980d0b
JB		 4283 func (stream, "]");
4284 if (rm == 0xd)
4285 func (stream, "!");
4286 else if (rm != 0xf)
4287 func (stream, ", %s", arm_regnames[rm]);
4288 }
4289 break;
43e65147 4290
16980d0b
JB		 4291 case 'B':
4292 {
4293 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4294 int rn = ((given >> 16) & 0xf);
4295 int rm = ((given >> 0) & 0xf);
4296 int idx_align = ((given >> 4) & 0xf);
4297 int align = 0;
4298 int size = ((given >> 10) & 0x3);
4299 int idx = idx_align >> (size + 1);
4300 int length = ((given >> 8) & 3) + 1;
4301 int stride = 1;
4302 int i;
4303
4304 if (length > 1 && size > 0)
4305 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 4306
16980d0b
JB		 4307 switch (length)
4308 {
4309 case 1:
4310 {
4311 int amask = (1 << size) - 1;
4312 if ((idx_align & (1 << size)) != 0)
4313 return FALSE;
4314 if (size > 0)
4315 {
4316 if ((idx_align & amask) == amask)
4317 align = 8 << size;
4318 else if ((idx_align & amask) != 0)
4319 return FALSE;
4320 }
4321 }
4322 break;
43e65147 4323
16980d0b
JB		 4324 case 2:
4325 if (size == 2 && (idx_align & 2) != 0)
4326 return FALSE;
4327 align = (idx_align & 1) ? 16 << size : 0;
4328 break;
43e65147 4329
16980d0b
JB		 4330 case 3:
4331 if ((size == 2 && (idx_align & 3) != 0)
4332 || (idx_align & 1) != 0)
4333 return FALSE;
4334 break;
43e65147 4335
16980d0b
JB		 4336 case 4:
4337 if (size == 2)
4338 {
4339 if ((idx_align & 3) == 3)
4340 return FALSE;
4341 align = (idx_align & 3) * 64;
4342 }
4343 else
4344 align = (idx_align & 1) ? 32 << size : 0;
4345 break;
43e65147 4346
16980d0b
JB		 4347 default:
4348 abort ();
4349 }
43e65147 4350
16980d0b
JB		 4351 func (stream, "{");
4352 for (i = 0; i < length; i++)
4353 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4354 rd + i * stride, idx);
4355 func (stream, "}, [%s", arm_regnames[rn]);
4356 if (align)
8e560766 4357 func (stream, " :%d", align);
16980d0b
JB		 4358 func (stream, "]");
4359 if (rm == 0xd)
4360 func (stream, "!");
4361 else if (rm != 0xf)
4362 func (stream, ", %s", arm_regnames[rm]);
4363 }
4364 break;
43e65147 4365
16980d0b
JB		 4366 case 'C':
4367 {
4368 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4369 int rn = ((given >> 16) & 0xf);
4370 int rm = ((given >> 0) & 0xf);
4371 int align = ((given >> 4) & 0x1);
4372 int size = ((given >> 6) & 0x3);
4373 int type = ((given >> 8) & 0x3);
4374 int n = type + 1;
4375 int stride = ((given >> 5) & 0x1);
4376 int ix;
43e65147 4377
16980d0b
JB		 4378 if (stride && (n == 1))
4379 n++;
4380 else
4381 stride++;
43e65147 4382
16980d0b
JB		 4383 func (stream, "{");
4384 if (stride > 1)
4385 for (ix = 0; ix != n; ix++)
4386 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4387 else if (n == 1)
4388 func (stream, "d%d[]", rd);
4389 else
4390 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4391 func (stream, "}, [%s", arm_regnames[rn]);
4392 if (align)
4393 {
91d6fa6a 4394 align = (8 * (type + 1)) << size;
16980d0b
JB		 4395 if (type == 3)
4396 align = (size > 1) ? align >> 1 : align;
4397 if (type == 2 || (type == 0 && !size))
8e560766 4398 func (stream, " :<bad align %d>", align);
16980d0b 4399 else
8e560766 4400 func (stream, " :%d", align);
16980d0b
JB		 4401 }
4402 func (stream, "]");
4403 if (rm == 0xd)
4404 func (stream, "!");
4405 else if (rm != 0xf)
4406 func (stream, ", %s", arm_regnames[rm]);
4407 }
4408 break;
43e65147 4409
16980d0b
JB		 4410 case 'D':
4411 {
4412 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4413 int size = (given >> 20) & 3;
4414 int reg = raw_reg & ((4 << size) - 1);
4415 int ix = raw_reg >> size >> 2;
43e65147 4416
16980d0b
JB		 4417 func (stream, "d%d[%d]", reg, ix);
4418 }
4419 break;
43e65147 4420
16980d0b 4421 case 'E':
fe56b6ce 4422 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 4423 {
4424 int bits = 0;
4425 int cmode = (given >> 8) & 0xf;
4426 int op = (given >> 5) & 0x1;
4427 unsigned long value = 0, hival = 0;
4428 unsigned shift;
4429 int size = 0;
0dbde4cf 4430 int isfloat = 0;
43e65147 4431
16980d0b
JB		 4432 bits |= ((given >> 24) & 1) << 7;
4433 bits |= ((given >> 16) & 7) << 4;
4434 bits |= ((given >> 0) & 15) << 0;
43e65147 4435
16980d0b
JB		 4436 if (cmode < 8)
4437 {
4438 shift = (cmode >> 1) & 3;
fe56b6ce 4439 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4440 size = 32;
4441 }
4442 else if (cmode < 12)
4443 {
4444 shift = (cmode >> 1) & 1;
fe56b6ce 4445 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4446 size = 16;
4447 }
4448 else if (cmode < 14)
4449 {
4450 shift = (cmode & 1) + 1;
fe56b6ce 4451 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4452 value |= (1ul << (8 * shift)) - 1;
4453 size = 32;
4454 }
4455 else if (cmode == 14)
4456 {
4457 if (op)
4458 {
fe56b6ce 4459 /* Bit replication into bytes. */
16980d0b
JB		 4460 int ix;
4461 unsigned long mask;
43e65147 4462
16980d0b
JB		 4463 value = 0;
4464 hival = 0;
4465 for (ix = 7; ix >= 0; ix--)
4466 {
4467 mask = ((bits >> ix) & 1) ? 0xff : 0;
4468 if (ix <= 3)
4469 value = (value << 8) | mask;
4470 else
4471 hival = (hival << 8) | mask;
4472 }
4473 size = 64;
4474 }
4475 else
4476 {
fe56b6ce
NC		 4477 /* Byte replication. */
4478 value = (unsigned long) bits;
16980d0b
JB		 4479 size = 8;
4480 }
4481 }
4482 else if (!op)
4483 {
fe56b6ce 4484 /* Floating point encoding. */
16980d0b 4485 int tmp;
43e65147 4486
fe56b6ce
NC		 4487 value = (unsigned long) (bits & 0x7f) << 19;
4488 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 4489 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 4490 value |= (unsigned long) tmp << 24;
16980d0b 4491 size = 32;
0dbde4cf 4492 isfloat = 1;
16980d0b
JB		 4493 }
4494 else
4495 {
4496 func (stream, "<illegal constant %.8x:%x:%x>",
4497 bits, cmode, op);
4498 size = 32;
4499 break;
4500 }
4501 switch (size)
4502 {
4503 case 8:
4504 func (stream, "#%ld\t; 0x%.2lx", value, value);
4505 break;
43e65147 4506
16980d0b
JB		 4507 case 16:
4508 func (stream, "#%ld\t; 0x%.4lx", value, value);
4509 break;
4510
4511 case 32:
0dbde4cf
JB		 4512 if (isfloat)
4513 {
4514 unsigned char valbytes[4];
4515 double fvalue;
43e65147 4516
0dbde4cf
JB		 4517 /* Do this a byte at a time so we don't have to
4518 worry about the host's endianness. */
4519 valbytes[0] = value & 0xff;
4520 valbytes[1] = (value >> 8) & 0xff;
4521 valbytes[2] = (value >> 16) & 0xff;
4522 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 4523
4524 floatformat_to_double
c1e26897
NC		 4525 (& floatformat_ieee_single_little, valbytes,
4526 & fvalue);
43e65147 4527
0dbde4cf
JB		 4528 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4529 value);
4530 }
4531 else
4e9d3b81 4532 func (stream, "#%ld\t; 0x%.8lx",
43e65147 4533 (long) (((value & 0x80000000L) != 0)
9d82ec38 4534 ? value | ~0xffffffffL : value),
c1e26897 4535 value);
16980d0b
JB		 4536 break;
4537
4538 case 64:
4539 func (stream, "#0x%.8lx%.8lx", hival, value);
4540 break;
43e65147 4541
16980d0b
JB		 4542 default:
4543 abort ();
4544 }
4545 }
4546 break;
43e65147 4547
16980d0b
JB		 4548 case 'F':
4549 {
4550 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4551 int num = (given >> 8) & 0x3;
43e65147 4552
16980d0b
JB		 4553 if (!num)
4554 func (stream, "{d%d}", regno);
4555 else if (num + regno >= 32)
4556 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4557 else
4558 func (stream, "{d%d-d%d}", regno, regno + num);
4559 }
4560 break;
7e8e6784 4561
16980d0b
JB		 4562
4563 case '0': case '1': case '2': case '3': case '4':
4564 case '5': case '6': case '7': case '8': case '9':
4565 {
4566 int width;
4567 unsigned long value;
4568
4569 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4570
16980d0b
JB		 4571 switch (*c)
4572 {
4573 case 'r':
4574 func (stream, "%s", arm_regnames[value]);
4575 break;
4576 case 'd':
4577 func (stream, "%ld", value);
05413229 4578 value_in_comment = value;
16980d0b
JB		 4579 break;
4580 case 'e':
4581 func (stream, "%ld", (1ul << width) - value);
4582 break;
43e65147 4583
16980d0b
JB		 4584 case 'S':
4585 case 'T':
4586 case 'U':
05413229 4587 /* Various width encodings. */
16980d0b
JB		 4588 {
4589 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4590 int limit;
4591 unsigned low, high;
4592
4593 c++;
4594 if (*c >= '0' && *c <= '9')
4595 limit = *c - '0';
4596 else if (*c >= 'a' && *c <= 'f')
4597 limit = *c - 'a' + 10;
4598 else
4599 abort ();
4600 low = limit >> 2;
4601 high = limit & 3;
4602
4603 if (value < low || value > high)
4604 func (stream, "<illegal width %d>", base << value);
4605 else
4606 func (stream, "%d", base << value);
4607 }
4608 break;
4609 case 'R':
4610 if (given & (1 << 6))
4611 goto Q;
4612 /* FALLTHROUGH */
4613 case 'D':
4614 func (stream, "d%ld", value);
4615 break;
4616 case 'Q':
4617 Q:
4618 if (value & 1)
4619 func (stream, "<illegal reg q%ld.5>", value >> 1);
4620 else
4621 func (stream, "q%ld", value >> 1);
4622 break;
43e65147 4623
16980d0b
JB		 4624 case '`':
4625 c++;
4626 if (value == 0)
4627 func (stream, "%c", *c);
4628 break;
4629 case '\'':
4630 c++;
4631 if (value == ((1ul << width) - 1))
4632 func (stream, "%c", *c);
4633 break;
4634 case '?':
fe56b6ce 4635 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 4636 c += 1 << width;
4637 break;
4638 default:
4639 abort ();
4640 }
16980d0b 4641 }
dffaa15c
AM		 4642 break;
4643
4644 default:
4645 abort ();
16980d0b
JB		 4646 }
4647 }
4648 else
4649 func (stream, "%c", *c);
4650 }
05413229
NC		 4651
4652 if (value_in_comment > 32 || value_in_comment < -16)
4653 func (stream, "\t; 0x%lx", value_in_comment);
4654
e2efe87d
MGD		 4655 if (is_unpredictable)
4656 func (stream, UNPREDICTABLE_INSTRUCTION);
4657
16980d0b
JB		 4658 return TRUE;
4659 }
4660 }
4661 return FALSE;
4662}
4663
90ec0d68
MGD		 4664/* Return the name of a v7A special register. */
4665
43e65147 4666static const char *
90ec0d68
MGD		 4667banked_regname (unsigned reg)
4668{
4669 switch (reg)
4670 {
4671 case 15: return "CPSR";
43e65147 4672 case 32: return "R8_usr";
90ec0d68
MGD		 4673 case 33: return "R9_usr";
4674 case 34: return "R10_usr";
4675 case 35: return "R11_usr";
4676 case 36: return "R12_usr";
4677 case 37: return "SP_usr";
4678 case 38: return "LR_usr";
43e65147 4679 case 40: return "R8_fiq";
90ec0d68
MGD		 4680 case 41: return "R9_fiq";
4681 case 42: return "R10_fiq";
4682 case 43: return "R11_fiq";
4683 case 44: return "R12_fiq";
4684 case 45: return "SP_fiq";
4685 case 46: return "LR_fiq";
4686 case 48: return "LR_irq";
4687 case 49: return "SP_irq";
4688 case 50: return "LR_svc";
4689 case 51: return "SP_svc";
4690 case 52: return "LR_abt";
4691 case 53: return "SP_abt";
4692 case 54: return "LR_und";
4693 case 55: return "SP_und";
4694 case 60: return "LR_mon";
4695 case 61: return "SP_mon";
4696 case 62: return "ELR_hyp";
4697 case 63: return "SP_hyp";
4698 case 79: return "SPSR";
4699 case 110: return "SPSR_fiq";
4700 case 112: return "SPSR_irq";
4701 case 114: return "SPSR_svc";
4702 case 116: return "SPSR_abt";
4703 case 118: return "SPSR_und";
4704 case 124: return "SPSR_mon";
4705 case 126: return "SPSR_hyp";
4706 default: return NULL;
4707 }
4708}
4709
e797f7e0
MGD		 4710/* Return the name of the DMB/DSB option. */
4711static const char *
4712data_barrier_option (unsigned option)
4713{
4714 switch (option & 0xf)
4715 {
4716 case 0xf: return "sy";
4717 case 0xe: return "st";
4718 case 0xd: return "ld";
4719 case 0xb: return "ish";
4720 case 0xa: return "ishst";
4721 case 0x9: return "ishld";
4722 case 0x7: return "un";
4723 case 0x6: return "unst";
4724 case 0x5: return "nshld";
4725 case 0x3: return "osh";
4726 case 0x2: return "oshst";
4727 case 0x1: return "oshld";
4728 default: return NULL;
4729 }
4730}
4731
4a5329c6
ZW		 4732/* Print one ARM instruction from PC on INFO->STREAM. */
4733
4734static void
4735print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4736{
6b5d3a4d 4737 const struct opcode32 *insn;
6a51a8a8 4738 void *stream = info->stream;
6b5d3a4d 4739 fprintf_ftype func = info->fprintf_func;
b0e28b39 4740 struct arm_private_data *private_data = info->private_data;
252b5132 4741
16980d0b
JB		 4742 if (print_insn_coprocessor (pc, info, given, FALSE))
4743 return;
4744
4745 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 4746 return;
4747
252b5132
RH		 4748 for (insn = arm_opcodes; insn->assembler; insn++)
4749 {
0313a2b8
NC		 4750 if ((given & insn->mask) != insn->value)
4751 continue;
823d2571
TG		 4752
4753 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 4754 continue;
4755
4756 /* Special case: an instruction with all bits set in the condition field
4757 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4758 or by the catchall at the end of the table. */
4759 if ((given & 0xF0000000) != 0xF0000000
4760 || (insn->mask & 0xF0000000) == 0xF0000000
4761 || (insn->mask == 0 && insn->value == 0))
252b5132 4762 {
ff4a8d2b
NC		 4763 unsigned long u_reg = 16;
4764 unsigned long U_reg = 16;
ab8e2090 4765 bfd_boolean is_unpredictable = FALSE;
05413229 4766 signed long value_in_comment = 0;
6b5d3a4d 4767 const char *c;
b34976b6 4768
252b5132
RH		 4769 for (c = insn->assembler; *c; c++)
4770 {
4771 if (*c == '%')
4772 {
c1e26897
NC		 4773 bfd_boolean allow_unpredictable = FALSE;
4774
252b5132
RH		 4775 switch (*++c)
4776 {
4777 case '%':
4778 func (stream, "%%");
4779 break;
4780
4781 case 'a':
05413229 4782 value_in_comment = print_arm_address (pc, info, given);
62b3e311 4783 break;
252b5132 4784
62b3e311
PB		 4785 case 'P':
4786 /* Set P address bit and use normal address
4787 printing routine. */
c1e26897 4788 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 4789 break;
4790
c1e26897
NC		 4791 case 'S':
4792 allow_unpredictable = TRUE;
1a0670f3 4793 /* Fall through. */
252b5132
RH		 4794 case 's':
4795 if ((given & 0x004f0000) == 0x004f0000)
4796 {
58efb6c0 4797 /* PC relative with immediate offset. */
f8b960bc 4798 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 4799
aefd8a40
NC		 4800 if (PRE_BIT_SET)
4801 {
26d97720
NS		 4802 /* Elide positive zero offset. */
4803 if (offset || NEGATIVE_BIT_SET)
4804 func (stream, "[pc, #%s%d]\t; ",
d908c8af 4805 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 4806 else
26d97720
NS		 4807 func (stream, "[pc]\t; ");
4808 if (NEGATIVE_BIT_SET)
4809 offset = -offset;
aefd8a40
NC		 4810 info->print_address_func (offset + pc + 8, info);
4811 }
4812 else
4813 {
26d97720
NS		 4814 /* Always show the offset. */
4815 func (stream, "[pc], #%s%d",
d908c8af 4816 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 4817 if (! allow_unpredictable)
4818 is_unpredictable = TRUE;
aefd8a40 4819 }
252b5132
RH		 4820 }
4821 else
4822 {
fe56b6ce
NC		 4823 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4824
b34976b6 4825 func (stream, "[%s",
252b5132 4826 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 4827
c1e26897 4828 if (PRE_BIT_SET)
252b5132 4829 {
c1e26897 4830 if (IMMEDIATE_BIT_SET)
252b5132 4831 {
26d97720
NS		 4832 /* Elide offset for non-writeback
4833 positive zero. */
4834 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4835 || offset)
4836 func (stream, ", #%s%d",
4837 NEGATIVE_BIT_SET ? "-" : "", offset);
4838
4839 if (NEGATIVE_BIT_SET)
4840 offset = -offset;
945ee430 4841
fe56b6ce 4842 value_in_comment = offset;
252b5132 4843 }
945ee430 4844 else
ff4a8d2b
NC		 4845 {
4846 /* Register Offset or Register Pre-Indexed. */
4847 func (stream, ", %s%s",
4848 NEGATIVE_BIT_SET ? "-" : "",
4849 arm_regnames[given & 0xf]);
4850
4851 /* Writing back to the register that is the source/
4852 destination of the load/store is unpredictable. */
4853 if (! allow_unpredictable
4854 && WRITEBACK_BIT_SET
4855 && ((given & 0xf) == ((given >> 12) & 0xf)))
4856 is_unpredictable = TRUE;
4857 }
252b5132 4858
b34976b6 4859 func (stream, "]%s",
c1e26897 4860 WRITEBACK_BIT_SET ? "!" : "");
252b5132 4861 }
945ee430 4862 else
252b5132 4863 {
c1e26897 4864 if (IMMEDIATE_BIT_SET)
252b5132 4865 {
945ee430 4866 /* Immediate Post-indexed. */
aefd8a40 4867 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 4868 func (stream, "], #%s%d",
4869 NEGATIVE_BIT_SET ? "-" : "", offset);
4870 if (NEGATIVE_BIT_SET)
4871 offset = -offset;
fe56b6ce 4872 value_in_comment = offset;
252b5132 4873 }
945ee430 4874 else
ff4a8d2b
NC		 4875 {
4876 /* Register Post-indexed. */
4877 func (stream, "], %s%s",
4878 NEGATIVE_BIT_SET ? "-" : "",
4879 arm_regnames[given & 0xf]);
4880
4881 /* Writing back to the register that is the source/
4882 destination of the load/store is unpredictable. */
4883 if (! allow_unpredictable
4884 && (given & 0xf) == ((given >> 12) & 0xf))
4885 is_unpredictable = TRUE;
4886 }
c1e26897 4887
07a28fab
NC		 4888 if (! allow_unpredictable)
4889 {
4890 /* Writeback is automatically implied by post- addressing.
4891 Setting the W bit is unnecessary and ARM specify it as
4892 being unpredictable. */
4893 if (WRITEBACK_BIT_SET
4894 /* Specifying the PC register as the post-indexed
4895 registers is also unpredictable. */
ab8e2090
NC		 4896 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4897 is_unpredictable = TRUE;
07a28fab 4898 }
252b5132
RH		 4899 }
4900 }
4901 break;
b34976b6 4902
252b5132 4903 case 'b':
6b5d3a4d 4904 {
f8b960bc 4905 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 4906 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 4907 }
252b5132
RH		 4908 break;
4909
4910 case 'c':
c22aaad1
PB		 4911 if (((given >> 28) & 0xf) != 0xe)
4912 func (stream, "%s",
4913 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 4914 break;
4915
4916 case 'm':
4917 {
4918 int started = 0;
4919 int reg;
4920
4921 func (stream, "{");
4922 for (reg = 0; reg < 16; reg++)
4923 if ((given & (1 << reg)) != 0)
4924 {
4925 if (started)
4926 func (stream, ", ");
4927 started = 1;
4928 func (stream, "%s", arm_regnames[reg]);
4929 }
4930 func (stream, "}");
ab8e2090
NC		 4931 if (! started)
4932 is_unpredictable = TRUE;
252b5132
RH		 4933 }
4934 break;
4935
37b37b2d 4936 case 'q':
78c66db8 4937 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 4938 break;
4939
252b5132
RH		 4940 case 'o':
4941 if ((given & 0x02000000) != 0)
4942 {
a415b1cd
JB		 4943 unsigned int rotate = (given & 0xf00) >> 7;
4944 unsigned int immed = (given & 0xff);
4945 unsigned int a, i;
4946
4947 a = (((immed << (32 - rotate))
4948 | (immed >> rotate)) & 0xffffffff);
4949 /* If there is another encoding with smaller rotate,
4950 the rotate should be specified directly. */
4951 for (i = 0; i < 32; i += 2)
4952 if ((a << i | a >> (32 - i)) <= 0xff)
4953 break;
4954
4955 if (i != rotate)
4956 func (stream, "#%d, %d", immed, rotate);
4957 else
4958 func (stream, "#%d", a);
4959 value_in_comment = a;
252b5132
RH		 4960 }
4961 else
78c66db8 4962 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 4963 break;
4964
4965 case 'p':
4966 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 4967 {
823d2571
TG		 4968 arm_feature_set arm_ext_v6 =
4969 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4970
aefd8a40
NC		 4971 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4972 mechanism for setting PSR flag bits. They are
4973 obsolete in V6 onwards. */
823d2571
TG		 4974 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4975 arm_ext_v6))
aefd8a40 4976 func (stream, "p");
4ab90a7a
AV		 4977 else
4978 is_unpredictable = TRUE;
aefd8a40 4979 }
252b5132
RH		 4980 break;
4981
4982 case 't':
4983 if ((given & 0x01200000) == 0x00200000)
4984 func (stream, "t");
4985 break;
4986
252b5132 4987 case 'A':
05413229
NC		 4988 {
4989 int offset = given & 0xff;
f02232aa 4990
05413229 4991 value_in_comment = offset * 4;
c1e26897 4992 if (NEGATIVE_BIT_SET)
05413229 4993 value_in_comment = - value_in_comment;
f02232aa 4994
05413229 4995 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 4996
c1e26897 4997 if (PRE_BIT_SET)
05413229
NC		 4998 {
4999 if (offset)
fe56b6ce 5000 func (stream, ", #%d]%s",
d908c8af 5001 (int) value_in_comment,
c1e26897 5002 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 5003 else
5004 func (stream, "]");
5005 }
5006 else
5007 {
5008 func (stream, "]");
f02232aa 5009
c1e26897 5010 if (WRITEBACK_BIT_SET)
05413229
NC		 5011 {
5012 if (offset)
d908c8af 5013 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 5014 }
5015 else
fe56b6ce 5016 {
d908c8af 5017 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 5018 value_in_comment = offset;
5019 }
05413229
NC		 5020 }
5021 }
252b5132
RH		 5022 break;
5023
077b8428
NC		 5024 case 'B':
5025 /* Print ARM V5 BLX(1) address: pc+25 bits. */
5026 {
5027 bfd_vma address;
5028 bfd_vma offset = 0;
b34976b6 5029
c1e26897 5030 if (! NEGATIVE_BIT_SET)
077b8428
NC		 5031 /* Is signed, hi bits should be ones. */
5032 offset = (-1) ^ 0x00ffffff;
5033
5034 /* Offset is (SignExtend(offset field)<<2). */
5035 offset += given & 0x00ffffff;
5036 offset <<= 2;
5037 address = offset + pc + 8;
b34976b6 5038
8f06b2d8
PB		 5039 if (given & 0x01000000)
5040 /* H bit allows addressing to 2-byte boundaries. */
5041 address += 2;
b1ee46c5 5042
8f06b2d8 5043 info->print_address_func (address, info);
b1ee46c5 5044 }
b1ee46c5
AH		 5045 break;
5046
252b5132 5047 case 'C':
90ec0d68
MGD		 5048 if ((given & 0x02000200) == 0x200)
5049 {
5050 const char * name;
5051 unsigned sysm = (given & 0x004f0000) >> 16;
5052
5053 sysm |= (given & 0x300) >> 4;
5054 name = banked_regname (sysm);
5055
5056 if (name != NULL)
5057 func (stream, "%s", name);
5058 else
d908c8af 5059 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 5060 }
5061 else
5062 {
43e65147 5063 func (stream, "%cPSR_",
90ec0d68
MGD		 5064 (given & 0x00400000) ? 'S' : 'C');
5065 if (given & 0x80000)
5066 func (stream, "f");
5067 if (given & 0x40000)
5068 func (stream, "s");
5069 if (given & 0x20000)
5070 func (stream, "x");
5071 if (given & 0x10000)
5072 func (stream, "c");
5073 }
252b5132
RH		 5074 break;
5075
62b3e311 5076 case 'U':
43e65147 5077 if ((given & 0xf0) == 0x60)
62b3e311 5078 {
52e7f43d
RE		 5079 switch (given & 0xf)
5080 {
5081 case 0xf: func (stream, "sy"); break;
5082 default:
5083 func (stream, "#%d", (int) given & 0xf);
5084 break;
5085 }
43e65147
L		 5086 }
5087 else
52e7f43d 5088 {
e797f7e0
MGD		 5089 const char * opt = data_barrier_option (given & 0xf);
5090 if (opt != NULL)
5091 func (stream, "%s", opt);
5092 else
52e7f43d 5093 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 5094 }
5095 break;
5096
b34976b6 5097 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 5098 case '5': case '6': case '7': case '8': case '9':
5099 {
16980d0b
JB		 5100 int width;
5101 unsigned long value;
252b5132 5102
16980d0b 5103 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 5104
252b5132
RH		 5105 switch (*c)
5106 {
ab8e2090
NC		 5107 case 'R':
5108 if (value == 15)
5109 is_unpredictable = TRUE;
5110 /* Fall through. */
16980d0b 5111 case 'r':
9eb6c0f1
MGD		 5112 case 'T':
5113 /* We want register + 1 when decoding T. */
5114 if (*c == 'T')
5115 ++value;
5116
ff4a8d2b
NC		 5117 if (c[1] == 'u')
5118 {
5119 /* Eat the 'u' character. */
5120 ++ c;
5121
5122 if (u_reg == value)
5123 is_unpredictable = TRUE;
5124 u_reg = value;
5125 }
5126 if (c[1] == 'U')
5127 {
5128 /* Eat the 'U' character. */
5129 ++ c;
5130
5131 if (U_reg == value)
5132 is_unpredictable = TRUE;
5133 U_reg = value;
5134 }
16980d0b
JB		 5135 func (stream, "%s", arm_regnames[value]);
5136 break;
5137 case 'd':
5138 func (stream, "%ld", value);
05413229 5139 value_in_comment = value;
16980d0b
JB		 5140 break;
5141 case 'b':
5142 func (stream, "%ld", value * 8);
05413229 5143 value_in_comment = value * 8;
16980d0b
JB		 5144 break;
5145 case 'W':
5146 func (stream, "%ld", value + 1);
05413229 5147 value_in_comment = value + 1;
16980d0b
JB		 5148 break;
5149 case 'x':
5150 func (stream, "0x%08lx", value);
5151
5152 /* Some SWI instructions have special
5153 meanings. */
5154 if ((given & 0x0fffffff) == 0x0FF00000)
5155 func (stream, "\t; IMB");
5156 else if ((given & 0x0fffffff) == 0x0FF00001)
5157 func (stream, "\t; IMBRange");
5158 break;
5159 case 'X':
5160 func (stream, "%01lx", value & 0xf);
05413229 5161 value_in_comment = value;
252b5132
RH		 5162 break;
5163 case '`':
5164 c++;
16980d0b 5165 if (value == 0)
252b5132
RH		 5166 func (stream, "%c", *c);
5167 break;
5168 case '\'':
5169 c++;
16980d0b 5170 if (value == ((1ul << width) - 1))
252b5132
RH		 5171 func (stream, "%c", *c);
5172 break;
5173 case '?':
fe56b6ce 5174 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 5175 c += 1 << width;
252b5132
RH		 5176 break;
5177 default:
5178 abort ();
5179 }
dffaa15c
AM		 5180 }
5181 break;
0dd132b6 5182
dffaa15c
AM		 5183 case 'e':
5184 {
5185 int imm;
0dd132b6 5186
dffaa15c
AM		 5187 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5188 func (stream, "%d", imm);
5189 value_in_comment = imm;
5190 }
5191 break;
fe56b6ce 5192
dffaa15c
AM		 5193 case 'E':
5194 /* LSB and WIDTH fields of BFI or BFC. The machine-
5195 language instruction encodes LSB and MSB. */
5196 {
5197 long msb = (given & 0x001f0000) >> 16;
5198 long lsb = (given & 0x00000f80) >> 7;
5199 long w = msb - lsb + 1;
0a003adc 5200
dffaa15c
AM		 5201 if (w > 0)
5202 func (stream, "#%lu, #%lu", lsb, w);
5203 else
5204 func (stream, "(invalid: %lu:%lu)", lsb, msb);
5205 }
5206 break;
90ec0d68 5207
dffaa15c
AM		 5208 case 'R':
5209 /* Get the PSR/banked register name. */
5210 {
5211 const char * name;
5212 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 5213
dffaa15c
AM		 5214 sysm |= (given & 0x300) >> 4;
5215 name = banked_regname (sysm);
90ec0d68 5216
dffaa15c
AM		 5217 if (name != NULL)
5218 func (stream, "%s", name);
5219 else
5220 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5221 }
5222 break;
fe56b6ce 5223
dffaa15c
AM		 5224 case 'V':
5225 /* 16-bit unsigned immediate from a MOVT or MOVW
5226 instruction, encoded in bits 0:11 and 15:19. */
5227 {
5228 long hi = (given & 0x000f0000) >> 4;
5229 long lo = (given & 0x00000fff);
5230 long imm16 = hi | lo;
0a003adc 5231
dffaa15c
AM		 5232 func (stream, "#%lu", imm16);
5233 value_in_comment = imm16;
252b5132 5234 }
dffaa15c
AM		 5235 break;
5236
5237 default:
5238 abort ();
252b5132
RH		 5239 }
5240 }
5241 else
5242 func (stream, "%c", *c);
5243 }
05413229
NC		 5244
5245 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 5246 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 5247
5248 if (is_unpredictable)
5249 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 5250
4a5329c6 5251 return;
252b5132
RH		 5252 }
5253 }
0b347048
TC		 5254 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
5255 return;
252b5132
RH		 5256}
5257
4a5329c6 5258/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 5259
4a5329c6
ZW		 5260static void
5261print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 5262{
6b5d3a4d 5263 const struct opcode16 *insn;
6a51a8a8
AM		 5264 void *stream = info->stream;
5265 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 5266
5267 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 5268 if ((given & insn->mask) == insn->value)
5269 {
05413229 5270 signed long value_in_comment = 0;
6b5d3a4d 5271 const char *c = insn->assembler;
05413229 5272
c19d1205
ZW		 5273 for (; *c; c++)
5274 {
5275 int domaskpc = 0;
5276 int domasklr = 0;
5277
5278 if (*c != '%')
5279 {
5280 func (stream, "%c", *c);
5281 continue;
5282 }
252b5132 5283
c19d1205
ZW		 5284 switch (*++c)
5285 {
5286 case '%':
5287 func (stream, "%%");
5288 break;
b34976b6 5289
c22aaad1
PB		 5290 case 'c':
5291 if (ifthen_state)
5292 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5293 break;
5294
5295 case 'C':
5296 if (ifthen_state)
5297 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5298 else
5299 func (stream, "s");
5300 break;
5301
5302 case 'I':
5303 {
5304 unsigned int tmp;
5305
5306 ifthen_next_state = given & 0xff;
5307 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5308 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5309 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5310 }
5311 break;
5312
5313 case 'x':
5314 if (ifthen_next_state)
5315 func (stream, "\t; unpredictable branch in IT block\n");
5316 break;
5317
5318 case 'X':
5319 if (ifthen_state)
5320 func (stream, "\t; unpredictable <IT:%s>",
5321 arm_conditional[IFTHEN_COND]);
5322 break;
5323
c19d1205
ZW		 5324 case 'S':
5325 {
5326 long reg;
5327
5328 reg = (given >> 3) & 0x7;
5329 if (given & (1 << 6))
5330 reg += 8;
4f3c3dbb 5331
c19d1205
ZW		 5332 func (stream, "%s", arm_regnames[reg]);
5333 }
5334 break;
baf0cc5e 5335
c19d1205 5336 case 'D':
4f3c3dbb 5337 {
c19d1205
ZW		 5338 long reg;
5339
5340 reg = given & 0x7;
5341 if (given & (1 << 7))
5342 reg += 8;
5343
5344 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 5345 }
c19d1205
ZW		 5346 break;
5347
5348 case 'N':
5349 if (given & (1 << 8))
5350 domasklr = 1;
5351 /* Fall through. */
5352 case 'O':
5353 if (*c == 'O' && (given & (1 << 8)))
5354 domaskpc = 1;
5355 /* Fall through. */
5356 case 'M':
5357 {
5358 int started = 0;
5359 int reg;
5360
5361 func (stream, "{");
5362
5363 /* It would be nice if we could spot
5364 ranges, and generate the rS-rE format: */
5365 for (reg = 0; (reg < 8); reg++)
5366 if ((given & (1 << reg)) != 0)
5367 {
5368 if (started)
5369 func (stream, ", ");
5370 started = 1;
5371 func (stream, "%s", arm_regnames[reg]);
5372 }
5373
5374 if (domasklr)
5375 {
5376 if (started)
5377 func (stream, ", ");
5378 started = 1;
d908c8af 5379 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 5380 }
5381
5382 if (domaskpc)
5383 {
5384 if (started)
5385 func (stream, ", ");
d908c8af 5386 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 5387 }
5388
5389 func (stream, "}");
5390 }
5391 break;
5392
4547cb56
NC		 5393 case 'W':
5394 /* Print writeback indicator for a LDMIA. We are doing a
5395 writeback if the base register is not in the register
5396 mask. */
5397 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5398 func (stream, "!");
dffaa15c 5399 break;
4547cb56 5400
c19d1205
ZW		 5401 case 'b':
5402 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5403 {
5404 bfd_vma address = (pc + 4
5405 + ((given & 0x00f8) >> 2)
5406 + ((given & 0x0200) >> 3));
5407 info->print_address_func (address, info);
5408 }
5409 break;
5410
5411 case 's':
5412 /* Right shift immediate -- bits 6..10; 1-31 print
5413 as themselves, 0 prints as 32. */
5414 {
5415 long imm = (given & 0x07c0) >> 6;
5416 if (imm == 0)
5417 imm = 32;
0fd3a477 5418 func (stream, "#%ld", imm);
c19d1205
ZW		 5419 }
5420 break;
5421
5422 case '0': case '1': case '2': case '3': case '4':
5423 case '5': case '6': case '7': case '8': case '9':
5424 {
5425 int bitstart = *c++ - '0';
5426 int bitend = 0;
5427
5428 while (*c >= '0' && *c <= '9')
5429 bitstart = (bitstart * 10) + *c++ - '0';
5430
5431 switch (*c)
5432 {
5433 case '-':
5434 {
f8b960bc 5435 bfd_vma reg;
c19d1205
ZW		 5436
5437 c++;
5438 while (*c >= '0' && *c <= '9')
5439 bitend = (bitend * 10) + *c++ - '0';
5440 if (!bitend)
5441 abort ();
5442 reg = given >> bitstart;
5443 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 5444
c19d1205
ZW		 5445 switch (*c)
5446 {
5447 case 'r':
5448 func (stream, "%s", arm_regnames[reg]);
5449 break;
5450
5451 case 'd':
d908c8af 5452 func (stream, "%ld", (long) reg);
05413229 5453 value_in_comment = reg;
c19d1205
ZW		 5454 break;
5455
5456 case 'H':
d908c8af 5457 func (stream, "%ld", (long) (reg << 1));
05413229 5458 value_in_comment = reg << 1;
c19d1205
ZW		 5459 break;
5460
5461 case 'W':
d908c8af 5462 func (stream, "%ld", (long) (reg << 2));
05413229 5463 value_in_comment = reg << 2;
c19d1205
ZW		 5464 break;
5465
5466 case 'a':
5467 /* PC-relative address -- the bottom two
5468 bits of the address are dropped
5469 before the calculation. */
5470 info->print_address_func
5471 (((pc + 4) & ~3) + (reg << 2), info);
05413229 5472 value_in_comment = 0;
c19d1205
ZW		 5473 break;
5474
5475 case 'x':
d908c8af 5476 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 5477 break;
5478
c19d1205
ZW		 5479 case 'B':
5480 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 5481 info->print_address_func (reg * 2 + pc + 4, info);
05413229 5482 value_in_comment = 0;
c19d1205
ZW		 5483 break;
5484
5485 case 'c':
c22aaad1 5486 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 5487 break;
5488
5489 default:
5490 abort ();
5491 }
5492 }
5493 break;
5494
5495 case '\'':
5496 c++;
5497 if ((given & (1 << bitstart)) != 0)
5498 func (stream, "%c", *c);
5499 break;
5500
5501 case '?':
5502 ++c;
5503 if ((given & (1 << bitstart)) != 0)
5504 func (stream, "%c", *c++);
5505 else
5506 func (stream, "%c", *++c);
5507 break;
5508
5509 default:
5510 abort ();
5511 }
5512 }
5513 break;
5514
5515 default:
5516 abort ();
5517 }
5518 }
05413229
NC		 5519
5520 if (value_in_comment > 32 || value_in_comment < -16)
5521 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 5522 return;
c19d1205
ZW		 5523 }
5524
5525 /* No match. */
0b347048
TC		 5526 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
5527 return;
c19d1205
ZW		 5528}
5529
62b3e311 5530/* Return the name of an V7M special register. */
fe56b6ce 5531
62b3e311
PB		 5532static const char *
5533psr_name (int regno)
5534{
5535 switch (regno)
5536 {
1a336194
TP		 5537 case 0x0: return "APSR";
5538 case 0x1: return "IAPSR";
5539 case 0x2: return "EAPSR";
5540 case 0x3: return "PSR";
5541 case 0x5: return "IPSR";
5542 case 0x6: return "EPSR";
5543 case 0x7: return "IEPSR";
5544 case 0x8: return "MSP";
5545 case 0x9: return "PSP";
5546 case 0xa: return "MSPLIM";
5547 case 0xb: return "PSPLIM";
5548 case 0x10: return "PRIMASK";
5549 case 0x11: return "BASEPRI";
5550 case 0x12: return "BASEPRI_MAX";
5551 case 0x13: return "FAULTMASK";
5552 case 0x14: return "CONTROL";
16a1fa25
TP		 5553 case 0x88: return "MSP_NS";
5554 case 0x89: return "PSP_NS";
1a336194
TP		 5555 case 0x8a: return "MSPLIM_NS";
5556 case 0x8b: return "PSPLIM_NS";
5557 case 0x90: return "PRIMASK_NS";
5558 case 0x91: return "BASEPRI_NS";
5559 case 0x93: return "FAULTMASK_NS";
5560 case 0x94: return "CONTROL_NS";
5561 case 0x98: return "SP_NS";
62b3e311
PB		 5562 default: return "<unknown>";
5563 }
5564}
5565
4a5329c6
ZW		 5566/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5567
5568static void
5569print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 5570{
6b5d3a4d 5571 const struct opcode32 *insn;
c19d1205
ZW		 5572 void *stream = info->stream;
5573 fprintf_ftype func = info->fprintf_func;
5574
16980d0b
JB		 5575 if (print_insn_coprocessor (pc, info, given, TRUE))
5576 return;
5577
5578 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 5579 return;
5580
c19d1205
ZW		 5581 for (insn = thumb32_opcodes; insn->assembler; insn++)
5582 if ((given & insn->mask) == insn->value)
5583 {
4b5a202f 5584 bfd_boolean is_clrm = FALSE;
ff4a8d2b 5585 bfd_boolean is_unpredictable = FALSE;
05413229 5586 signed long value_in_comment = 0;
6b5d3a4d 5587 const char *c = insn->assembler;
05413229 5588
c19d1205
ZW		 5589 for (; *c; c++)
5590 {
5591 if (*c != '%')
5592 {
5593 func (stream, "%c", *c);
5594 continue;
5595 }
5596
5597 switch (*++c)
5598 {
5599 case '%':
5600 func (stream, "%%");
5601 break;
5602
c22aaad1
PB		 5603 case 'c':
5604 if (ifthen_state)
5605 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5606 break;
5607
5608 case 'x':
5609 if (ifthen_next_state)
5610 func (stream, "\t; unpredictable branch in IT block\n");
5611 break;
5612
5613 case 'X':
5614 if (ifthen_state)
5615 func (stream, "\t; unpredictable <IT:%s>",
5616 arm_conditional[IFTHEN_COND]);
5617 break;
5618
c19d1205
ZW		 5619 case 'I':
5620 {
5621 unsigned int imm12 = 0;
fe56b6ce 5622
c19d1205
ZW		 5623 imm12 |= (given & 0x000000ffu);
5624 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 5625 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 5626 func (stream, "#%u", imm12);
5627 value_in_comment = imm12;
c19d1205
ZW		 5628 }
5629 break;
5630
5631 case 'M':
5632 {
5633 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 5634
c19d1205
ZW		 5635 bits |= (given & 0x000000ffu);
5636 bits |= (given & 0x00007000u) >> 4;
5637 bits |= (given & 0x04000000u) >> 15;
5638 imm8 = (bits & 0x0ff);
5639 mod = (bits & 0xf00) >> 8;
5640 switch (mod)
5641 {
5642 case 0: imm = imm8; break;
c1e26897
NC		 5643 case 1: imm = ((imm8 << 16) | imm8); break;
5644 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5645 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 5646 default:
5647 mod = (bits & 0xf80) >> 7;
5648 imm8 = (bits & 0x07f) | 0x80;
5649 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5650 }
fe56b6ce
NC		 5651 func (stream, "#%u", imm);
5652 value_in_comment = imm;
c19d1205
ZW		 5653 }
5654 break;
43e65147 5655
c19d1205
ZW		 5656 case 'J':
5657 {
5658 unsigned int imm = 0;
fe56b6ce 5659
c19d1205
ZW		 5660 imm |= (given & 0x000000ffu);
5661 imm |= (given & 0x00007000u) >> 4;
5662 imm |= (given & 0x04000000u) >> 15;
5663 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 5664 func (stream, "#%u", imm);
5665 value_in_comment = imm;
c19d1205
ZW		 5666 }
5667 break;
5668
5669 case 'K':
5670 {
5671 unsigned int imm = 0;
fe56b6ce 5672
c19d1205
ZW		 5673 imm |= (given & 0x000f0000u) >> 16;
5674 imm |= (given & 0x00000ff0u) >> 0;
5675 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 5676 func (stream, "#%u", imm);
5677 value_in_comment = imm;
c19d1205
ZW		 5678 }
5679 break;
5680
74db7efb
NC		 5681 case 'H':
5682 {
5683 unsigned int imm = 0;
5684
5685 imm |= (given & 0x000f0000u) >> 4;
5686 imm |= (given & 0x00000fffu) >> 0;
5687 func (stream, "#%u", imm);
5688 value_in_comment = imm;
5689 }
5690 break;
5691
90ec0d68
MGD		 5692 case 'V':
5693 {
5694 unsigned int imm = 0;
5695
5696 imm |= (given & 0x00000fffu);
5697 imm |= (given & 0x000f0000u) >> 4;
5698 func (stream, "#%u", imm);
5699 value_in_comment = imm;
5700 }
5701 break;
5702
c19d1205
ZW		 5703 case 'S':
5704 {
5705 unsigned int reg = (given & 0x0000000fu);
5706 unsigned int stp = (given & 0x00000030u) >> 4;
5707 unsigned int imm = 0;
5708 imm |= (given & 0x000000c0u) >> 6;
5709 imm |= (given & 0x00007000u) >> 10;
5710
5711 func (stream, "%s", arm_regnames[reg]);
5712 switch (stp)
5713 {
5714 case 0:
5715 if (imm > 0)
5716 func (stream, ", lsl #%u", imm);
5717 break;
5718
5719 case 1:
5720 if (imm == 0)
5721 imm = 32;
5722 func (stream, ", lsr #%u", imm);
5723 break;
5724
5725 case 2:
5726 if (imm == 0)
5727 imm = 32;
5728 func (stream, ", asr #%u", imm);
5729 break;
5730
5731 case 3:
5732 if (imm == 0)
5733 func (stream, ", rrx");
5734 else
5735 func (stream, ", ror #%u", imm);
5736 }
5737 }
5738 break;
5739
5740 case 'a':
5741 {
5742 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 5743 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 5744 unsigned int op = (given & 0x00000f00) >> 8;
5745 unsigned int i12 = (given & 0x00000fff);
5746 unsigned int i8 = (given & 0x000000ff);
5747 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 5748 bfd_vma offset = 0;
c19d1205
ZW		 5749
5750 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 5751 if (U) /* 12-bit positive immediate offset. */
5752 {
5753 offset = i12;
5754 if (Rn != 15)
5755 value_in_comment = offset;
5756 }
5757 else if (Rn == 15) /* 12-bit negative immediate offset. */
5758 offset = - (int) i12;
5759 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 5760 {
5761 unsigned int Rm = (i8 & 0x0f);
5762 unsigned int sh = (i8 & 0x30) >> 4;
05413229 5763
c19d1205
ZW		 5764 func (stream, ", %s", arm_regnames[Rm]);
5765 if (sh)
5766 func (stream, ", lsl #%u", sh);
5767 func (stream, "]");
5768 break;
5769 }
5770 else switch (op)
5771 {
05413229 5772 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 5773 offset = i8;
5774 break;
5775
05413229 5776 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 5777 offset = -i8;
5778 break;
5779
05413229 5780 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 5781 offset = i8;
5782 writeback = TRUE;
5783 break;
5784
05413229 5785 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 5786 offset = -i8;
5787 writeback = TRUE;
5788 break;
5789
05413229 5790 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 5791 offset = i8;
5792 postind = TRUE;
5793 break;
5794
05413229 5795 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 5796 offset = -i8;
5797 postind = TRUE;
5798 break;
5799
5800 default:
5801 func (stream, ", <undefined>]");
5802 goto skip;
5803 }
5804
5805 if (postind)
d908c8af 5806 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 5807 else
5808 {
5809 if (offset)
d908c8af 5810 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 5811 func (stream, writeback ? "]!" : "]");
5812 }
5813
5814 if (Rn == 15)
5815 {
5816 func (stream, "\t; ");
5817 info->print_address_func (((pc + 4) & ~3) + offset, info);
5818 }
5819 }
5820 skip:
5821 break;
5822
5823 case 'A':
5824 {
c1e26897
NC		 5825 unsigned int U = ! NEGATIVE_BIT_SET;
5826 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 5827 unsigned int Rn = (given & 0x000f0000) >> 16;
5828 unsigned int off = (given & 0x000000ff);
5829
5830 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 5831
5832 if (PRE_BIT_SET)
c19d1205
ZW		 5833 {
5834 if (off || !U)
05413229
NC		 5835 {
5836 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 5837 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 5838 }
c19d1205
ZW		 5839 func (stream, "]");
5840 if (W)
5841 func (stream, "!");
5842 }
5843 else
5844 {
5845 func (stream, "], ");
5846 if (W)
05413229
NC		 5847 {
5848 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 5849 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 5850 }
c19d1205 5851 else
fe56b6ce
NC		 5852 {
5853 func (stream, "{%u}", off);
5854 value_in_comment = off;
5855 }
c19d1205
ZW		 5856 }
5857 }
5858 break;
5859
5860 case 'w':
5861 {
5862 unsigned int Sbit = (given & 0x01000000) >> 24;
5863 unsigned int type = (given & 0x00600000) >> 21;
05413229 5864
c19d1205
ZW		 5865 switch (type)
5866 {
5867 case 0: func (stream, Sbit ? "sb" : "b"); break;
5868 case 1: func (stream, Sbit ? "sh" : "h"); break;
5869 case 2:
5870 if (Sbit)
5871 func (stream, "??");
5872 break;
5873 case 3:
5874 func (stream, "??");
5875 break;
5876 }
5877 }
5878 break;
5879
4b5a202f
AV		 5880 case 'n':
5881 is_clrm = TRUE;
5882 /* Fall through. */
c19d1205
ZW		 5883 case 'm':
5884 {
5885 int started = 0;
5886 int reg;
5887
5888 func (stream, "{");
5889 for (reg = 0; reg < 16; reg++)
5890 if ((given & (1 << reg)) != 0)
5891 {
5892 if (started)
5893 func (stream, ", ");
5894 started = 1;
4b5a202f
AV		 5895 if (is_clrm && reg == 13)
5896 func (stream, "(invalid: %s)", arm_regnames[reg]);
5897 else if (is_clrm && reg == 15)
5898 func (stream, "%s", "APSR");
5899 else
5900 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 5901 }
5902 func (stream, "}");
5903 }
5904 break;
5905
5906 case 'E':
5907 {
5908 unsigned int msb = (given & 0x0000001f);
5909 unsigned int lsb = 0;
fe56b6ce 5910
c19d1205
ZW		 5911 lsb |= (given & 0x000000c0u) >> 6;
5912 lsb |= (given & 0x00007000u) >> 10;
5913 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5914 }
5915 break;
5916
5917 case 'F':
5918 {
5919 unsigned int width = (given & 0x0000001f) + 1;
5920 unsigned int lsb = 0;
fe56b6ce 5921
c19d1205
ZW		 5922 lsb |= (given & 0x000000c0u) >> 6;
5923 lsb |= (given & 0x00007000u) >> 10;
5924 func (stream, "#%u, #%u", lsb, width);
5925 }
5926 break;
5927
e12437dc
AV		 5928 case 'G':
5929 {
5930 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
5931 func (stream, "%x", boff);
5932 }
5933 break;
5934
e5d6e09e
AV		 5935 case 'W':
5936 {
5937 unsigned int immA = (given & 0x001f0000u) >> 16;
5938 unsigned int immB = (given & 0x000007feu) >> 1;
5939 unsigned int immC = (given & 0x00000800u) >> 11;
5940 bfd_vma offset = 0;
5941
5942 offset |= immA << 12;
5943 offset |= immB << 2;
5944 offset |= immC << 1;
5945 /* Sign extend. */
5946 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
5947
5948 info->print_address_func (pc + 4 + offset, info);
5949 }
5950 break;
5951
1caf72a5
AV		 5952 case 'Y':
5953 {
5954 unsigned int immA = (given & 0x007f0000u) >> 16;
5955 unsigned int immB = (given & 0x000007feu) >> 1;
5956 unsigned int immC = (given & 0x00000800u) >> 11;
5957 bfd_vma offset = 0;
5958
5959 offset |= immA << 12;
5960 offset |= immB << 2;
5961 offset |= immC << 1;
5962 /* Sign extend. */
5963 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
5964
5965 info->print_address_func (pc + 4 + offset, info);
5966 }
5967 break;
5968
1889da70
AV		 5969 case 'Z':
5970 {
5971 unsigned int immA = (given & 0x00010000u) >> 16;
5972 unsigned int immB = (given & 0x000007feu) >> 1;
5973 unsigned int immC = (given & 0x00000800u) >> 11;
5974 bfd_vma offset = 0;
5975
5976 offset |= immA << 12;
5977 offset |= immB << 2;
5978 offset |= immC << 1;
5979 /* Sign extend. */
5980 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
5981
5982 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 5983
5984 unsigned int T = (given & 0x00020000u) >> 17;
5985 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
5986 unsigned int boffset = (T == 1) ? 4 : 2;
5987 func (stream, ", ");
5988 func (stream, "%x", endoffset + boffset);
1889da70
AV		 5989 }
5990 break;
5991
60f993ce
AV		 5992 case 'Q':
5993 {
5994 unsigned int immh = (given & 0x000007feu) >> 1;
5995 unsigned int imml = (given & 0x00000800u) >> 11;
5996 bfd_vma imm32 = 0;
5997
5998 imm32 |= immh << 2;
5999 imm32 |= imml << 1;
6000
6001 info->print_address_func (pc + 4 + imm32, info);
6002 }
6003 break;
6004
6005 case 'P':
6006 {
6007 unsigned int immh = (given & 0x000007feu) >> 1;
6008 unsigned int imml = (given & 0x00000800u) >> 11;
6009 bfd_vma imm32 = 0;
6010
6011 imm32 |= immh << 2;
6012 imm32 |= imml << 1;
6013
6014 info->print_address_func (pc + 4 - imm32, info);
6015 }
6016 break;
6017
c19d1205
ZW		 6018 case 'b':
6019 {
6020 unsigned int S = (given & 0x04000000u) >> 26;
6021 unsigned int J1 = (given & 0x00002000u) >> 13;
6022 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 6023 bfd_vma offset = 0;
c19d1205
ZW		 6024
6025 offset |= !S << 20;
6026 offset |= J2 << 19;
6027 offset |= J1 << 18;
6028 offset |= (given & 0x003f0000) >> 4;
6029 offset |= (given & 0x000007ff) << 1;
6030 offset -= (1 << 20);
6031
6032 info->print_address_func (pc + 4 + offset, info);
6033 }
6034 break;
6035
6036 case 'B':
6037 {
6038 unsigned int S = (given & 0x04000000u) >> 26;
6039 unsigned int I1 = (given & 0x00002000u) >> 13;
6040 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 6041 bfd_vma offset = 0;
c19d1205
ZW		 6042
6043 offset |= !S << 24;
6044 offset |= !(I1 ^ S) << 23;
6045 offset |= !(I2 ^ S) << 22;
6046 offset |= (given & 0x03ff0000u) >> 4;
6047 offset |= (given & 0x000007ffu) << 1;
6048 offset -= (1 << 24);
36b0c57d 6049 offset += pc + 4;
c19d1205 6050
36b0c57d
PB		 6051 /* BLX target addresses are always word aligned. */
6052 if ((given & 0x00001000u) == 0)
6053 offset &= ~2u;
6054
6055 info->print_address_func (offset, info);
c19d1205
ZW		 6056 }
6057 break;
6058
6059 case 's':
6060 {
6061 unsigned int shift = 0;
fe56b6ce 6062
c19d1205
ZW		 6063 shift |= (given & 0x000000c0u) >> 6;
6064 shift |= (given & 0x00007000u) >> 10;
c1e26897 6065 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 6066 func (stream, ", asr #%u", shift);
6067 else if (shift)
6068 func (stream, ", lsl #%u", shift);
6069 /* else print nothing - lsl #0 */
6070 }
6071 break;
6072
6073 case 'R':
6074 {
6075 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 6076
c19d1205
ZW		 6077 if (rot)
6078 func (stream, ", ror #%u", rot * 8);
6079 }
6080 break;
6081
62b3e311 6082 case 'U':
43e65147 6083 if ((given & 0xf0) == 0x60)
62b3e311 6084 {
52e7f43d
RE		 6085 switch (given & 0xf)
6086 {
6087 case 0xf: func (stream, "sy"); break;
6088 default:
6089 func (stream, "#%d", (int) given & 0xf);
6090 break;
6091 }
62b3e311 6092 }
43e65147 6093 else
52e7f43d 6094 {
e797f7e0
MGD		 6095 const char * opt = data_barrier_option (given & 0xf);
6096 if (opt != NULL)
6097 func (stream, "%s", opt);
6098 else
6099 func (stream, "#%d", (int) given & 0xf);
52e7f43d 6100 }
62b3e311
PB		 6101 break;
6102
6103 case 'C':
6104 if ((given & 0xff) == 0)
6105 {
6106 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
6107 if (given & 0x800)
6108 func (stream, "f");
6109 if (given & 0x400)
6110 func (stream, "s");
6111 if (given & 0x200)
6112 func (stream, "x");
6113 if (given & 0x100)
6114 func (stream, "c");
6115 }
90ec0d68
MGD		 6116 else if ((given & 0x20) == 0x20)
6117 {
6118 char const* name;
6119 unsigned sysm = (given & 0xf00) >> 8;
6120
6121 sysm |= (given & 0x30);
6122 sysm |= (given & 0x00100000) >> 14;
6123 name = banked_regname (sysm);
43e65147 6124
90ec0d68
MGD		 6125 if (name != NULL)
6126 func (stream, "%s", name);
6127 else
d908c8af 6128 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 6129 }
62b3e311
PB		 6130 else
6131 {
d908c8af 6132 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 6133 }
6134 break;
6135
6136 case 'D':
90ec0d68
MGD		 6137 if (((given & 0xff) == 0)
6138 || ((given & 0x20) == 0x20))
6139 {
6140 char const* name;
6141 unsigned sm = (given & 0xf0000) >> 16;
6142
6143 sm |= (given & 0x30);
6144 sm |= (given & 0x00100000) >> 14;
6145 name = banked_regname (sm);
6146
6147 if (name != NULL)
6148 func (stream, "%s", name);
6149 else
d908c8af 6150 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 6151 }
62b3e311 6152 else
d908c8af 6153 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 6154 break;
6155
c19d1205
ZW		 6156 case '0': case '1': case '2': case '3': case '4':
6157 case '5': case '6': case '7': case '8': case '9':
6158 {
16980d0b
JB		 6159 int width;
6160 unsigned long val;
c19d1205 6161
16980d0b 6162 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 6163
c19d1205
ZW		 6164 switch (*c)
6165 {
05413229
NC		 6166 case 'd':
6167 func (stream, "%lu", val);
6168 value_in_comment = val;
6169 break;
ff4a8d2b 6170
f0fba320
RL		 6171 case 'D':
6172 func (stream, "%lu", val + 1);
6173 value_in_comment = val + 1;
6174 break;
6175
05413229
NC		 6176 case 'W':
6177 func (stream, "%lu", val * 4);
6178 value_in_comment = val * 4;
6179 break;
ff4a8d2b 6180
f1c7f421
AV		 6181 case 'S':
6182 if (val == 13)
6183 is_unpredictable = TRUE;
6184 /* Fall through. */
ff4a8d2b
NC		 6185 case 'R':
6186 if (val == 15)
6187 is_unpredictable = TRUE;
6188 /* Fall through. */
6189 case 'r':
6190 func (stream, "%s", arm_regnames[val]);
6191 break;
c19d1205
ZW		 6192
6193 case 'c':
c22aaad1 6194 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 6195 break;
6196
6197 case '\'':
c19d1205 6198 c++;
16980d0b
JB		 6199 if (val == ((1ul << width) - 1))
6200 func (stream, "%c", *c);
c19d1205 6201 break;
43e65147 6202
c19d1205 6203 case '`':
c19d1205 6204 c++;
16980d0b
JB		 6205 if (val == 0)
6206 func (stream, "%c", *c);
c19d1205
ZW		 6207 break;
6208
6209 case '?':
fe56b6ce 6210 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 6211 c += 1 << width;
c19d1205 6212 break;
43e65147 6213
0bb027fd
RR		 6214 case 'x':
6215 func (stream, "0x%lx", val & 0xffffffffUL);
6216 break;
c19d1205
ZW		 6217
6218 default:
6219 abort ();
6220 }
6221 }
6222 break;
6223
32a94698
NC		 6224 case 'L':
6225 /* PR binutils/12534
6226 If we have a PC relative offset in an LDRD or STRD
6227 instructions then display the decoded address. */
6228 if (((given >> 16) & 0xf) == 0xf)
6229 {
6230 bfd_vma offset = (given & 0xff) * 4;
6231
6232 if ((given & (1 << 23)) == 0)
6233 offset = - offset;
6234 func (stream, "\t; ");
6235 info->print_address_func ((pc & ~3) + 4 + offset, info);
6236 }
6237 break;
6238
c19d1205
ZW		 6239 default:
6240 abort ();
6241 }
6242 }
05413229
NC		 6243
6244 if (value_in_comment > 32 || value_in_comment < -16)
6245 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 6246
6247 if (is_unpredictable)
6248 func (stream, UNPREDICTABLE_INSTRUCTION);
6249
4a5329c6 6250 return;
c19d1205 6251 }
252b5132 6252
58efb6c0 6253 /* No match. */
0b347048
TC		 6254 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
6255 return;
252b5132
RH		 6256}
6257
e821645d
DJ		 6258/* Print data bytes on INFO->STREAM. */
6259
6260static void
fe56b6ce
NC		 6261print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6262 struct disassemble_info *info,
e821645d
DJ		 6263 long given)
6264{
6265 switch (info->bytes_per_chunk)
6266 {
6267 case 1:
6268 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6269 break;
6270 case 2:
6271 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6272 break;
6273 case 4:
6274 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6275 break;
6276 default:
6277 abort ();
6278 }
6279}
6280
22a398e1 6281/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 6282 being displayed in symbol relative addresses.
6283
6284 Also disallow private symbol, with __tagsym$$ prefix,
6285 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 6286
6287bfd_boolean
6288arm_symbol_is_valid (asymbol * sym,
6289 struct disassemble_info * info ATTRIBUTE_UNUSED)
6290{
6291 const char * name;
43e65147 6292
22a398e1
NC		 6293 if (sym == NULL)
6294 return FALSE;
6295
6296 name = bfd_asymbol_name (sym);
6297
d8282f0e 6298 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 6299}
6300
65b48a81 6301/* Parse the string of disassembler options. */
baf0cc5e 6302
65b48a81 6303static void
f995bbe8 6304parse_arm_disassembler_options (const char *options)
dd92f639 6305{
f995bbe8 6306 const char *opt;
b34976b6 6307
65b48a81 6308 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 6309 {
65b48a81
PB		 6310 if (CONST_STRNEQ (opt, "reg-names-"))
6311 {
6312 unsigned int i;
6313 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6314 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
6315 {
6316 regname_selected = i;
6317 break;
6318 }
b34976b6 6319
65b48a81 6320 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 6321 /* xgettext: c-format */
6322 opcodes_error_handler (_("unrecognised register name set: %s"),
6323 opt);
65b48a81
PB		 6324 }
6325 else if (CONST_STRNEQ (opt, "force-thumb"))
6326 force_thumb = 1;
6327 else if (CONST_STRNEQ (opt, "no-force-thumb"))
6328 force_thumb = 0;
6329 else
a6743a54
AM		 6330 /* xgettext: c-format */
6331 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 6332 }
b34976b6 6333
dd92f639
NC		 6334 return;
6335}
6336
5bc5ae88
RL		 6337static bfd_boolean
6338mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6339 enum map_type *map_symbol);
6340
c22aaad1
PB		 6341/* Search back through the insn stream to determine if this instruction is
6342 conditionally executed. */
fe56b6ce 6343
c22aaad1 6344static void
fe56b6ce
NC		 6345find_ifthen_state (bfd_vma pc,
6346 struct disassemble_info *info,
c22aaad1
PB		 6347 bfd_boolean little)
6348{
6349 unsigned char b[2];
6350 unsigned int insn;
6351 int status;
6352 /* COUNT is twice the number of instructions seen. It will be odd if we
6353 just crossed an instruction boundary. */
6354 int count;
6355 int it_count;
6356 unsigned int seen_it;
6357 bfd_vma addr;
6358
6359 ifthen_address = pc;
6360 ifthen_state = 0;
6361
6362 addr = pc;
6363 count = 1;
6364 it_count = 0;
6365 seen_it = 0;
6366 /* Scan backwards looking for IT instructions, keeping track of where
6367 instruction boundaries are. We don't know if something is actually an
6368 IT instruction until we find a definite instruction boundary. */
6369 for (;;)
6370 {
fe56b6ce 6371 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 6372 {
6373 /* A symbol must be on an instruction boundary, and will not
6374 be within an IT block. */
6375 if (seen_it && (count & 1))
6376 break;
6377
6378 return;
6379 }
6380 addr -= 2;
fe56b6ce 6381 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 6382 if (status)
6383 return;
6384
6385 if (little)
6386 insn = (b[0]) | (b[1] << 8);
6387 else
6388 insn = (b[1]) | (b[0] << 8);
6389 if (seen_it)
6390 {
6391 if ((insn & 0xf800) < 0xe800)
6392 {
6393 /* Addr + 2 is an instruction boundary. See if this matches
6394 the expected boundary based on the position of the last
6395 IT candidate. */
6396 if (count & 1)
6397 break;
6398 seen_it = 0;
6399 }
6400 }
6401 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6402 {
5bc5ae88
RL		 6403 enum map_type type = MAP_ARM;
6404 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6405
6406 if (!found || (found && type == MAP_THUMB))
6407 {
6408 /* This could be an IT instruction. */
6409 seen_it = insn;
6410 it_count = count >> 1;
6411 }
c22aaad1
PB		 6412 }
6413 if ((insn & 0xf800) >= 0xe800)
6414 count++;
6415 else
6416 count = (count + 2) | 1;
6417 /* IT blocks contain at most 4 instructions. */
6418 if (count >= 8 && !seen_it)
6419 return;
6420 }
6421 /* We found an IT instruction. */
6422 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6423 if ((ifthen_state & 0xf) == 0)
6424 ifthen_state = 0;
6425}
6426
b0e28b39
DJ		 6427/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6428 mapping symbol. */
6429
6430static int
6431is_mapping_symbol (struct disassemble_info *info, int n,
6432 enum map_type *map_type)
6433{
6434 const char *name;
6435
6436 name = bfd_asymbol_name (info->symtab[n]);
6437 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6438 && (name[2] == 0 || name[2] == '.'))
6439 {
6440 *map_type = ((name[1] == 'a') ? MAP_ARM
6441 : (name[1] == 't') ? MAP_THUMB
6442 : MAP_DATA);
6443 return TRUE;
6444 }
6445
6446 return FALSE;
6447}
6448
6449/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6450 Returns nonzero if *MAP_TYPE was set. */
6451
6452static int
6453get_map_sym_type (struct disassemble_info *info,
6454 int n,
6455 enum map_type *map_type)
6456{
6457 /* If the symbol is in a different section, ignore it. */
6458 if (info->section != NULL && info->section != info->symtab[n]->section)
6459 return FALSE;
6460
6461 return is_mapping_symbol (info, n, map_type);
6462}
6463
6464/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 6465 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 6466
6467static int
fe56b6ce
NC		 6468get_sym_code_type (struct disassemble_info *info,
6469 int n,
e821645d 6470 enum map_type *map_type)
2087ad84
PB		 6471{
6472 elf_symbol_type *es;
6473 unsigned int type;
b0e28b39
DJ		 6474
6475 /* If the symbol is in a different section, ignore it. */
6476 if (info->section != NULL && info->section != info->symtab[n]->section)
6477 return FALSE;
2087ad84 6478
e821645d 6479 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 6480 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6481
6482 /* If the symbol has function type then use that. */
34e77a92 6483 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 6484 {
39d911fc
TP		 6485 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6486 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 6487 *map_type = MAP_THUMB;
6488 else
6489 *map_type = MAP_ARM;
2087ad84
PB		 6490 return TRUE;
6491 }
6492
2087ad84
PB		 6493 return FALSE;
6494}
6495
5bc5ae88
RL		 6496/* Search the mapping symbol state for instruction at pc. This is only
6497 applicable for elf target.
6498
6499 There is an assumption Here, info->private_data contains the correct AND
6500 up-to-date information about current scan process. The information will be
6501 used to speed this search process.
6502
6503 Return TRUE if the mapping state can be determined, and map_symbol
6504 will be updated accordingly. Otherwise, return FALSE. */
6505
6506static bfd_boolean
6507mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6508 enum map_type *map_symbol)
6509{
796d6298
TC		 6510 bfd_vma addr, section_vma = 0;
6511 int n, last_sym = -1;
5bc5ae88 6512 bfd_boolean found = FALSE;
796d6298
TC		 6513 bfd_boolean can_use_search_opt_p = FALSE;
6514
6515 /* Default to DATA. A text section is required by the ABI to contain an
6516 INSN mapping symbol at the start. A data section has no such
6517 requirement, hence if no mapping symbol is found the section must
6518 contain only data. This however isn't very useful if the user has
6519 fully stripped the binaries. If this is the case use the section
6520 attributes to determine the default. If we have no section default to
6521 INSN as well, as we may be disassembling some raw bytes on a baremetal
6522 HEX file or similar. */
6523 enum map_type type = MAP_DATA;
6524 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
6525 type = MAP_ARM;
5bc5ae88
RL		 6526 struct arm_private_data *private_data;
6527
796d6298 6528 if (info->private_data == NULL
5bc5ae88
RL		 6529 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6530 return FALSE;
6531
6532 private_data = info->private_data;
5bc5ae88 6533
796d6298
TC		 6534 /* First, look for mapping symbols. */
6535 if (info->symtab_size != 0)
6536 {
6537 if (pc <= private_data->last_mapping_addr)
6538 private_data->last_mapping_sym = -1;
6539
6540 /* Start scanning at the start of the function, or wherever
6541 we finished last time. */
6542 n = info->symtab_pos + 1;
6543
6544 /* If the last stop offset is different from the current one it means we
6545 are disassembling a different glob of bytes. As such the optimization
6546 would not be safe and we should start over. */
6547 can_use_search_opt_p
6548 = private_data->last_mapping_sym >= 0
6549 && info->stop_offset == private_data->last_stop_offset;
6550
6551 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
6552 n = private_data->last_mapping_sym;
6553
6554 /* Look down while we haven't passed the location being disassembled.
6555 The reason for this is that there's no defined order between a symbol
6556 and an mapping symbol that may be at the same address. We may have to
6557 look at least one position ahead. */
6558 for (; n < info->symtab_size; n++)
6559 {
6560 addr = bfd_asymbol_value (info->symtab[n]);
6561 if (addr > pc)
6562 break;
6563 if (get_map_sym_type (info, n, &type))
6564 {
6565 last_sym = n;
6566 found = TRUE;
6567 }
6568 }
5bc5ae88 6569
796d6298
TC		 6570 if (!found)
6571 {
6572 n = info->symtab_pos;
6573 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
6574 n = private_data->last_mapping_sym;
6575
6576 /* No mapping symbol found at this address. Look backwards
6577 for a preceeding one, but don't go pass the section start
6578 otherwise a data section with no mapping symbol can pick up
6579 a text mapping symbol of a preceeding section. The documentation
6580 says section can be NULL, in which case we will seek up all the
6581 way to the top. */
6582 if (info->section)
6583 section_vma = info->section->vma;
6584
6585 for (; n >= 0; n--)
6586 {
6587 addr = bfd_asymbol_value (info->symtab[n]);
6588 if (addr < section_vma)
6589 break;
6590
6591 if (get_map_sym_type (info, n, &type))
6592 {
6593 last_sym = n;
6594 found = TRUE;
6595 break;
6596 }
6597 }
6598 }
6599 }
6600
6601 /* If no mapping symbol was found, try looking up without a mapping
6602 symbol. This is done by walking up from the current PC to the nearest
6603 symbol. We don't actually have to loop here since symtab_pos will
6604 contain the nearest symbol already. */
6605 if (!found)
5bc5ae88 6606 {
796d6298
TC		 6607 n = info->symtab_pos;
6608 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 6609 {
796d6298
TC		 6610 last_sym = n;
6611 found = TRUE;
5bc5ae88
RL		 6612 }
6613 }
6614
796d6298
TC		 6615 private_data->last_mapping_sym = last_sym;
6616 private_data->last_type = type;
6617 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 6618
6619 *map_symbol = type;
6620 return found;
6621}
6622
0313a2b8
NC		 6623/* Given a bfd_mach_arm_XXX value, this function fills in the fields
6624 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 6625 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 6626
6627 FIXME: This could more efficiently implemented as a constant array,
6628 although it would also be less robust. */
6629
6630static void
6631select_arm_features (unsigned long mach,
6632 arm_feature_set * features)
6633{
c0c468d5
TP		 6634 arm_feature_set arch_fset;
6635 const arm_feature_set fpu_any = FPU_ANY;
6636
1af1dd51
MW		 6637#undef ARM_SET_FEATURES
6638#define ARM_SET_FEATURES(FSET) \
6639 { \
6640 const arm_feature_set fset = FSET; \
c0c468d5 6641 arch_fset = fset; \
1af1dd51 6642 }
823d2571 6643
c0c468d5
TP		 6644 /* When several architecture versions share the same bfd_mach_arm_XXX value
6645 the most featureful is chosen. */
0313a2b8
NC		 6646 switch (mach)
6647 {
c0c468d5
TP		 6648 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6649 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6650 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6651 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6652 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6653 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6654 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6655 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6656 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6657 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 6658 case bfd_mach_arm_ep9312:
c0c468d5
TP		 6659 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6660 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 6661 break;
c0c468d5
TP		 6662 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6663 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6664 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
6665 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
6666 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
6667 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
6668 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
6669 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
6670 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
6671 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
6672 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
6673 case bfd_mach_arm_8:
6674 {
0632eeea
SD		 6675 /* Add bits for extensions that Armv8.5-A recognizes. */
6676 arm_feature_set armv8_5_ext_fset
6677 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
6678 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
6679 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
c0c468d5
TP		 6680 break;
6681 }
6682 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
6683 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
6684 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
031254f2 6685 case bfd_mach_arm_8_1M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN); break;
c0c468d5
TP		 6686 /* If the machine type is unknown allow all architecture types and all
6687 extensions. */
6688 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 6689 default:
6690 abort ();
6691 }
1af1dd51 6692#undef ARM_SET_FEATURES
c0c468d5
TP		 6693
6694 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
6695 and thus on bfd_mach_arm_XXX value. Therefore for a given
6696 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
6697 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 6698}
6699
6700
58efb6c0
NC		 6701/* NOTE: There are no checks in these routines that
6702 the relevant number of data bytes exist. */
baf0cc5e 6703
58efb6c0 6704static int
4a5329c6 6705print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 6706{
c19d1205
ZW		 6707 unsigned char b[4];
6708 long given;
6709 int status;
e821645d 6710 int is_thumb = FALSE;
b0e28b39 6711 int is_data = FALSE;
bd2e2557 6712 int little_code;
e821645d 6713 unsigned int size = 4;
4a5329c6 6714 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 6715 bfd_boolean found = FALSE;
b0e28b39 6716 struct arm_private_data *private_data;
58efb6c0 6717
dd92f639
NC		 6718 if (info->disassembler_options)
6719 {
65b48a81 6720 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 6721
58efb6c0 6722 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 6723 info->disassembler_options = NULL;
6724 }
b34976b6 6725
0313a2b8
NC		 6726 /* PR 10288: Control which instructions will be disassembled. */
6727 if (info->private_data == NULL)
6728 {
b0e28b39 6729 static struct arm_private_data private;
0313a2b8
NC		 6730
6731 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6732 /* If the user did not use the -m command line switch then default to
6733 disassembling all types of ARM instruction.
43e65147 6734
0313a2b8
NC		 6735 The info->mach value has to be ignored as this will be based on
6736 the default archictecture for the target and/or hints in the notes
6737 section, but it will never be greater than the current largest arm
6738 machine value (iWMMXt2), which is only equivalent to the V5TE
6739 architecture. ARM architectures have advanced beyond the machine
6740 value encoding, and these newer architectures would be ignored if
6741 the machine value was used.
6742
6743 Ie the -m switch is used to restrict which instructions will be
6744 disassembled. If it is necessary to use the -m switch to tell
6745 objdump that an ARM binary is being disassembled, eg because the
6746 input is a raw binary file, but it is also desired to disassemble
6747 all ARM instructions then use "-marm". This will select the
6748 "unknown" arm architecture which is compatible with any ARM
6749 instruction. */
6750 info->mach = bfd_mach_arm_unknown;
6751
6752 /* Compute the architecture bitmask from the machine number.
6753 Note: This assumes that the machine number will not change
6754 during disassembly.... */
b0e28b39 6755 select_arm_features (info->mach, & private.features);
0313a2b8 6756
1fbaefec
PB		 6757 private.last_mapping_sym = -1;
6758 private.last_mapping_addr = 0;
796d6298 6759 private.last_stop_offset = 0;
b0e28b39
DJ		 6760
6761 info->private_data = & private;
0313a2b8 6762 }
b0e28b39
DJ		 6763
6764 private_data = info->private_data;
6765
bd2e2557
SS		 6766 /* Decide if our code is going to be little-endian, despite what the
6767 function argument might say. */
6768 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6769
b0e28b39
DJ		 6770 /* For ELF, consult the symbol table to determine what kind of code
6771 or data we have. */
8977d4b2 6772 if (info->symtab_size != 0
e821645d
DJ		 6773 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6774 {
6775 bfd_vma addr;
796d6298 6776 int n;
e821645d 6777 int last_sym = -1;
b0e28b39 6778 enum map_type type = MAP_ARM;
e821645d 6779
796d6298
TC		 6780 found = mapping_symbol_for_insn (pc, info, &type);
6781 last_sym = private_data->last_mapping_sym;
e821645d 6782
1fbaefec
PB		 6783 is_thumb = (private_data->last_type == MAP_THUMB);
6784 is_data = (private_data->last_type == MAP_DATA);
b34976b6 6785
e821645d
DJ		 6786 /* Look a little bit ahead to see if we should print out
6787 two or four bytes of data. If there's a symbol,
6788 mapping or otherwise, after two bytes then don't
6789 print more. */
6790 if (is_data)
6791 {
6792 size = 4 - (pc & 3);
6793 for (n = last_sym + 1; n < info->symtab_size; n++)
6794 {
6795 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 6796 if (addr > pc
6797 && (info->section == NULL
6798 || info->section == info->symtab[n]->section))
e821645d
DJ		 6799 {
6800 if (addr - pc < size)
6801 size = addr - pc;
6802 break;
6803 }
6804 }
6805 /* If the next symbol is after three bytes, we need to
6806 print only part of the data, so that we can use either
6807 .byte or .short. */
6808 if (size == 3)
6809 size = (pc & 1) ? 1 : 2;
6810 }
6811 }
6812
6813 if (info->symbols != NULL)
252b5132 6814 {
5876e06d
NC		 6815 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6816 {
2f0ca46a 6817 coff_symbol_type * cs;
b34976b6 6818
5876e06d
NC		 6819 cs = coffsymbol (*info->symbols);
6820 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6821 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6822 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6823 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6824 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6825 }
e821645d
DJ		 6826 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6827 && !found)
5876e06d 6828 {
2087ad84
PB		 6829 /* If no mapping symbol has been found then fall back to the type
6830 of the function symbol. */
e821645d
DJ		 6831 elf_symbol_type * es;
6832 unsigned int type;
2087ad84 6833
e821645d
DJ		 6834 es = *(elf_symbol_type **)(info->symbols);
6835 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 6836
39d911fc
TP		 6837 is_thumb =
6838 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6839 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 6840 }
e49d43ff
TG		 6841 else if (bfd_asymbol_flavour (*info->symbols)
6842 == bfd_target_mach_o_flavour)
6843 {
6844 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6845
6846 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6847 }
5876e06d 6848 }
b34976b6 6849
e821645d
DJ		 6850 if (force_thumb)
6851 is_thumb = TRUE;
6852
b8f9ee44
CL		 6853 if (is_data)
6854 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6855 else
6856 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6857
c19d1205 6858 info->bytes_per_line = 4;
252b5132 6859
1316c8b3
NC		 6860 /* PR 10263: Disassemble data if requested to do so by the user. */
6861 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 6862 {
6863 int i;
6864
1316c8b3 6865 /* Size was already set above. */
e821645d
DJ		 6866 info->bytes_per_chunk = size;
6867 printer = print_insn_data;
6868
fe56b6ce 6869 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 6870 given = 0;
6871 if (little)
6872 for (i = size - 1; i >= 0; i--)
6873 given = b[i] | (given << 8);
6874 else
6875 for (i = 0; i < (int) size; i++)
6876 given = b[i] | (given << 8);
6877 }
6878 else if (!is_thumb)
252b5132 6879 {
c19d1205
ZW		 6880 /* In ARM mode endianness is a straightforward issue: the instruction
6881 is four bytes long and is either ordered 0123 or 3210. */
6882 printer = print_insn_arm;
6883 info->bytes_per_chunk = 4;
4a5329c6 6884 size = 4;
c19d1205 6885
0313a2b8 6886 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 6887 if (little_code)
c19d1205
ZW		 6888 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6889 else
6890 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 6891 }
58efb6c0 6892 else
252b5132 6893 {
c19d1205
ZW		 6894 /* In Thumb mode we have the additional wrinkle of two
6895 instruction lengths. Fortunately, the bits that determine
6896 the length of the current instruction are always to be found
6897 in the first two bytes. */
4a5329c6 6898 printer = print_insn_thumb16;
c19d1205 6899 info->bytes_per_chunk = 2;
4a5329c6
ZW		 6900 size = 2;
6901
fe56b6ce 6902 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 6903 if (little_code)
9a2ff3f5
AM		 6904 given = (b[0]) | (b[1] << 8);
6905 else
6906 given = (b[1]) | (b[0] << 8);
6907
c19d1205 6908 if (!status)
252b5132 6909 {
c19d1205
ZW		 6910 /* These bit patterns signal a four-byte Thumb
6911 instruction. */
6912 if ((given & 0xF800) == 0xF800
6913 || (given & 0xF800) == 0xF000
6914 || (given & 0xF800) == 0xE800)
252b5132 6915 {
0313a2b8 6916 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 6917 if (little_code)
c19d1205 6918 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 6919 else
c19d1205
ZW		 6920 given = (b[1]) | (b[0] << 8) | (given << 16);
6921
6922 printer = print_insn_thumb32;
4a5329c6 6923 size = 4;
252b5132 6924 }
252b5132 6925 }
c22aaad1
PB		 6926
6927 if (ifthen_address != pc)
0313a2b8 6928 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 6929
6930 if (ifthen_state)
6931 {
6932 if ((ifthen_state & 0xf) == 0x8)
6933 ifthen_next_state = 0;
6934 else
6935 ifthen_next_state = (ifthen_state & 0xe0)
6936 | ((ifthen_state & 0xf) << 1);
6937 }
252b5132 6938 }
b34976b6 6939
c19d1205
ZW		 6940 if (status)
6941 {
6942 info->memory_error_func (status, pc, info);
6943 return -1;
6944 }
6a56ec7e
NC		 6945 if (info->flags & INSN_HAS_RELOC)
6946 /* If the instruction has a reloc associated with it, then
6947 the offset field in the instruction will actually be the
6948 addend for the reloc. (We are using REL type relocs).
6949 In such cases, we can ignore the pc when computing
6950 addresses, since the addend is not currently pc-relative. */
6951 pc = 0;
b34976b6 6952
4a5329c6 6953 printer (pc, info, given);
c22aaad1
PB		 6954
6955 if (is_thumb)
6956 {
6957 ifthen_state = ifthen_next_state;
6958 ifthen_address += size;
6959 }
4a5329c6 6960 return size;
252b5132
RH		 6961}
6962
6963int
4a5329c6 6964print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 6965{
bd2e2557
SS		 6966 /* Detect BE8-ness and record it in the disassembler info. */
6967 if (info->flavour == bfd_target_elf_flavour
6968 && info->section != NULL
6969 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6970 info->endian_code = BFD_ENDIAN_LITTLE;
6971
b34976b6 6972 return print_insn (pc, info, FALSE);
58efb6c0 6973}
01c7f630 6974
58efb6c0 6975int
4a5329c6 6976print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 6977{
b34976b6 6978 return print_insn (pc, info, TRUE);
58efb6c0 6979}
252b5132 6980
471b9d15 6981const disasm_options_and_args_t *
65b48a81
PB		 6982disassembler_options_arm (void)
6983{
471b9d15 6984 static disasm_options_and_args_t *opts_and_args;
65b48a81 6985
471b9d15 6986 if (opts_and_args == NULL)
65b48a81 6987 {
471b9d15 6988 disasm_options_t *opts;
65b48a81 6989 unsigned int i;
471b9d15
MR		 6990
6991 opts_and_args = XNEW (disasm_options_and_args_t);
6992 opts_and_args->args = NULL;
6993
6994 opts = &opts_and_args->options;
65b48a81
PB		 6995 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6996 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 6997 opts->arg = NULL;
65b48a81
PB		 6998 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6999 {
7000 opts->name[i] = regnames[i].name;
7001 if (regnames[i].description != NULL)
7002 opts->description[i] = _(regnames[i].description);
7003 else
7004 opts->description[i] = NULL;
7005 }
7006 /* The array we return must be NULL terminated. */
7007 opts->name[i] = NULL;
7008 opts->description[i] = NULL;
7009 }
7010
471b9d15 7011 return opts_and_args;
65b48a81
PB		 7012}
7013
58efb6c0 7014void
4a5329c6 7015print_arm_disassembler_options (FILE *stream)
58efb6c0 7016{
65b48a81 7017 unsigned int i, max_len = 0;
58efb6c0
NC		 7018 fprintf (stream, _("\n\
7019The following ARM specific disassembler options are supported for use with\n\
7020the -M switch:\n"));
b34976b6 7021
65b48a81
PB		 7022 for (i = 0; i < NUM_ARM_OPTIONS; i++)
7023 {
7024 unsigned int len = strlen (regnames[i].name);
7025 if (max_len < len)
7026 max_len = len;
7027 }
58efb6c0 7028
65b48a81
PB		 7029 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
7030 fprintf (stream, " %s%*c %s\n",
7031 regnames[i].name,
7032 (int)(max_len - strlen (regnames[i].name)), ' ',
7033 _(regnames[i].description));
252b5132 7034}
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